1 /* 2 * Tsi721 PCIExpress-to-SRIO bridge definitions 3 * 4 * Copyright 2011, Integrated Device Technology, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program; if not, write to the Free Software Foundation, Inc., 59 18 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #ifndef __TSI721_H 22 #define __TSI721_H 23 24 #define DRV_NAME "tsi721" 25 26 #define DEFAULT_HOPCOUNT 0xff 27 #define DEFAULT_DESTID 0xff 28 29 /* PCI device ID */ 30 #define PCI_DEVICE_ID_TSI721 0x80ab 31 32 #define BAR_0 0 33 #define BAR_1 1 34 #define BAR_2 2 35 #define BAR_4 4 36 37 #define TSI721_PC2SR_BARS 2 38 #define TSI721_PC2SR_WINS 8 39 #define TSI721_PC2SR_ZONES 8 40 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */ 41 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */ 42 #define IDB_QSIZE 512 /* Inbound Doorbell Queue size */ 43 44 /* Memory space sizes */ 45 #define TSI721_REG_SPACE_SIZE (512 * 1024) /* 512K */ 46 #define TSI721_DB_WIN_SIZE (16 * 1024 * 1024) /* 16MB */ 47 48 #define RIO_TT_CODE_8 0x00000000 49 #define RIO_TT_CODE_16 0x00000001 50 51 #define TSI721_DMA_MAXCH 8 52 #define TSI721_DMA_MINSTSSZ 32 53 #define TSI721_DMA_STSBLKSZ 8 54 55 #define TSI721_SRIO_MAXCH 8 56 57 #define DBELL_SID(buf) (((u8)buf[2] << 8) | (u8)buf[3]) 58 #define DBELL_TID(buf) (((u8)buf[4] << 8) | (u8)buf[5]) 59 #define DBELL_INF(buf) (((u8)buf[0] << 8) | (u8)buf[1]) 60 61 #define TSI721_RIO_PW_MSG_SIZE 16 /* Tsi721 saves only 16 bytes of PW msg */ 62 63 /* Register definitions */ 64 65 /* 66 * Registers in PCIe configuration space 67 */ 68 69 #define TSI721_PCIECFG_MSIXTBL 0x0a4 70 #define TSI721_MSIXTBL_OFFSET 0x2c000 71 #define TSI721_PCIECFG_MSIXPBA 0x0a8 72 #define TSI721_MSIXPBA_OFFSET 0x2a000 73 #define TSI721_PCIECFG_EPCTL 0x400 74 75 /* 76 * Event Management Registers 77 */ 78 79 #define TSI721_RIO_EM_INT_STAT 0x10910 80 #define TSI721_RIO_EM_INT_STAT_PW_RX 0x00010000 81 82 #define TSI721_RIO_EM_INT_ENABLE 0x10914 83 #define TSI721_RIO_EM_INT_ENABLE_PW_RX 0x00010000 84 85 #define TSI721_RIO_EM_DEV_INT_EN 0x10930 86 #define TSI721_RIO_EM_DEV_INT_EN_INT 0x00000001 87 88 /* 89 * Port-Write Block Registers 90 */ 91 92 #define TSI721_RIO_PW_CTL 0x10a04 93 #define TSI721_RIO_PW_CTL_PW_TIMER 0xf0000000 94 #define TSI721_RIO_PW_CTL_PWT_DIS (0 << 28) 95 #define TSI721_RIO_PW_CTL_PWT_103 (1 << 28) 96 #define TSI721_RIO_PW_CTL_PWT_205 (1 << 29) 97 #define TSI721_RIO_PW_CTL_PWT_410 (1 << 30) 98 #define TSI721_RIO_PW_CTL_PWT_820 (1 << 31) 99 #define TSI721_RIO_PW_CTL_PWC_MODE 0x01000000 100 #define TSI721_RIO_PW_CTL_PWC_CONT 0x00000000 101 #define TSI721_RIO_PW_CTL_PWC_REL 0x01000000 102 103 #define TSI721_RIO_PW_RX_STAT 0x10a10 104 #define TSI721_RIO_PW_RX_STAT_WR_SIZE 0x0000f000 105 #define TSI_RIO_PW_RX_STAT_WDPTR 0x00000100 106 #define TSI721_RIO_PW_RX_STAT_PW_SHORT 0x00000008 107 #define TSI721_RIO_PW_RX_STAT_PW_TRUNC 0x00000004 108 #define TSI721_RIO_PW_RX_STAT_PW_DISC 0x00000002 109 #define TSI721_RIO_PW_RX_STAT_PW_VAL 0x00000001 110 111 #define TSI721_RIO_PW_RX_CAPT(x) (0x10a20 + (x)*4) 112 113 /* 114 * Inbound Doorbells 115 */ 116 117 #define TSI721_IDB_ENTRY_SIZE 64 118 119 #define TSI721_IDQ_CTL(x) (0x20000 + (x) * 0x1000) 120 #define TSI721_IDQ_SUSPEND 0x00000002 121 #define TSI721_IDQ_INIT 0x00000001 122 123 #define TSI721_IDQ_STS(x) (0x20004 + (x) * 0x1000) 124 #define TSI721_IDQ_RUN 0x00200000 125 126 #define TSI721_IDQ_MASK(x) (0x20008 + (x) * 0x1000) 127 #define TSI721_IDQ_MASK_MASK 0xffff0000 128 #define TSI721_IDQ_MASK_PATT 0x0000ffff 129 130 #define TSI721_IDQ_RP(x) (0x2000c + (x) * 0x1000) 131 #define TSI721_IDQ_RP_PTR 0x0007ffff 132 133 #define TSI721_IDQ_WP(x) (0x20010 + (x) * 0x1000) 134 #define TSI721_IDQ_WP_PTR 0x0007ffff 135 136 #define TSI721_IDQ_BASEL(x) (0x20014 + (x) * 0x1000) 137 #define TSI721_IDQ_BASEL_ADDR 0xffffffc0 138 #define TSI721_IDQ_BASEU(x) (0x20018 + (x) * 0x1000) 139 #define TSI721_IDQ_SIZE(x) (0x2001c + (x) * 0x1000) 140 #define TSI721_IDQ_SIZE_VAL(size) (__fls(size) - 4) 141 #define TSI721_IDQ_SIZE_MIN 512 142 #define TSI721_IDQ_SIZE_MAX (512 * 1024) 143 144 #define TSI721_SR_CHINT(x) (0x20040 + (x) * 0x1000) 145 #define TSI721_SR_CHINTE(x) (0x20044 + (x) * 0x1000) 146 #define TSI721_SR_CHINTSET(x) (0x20048 + (x) * 0x1000) 147 #define TSI721_SR_CHINT_ODBOK 0x00000020 148 #define TSI721_SR_CHINT_IDBQRCV 0x00000010 149 #define TSI721_SR_CHINT_SUSP 0x00000008 150 #define TSI721_SR_CHINT_ODBTO 0x00000004 151 #define TSI721_SR_CHINT_ODBRTRY 0x00000002 152 #define TSI721_SR_CHINT_ODBERR 0x00000001 153 #define TSI721_SR_CHINT_ALL 0x0000003f 154 155 #define TSI721_IBWIN_NUM 8 156 157 #define TSI721_IBWIN_LB(x) (0x29000 + (x) * 0x20) 158 #define TSI721_IBWIN_LB_BA 0xfffff000 159 #define TSI721_IBWIN_LB_WEN 0x00000001 160 161 #define TSI721_IBWIN_UB(x) (0x29004 + (x) * 0x20) 162 #define TSI721_IBWIN_SZ(x) (0x29008 + (x) * 0x20) 163 #define TSI721_IBWIN_SZ_SIZE 0x00001f00 164 #define TSI721_IBWIN_SIZE(size) (__fls(size) - 12) 165 166 #define TSI721_IBWIN_TLA(x) (0x2900c + (x) * 0x20) 167 #define TSI721_IBWIN_TLA_ADD 0xfffff000 168 #define TSI721_IBWIN_TUA(x) (0x29010 + (x) * 0x20) 169 170 #define TSI721_SR2PC_GEN_INTE 0x29800 171 #define TSI721_SR2PC_PWE 0x29804 172 #define TSI721_SR2PC_GEN_INT 0x29808 173 174 #define TSI721_DEV_INTE 0x29840 175 #define TSI721_DEV_INT 0x29844 176 #define TSI721_DEV_INTSET 0x29848 177 #define TSI721_DEV_INT_BDMA_CH 0x00002000 178 #define TSI721_DEV_INT_BDMA_NCH 0x00001000 179 #define TSI721_DEV_INT_SMSG_CH 0x00000800 180 #define TSI721_DEV_INT_SMSG_NCH 0x00000400 181 #define TSI721_DEV_INT_SR2PC_CH 0x00000200 182 #define TSI721_DEV_INT_SRIO 0x00000020 183 184 #define TSI721_DEV_CHAN_INTE 0x2984c 185 #define TSI721_DEV_CHAN_INT 0x29850 186 187 #define TSI721_INT_SR2PC_CHAN_M 0xff000000 188 #define TSI721_INT_SR2PC_CHAN(x) (1 << (24 + (x))) 189 #define TSI721_INT_IMSG_CHAN_M 0x00ff0000 190 #define TSI721_INT_IMSG_CHAN(x) (1 << (16 + (x))) 191 #define TSI721_INT_OMSG_CHAN_M 0x0000ff00 192 #define TSI721_INT_OMSG_CHAN(x) (1 << (8 + (x))) 193 #define TSI721_INT_BDMA_CHAN_M 0x000000ff 194 #define TSI721_INT_BDMA_CHAN(x) (1 << (x)) 195 196 /* 197 * PC2SR block registers 198 */ 199 #define TSI721_OBWIN_NUM TSI721_PC2SR_WINS 200 201 #define TSI721_OBWINLB(x) (0x40000 + (x) * 0x20) 202 #define TSI721_OBWINLB_BA 0xffff8000 203 #define TSI721_OBWINLB_WEN 0x00000001 204 205 #define TSI721_OBWINUB(x) (0x40004 + (x) * 0x20) 206 207 #define TSI721_OBWINSZ(x) (0x40008 + (x) * 0x20) 208 #define TSI721_OBWINSZ_SIZE 0x00001f00 209 #define TSI721_OBWIN_SIZE(size) (__fls(size) - 15) 210 211 #define TSI721_ZONE_SEL 0x41300 212 #define TSI721_ZONE_SEL_RD_WRB 0x00020000 213 #define TSI721_ZONE_SEL_GO 0x00010000 214 #define TSI721_ZONE_SEL_WIN 0x00000038 215 #define TSI721_ZONE_SEL_ZONE 0x00000007 216 217 #define TSI721_LUT_DATA0 0x41304 218 #define TSI721_LUT_DATA0_ADD 0xfffff000 219 #define TSI721_LUT_DATA0_RDTYPE 0x00000f00 220 #define TSI721_LUT_DATA0_NREAD 0x00000100 221 #define TSI721_LUT_DATA0_MNTRD 0x00000200 222 #define TSI721_LUT_DATA0_RDCRF 0x00000020 223 #define TSI721_LUT_DATA0_WRCRF 0x00000010 224 #define TSI721_LUT_DATA0_WRTYPE 0x0000000f 225 #define TSI721_LUT_DATA0_NWR 0x00000001 226 #define TSI721_LUT_DATA0_MNTWR 0x00000002 227 #define TSI721_LUT_DATA0_NWR_R 0x00000004 228 229 #define TSI721_LUT_DATA1 0x41308 230 231 #define TSI721_LUT_DATA2 0x4130c 232 #define TSI721_LUT_DATA2_HC 0xff000000 233 #define TSI721_LUT_DATA2_ADD65 0x000c0000 234 #define TSI721_LUT_DATA2_TT 0x00030000 235 #define TSI721_LUT_DATA2_DSTID 0x0000ffff 236 237 #define TSI721_PC2SR_INTE 0x41310 238 239 #define TSI721_DEVCTL 0x48004 240 #define TSI721_DEVCTL_SRBOOT_CMPL 0x00000004 241 242 #define TSI721_I2C_INT_ENABLE 0x49120 243 244 /* 245 * Block DMA Engine Registers 246 * x = 0..7 247 */ 248 249 #define TSI721_DMAC_BASE(x) (0x51000 + (x) * 0x1000) 250 251 #define TSI721_DMAC_DWRCNT 0x000 252 #define TSI721_DMAC_DRDCNT 0x004 253 254 #define TSI721_DMAC_CTL 0x008 255 #define TSI721_DMAC_CTL_SUSP 0x00000002 256 #define TSI721_DMAC_CTL_INIT 0x00000001 257 258 #define TSI721_DMAC_INT 0x00c 259 #define TSI721_DMAC_INT_STFULL 0x00000010 260 #define TSI721_DMAC_INT_DONE 0x00000008 261 #define TSI721_DMAC_INT_SUSP 0x00000004 262 #define TSI721_DMAC_INT_ERR 0x00000002 263 #define TSI721_DMAC_INT_IOFDONE 0x00000001 264 #define TSI721_DMAC_INT_ALL 0x0000001f 265 266 #define TSI721_DMAC_INTSET 0x010 267 268 #define TSI721_DMAC_STS 0x014 269 #define TSI721_DMAC_STS_ABORT 0x00400000 270 #define TSI721_DMAC_STS_RUN 0x00200000 271 #define TSI721_DMAC_STS_CS 0x001f0000 272 273 #define TSI721_DMAC_INTE 0x018 274 275 #define TSI721_DMAC_DPTRL 0x024 276 #define TSI721_DMAC_DPTRL_MASK 0xffffffe0 277 278 #define TSI721_DMAC_DPTRH 0x028 279 280 #define TSI721_DMAC_DSBL 0x02c 281 #define TSI721_DMAC_DSBL_MASK 0xffffffc0 282 283 #define TSI721_DMAC_DSBH 0x030 284 285 #define TSI721_DMAC_DSSZ 0x034 286 #define TSI721_DMAC_DSSZ_SIZE_M 0x0000000f 287 #define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4) 288 289 #define TSI721_DMAC_DSRP 0x038 290 #define TSI721_DMAC_DSRP_MASK 0x0007ffff 291 292 #define TSI721_DMAC_DSWP 0x03c 293 #define TSI721_DMAC_DSWP_MASK 0x0007ffff 294 295 #define TSI721_BDMA_INTE 0x5f000 296 297 /* 298 * Messaging definitions 299 */ 300 #define TSI721_MSG_BUFFER_SIZE RIO_MAX_MSG_SIZE 301 #define TSI721_MSG_MAX_SIZE RIO_MAX_MSG_SIZE 302 #define TSI721_IMSG_MAXCH 8 303 #define TSI721_IMSG_CHNUM TSI721_IMSG_MAXCH 304 #define TSI721_IMSGD_MIN_RING_SIZE 32 305 #define TSI721_IMSGD_RING_SIZE 512 306 307 #define TSI721_OMSG_CHNUM 4 /* One channel per MBOX */ 308 #define TSI721_OMSGD_MIN_RING_SIZE 32 309 #define TSI721_OMSGD_RING_SIZE 512 310 311 /* 312 * Outbound Messaging Engine Registers 313 * x = 0..7 314 */ 315 316 #define TSI721_OBDMAC_DWRCNT(x) (0x61000 + (x) * 0x1000) 317 318 #define TSI721_OBDMAC_DRDCNT(x) (0x61004 + (x) * 0x1000) 319 320 #define TSI721_OBDMAC_CTL(x) (0x61008 + (x) * 0x1000) 321 #define TSI721_OBDMAC_CTL_MASK 0x00000007 322 #define TSI721_OBDMAC_CTL_RETRY_THR 0x00000004 323 #define TSI721_OBDMAC_CTL_SUSPEND 0x00000002 324 #define TSI721_OBDMAC_CTL_INIT 0x00000001 325 326 #define TSI721_OBDMAC_INT(x) (0x6100c + (x) * 0x1000) 327 #define TSI721_OBDMAC_INTSET(x) (0x61010 + (x) * 0x1000) 328 #define TSI721_OBDMAC_INTE(x) (0x61018 + (x) * 0x1000) 329 #define TSI721_OBDMAC_INT_MASK 0x0000001F 330 #define TSI721_OBDMAC_INT_ST_FULL 0x00000010 331 #define TSI721_OBDMAC_INT_DONE 0x00000008 332 #define TSI721_OBDMAC_INT_SUSPENDED 0x00000004 333 #define TSI721_OBDMAC_INT_ERROR 0x00000002 334 #define TSI721_OBDMAC_INT_IOF_DONE 0x00000001 335 #define TSI721_OBDMAC_INT_ALL TSI721_OBDMAC_INT_MASK 336 337 #define TSI721_OBDMAC_STS(x) (0x61014 + (x) * 0x1000) 338 #define TSI721_OBDMAC_STS_MASK 0x007f0000 339 #define TSI721_OBDMAC_STS_ABORT 0x00400000 340 #define TSI721_OBDMAC_STS_RUN 0x00200000 341 #define TSI721_OBDMAC_STS_CS 0x001f0000 342 343 #define TSI721_OBDMAC_PWE(x) (0x6101c + (x) * 0x1000) 344 #define TSI721_OBDMAC_PWE_MASK 0x00000002 345 #define TSI721_OBDMAC_PWE_ERROR_EN 0x00000002 346 347 #define TSI721_OBDMAC_DPTRL(x) (0x61020 + (x) * 0x1000) 348 #define TSI721_OBDMAC_DPTRL_MASK 0xfffffff0 349 350 #define TSI721_OBDMAC_DPTRH(x) (0x61024 + (x) * 0x1000) 351 #define TSI721_OBDMAC_DPTRH_MASK 0xffffffff 352 353 #define TSI721_OBDMAC_DSBL(x) (0x61040 + (x) * 0x1000) 354 #define TSI721_OBDMAC_DSBL_MASK 0xffffffc0 355 356 #define TSI721_OBDMAC_DSBH(x) (0x61044 + (x) * 0x1000) 357 #define TSI721_OBDMAC_DSBH_MASK 0xffffffff 358 359 #define TSI721_OBDMAC_DSSZ(x) (0x61048 + (x) * 0x1000) 360 #define TSI721_OBDMAC_DSSZ_MASK 0x0000000f 361 362 #define TSI721_OBDMAC_DSRP(x) (0x6104c + (x) * 0x1000) 363 #define TSI721_OBDMAC_DSRP_MASK 0x0007ffff 364 365 #define TSI721_OBDMAC_DSWP(x) (0x61050 + (x) * 0x1000) 366 #define TSI721_OBDMAC_DSWP_MASK 0x0007ffff 367 368 #define TSI721_RQRPTO 0x60010 369 #define TSI721_RQRPTO_MASK 0x00ffffff 370 #define TSI721_RQRPTO_VAL 400 /* Response TO value */ 371 372 /* 373 * Inbound Messaging Engine Registers 374 * x = 0..7 375 */ 376 377 #define TSI721_IB_DEVID_GLOBAL 0xffff 378 #define TSI721_IBDMAC_FQBL(x) (0x61200 + (x) * 0x1000) 379 #define TSI721_IBDMAC_FQBL_MASK 0xffffffc0 380 381 #define TSI721_IBDMAC_FQBH(x) (0x61204 + (x) * 0x1000) 382 #define TSI721_IBDMAC_FQBH_MASK 0xffffffff 383 384 #define TSI721_IBDMAC_FQSZ_ENTRY_INX TSI721_IMSGD_RING_SIZE 385 #define TSI721_IBDMAC_FQSZ(x) (0x61208 + (x) * 0x1000) 386 #define TSI721_IBDMAC_FQSZ_MASK 0x0000000f 387 388 #define TSI721_IBDMAC_FQRP(x) (0x6120c + (x) * 0x1000) 389 #define TSI721_IBDMAC_FQRP_MASK 0x0007ffff 390 391 #define TSI721_IBDMAC_FQWP(x) (0x61210 + (x) * 0x1000) 392 #define TSI721_IBDMAC_FQWP_MASK 0x0007ffff 393 394 #define TSI721_IBDMAC_FQTH(x) (0x61214 + (x) * 0x1000) 395 #define TSI721_IBDMAC_FQTH_MASK 0x0007ffff 396 397 #define TSI721_IB_DEVID 0x60020 398 #define TSI721_IB_DEVID_MASK 0x0000ffff 399 400 #define TSI721_IBDMAC_CTL(x) (0x61240 + (x) * 0x1000) 401 #define TSI721_IBDMAC_CTL_MASK 0x00000003 402 #define TSI721_IBDMAC_CTL_SUSPEND 0x00000002 403 #define TSI721_IBDMAC_CTL_INIT 0x00000001 404 405 #define TSI721_IBDMAC_STS(x) (0x61244 + (x) * 0x1000) 406 #define TSI721_IBDMAC_STS_MASK 0x007f0000 407 #define TSI721_IBSMAC_STS_ABORT 0x00400000 408 #define TSI721_IBSMAC_STS_RUN 0x00200000 409 #define TSI721_IBSMAC_STS_CS 0x001f0000 410 411 #define TSI721_IBDMAC_INT(x) (0x61248 + (x) * 0x1000) 412 #define TSI721_IBDMAC_INTSET(x) (0x6124c + (x) * 0x1000) 413 #define TSI721_IBDMAC_INTE(x) (0x61250 + (x) * 0x1000) 414 #define TSI721_IBDMAC_INT_MASK 0x0000100f 415 #define TSI721_IBDMAC_INT_SRTO 0x00001000 416 #define TSI721_IBDMAC_INT_SUSPENDED 0x00000008 417 #define TSI721_IBDMAC_INT_PC_ERROR 0x00000004 418 #define TSI721_IBDMAC_INT_FQ_LOW 0x00000002 419 #define TSI721_IBDMAC_INT_DQ_RCV 0x00000001 420 #define TSI721_IBDMAC_INT_ALL TSI721_IBDMAC_INT_MASK 421 422 #define TSI721_IBDMAC_PWE(x) (0x61254 + (x) * 0x1000) 423 #define TSI721_IBDMAC_PWE_MASK 0x00001700 424 #define TSI721_IBDMAC_PWE_SRTO 0x00001000 425 #define TSI721_IBDMAC_PWE_ILL_FMT 0x00000400 426 #define TSI721_IBDMAC_PWE_ILL_DEC 0x00000200 427 #define TSI721_IBDMAC_PWE_IMP_SP 0x00000100 428 429 #define TSI721_IBDMAC_DQBL(x) (0x61300 + (x) * 0x1000) 430 #define TSI721_IBDMAC_DQBL_MASK 0xffffffc0 431 #define TSI721_IBDMAC_DQBL_ADDR 0xffffffc0 432 433 #define TSI721_IBDMAC_DQBH(x) (0x61304 + (x) * 0x1000) 434 #define TSI721_IBDMAC_DQBH_MASK 0xffffffff 435 436 #define TSI721_IBDMAC_DQRP(x) (0x61308 + (x) * 0x1000) 437 #define TSI721_IBDMAC_DQRP_MASK 0x0007ffff 438 439 #define TSI721_IBDMAC_DQWR(x) (0x6130c + (x) * 0x1000) 440 #define TSI721_IBDMAC_DQWR_MASK 0x0007ffff 441 442 #define TSI721_IBDMAC_DQSZ(x) (0x61314 + (x) * 0x1000) 443 #define TSI721_IBDMAC_DQSZ_MASK 0x0000000f 444 445 /* 446 * Messaging Engine Interrupts 447 */ 448 449 #define TSI721_SMSG_PWE 0x6a004 450 451 #define TSI721_SMSG_INTE 0x6a000 452 #define TSI721_SMSG_INT 0x6a008 453 #define TSI721_SMSG_INTSET 0x6a010 454 #define TSI721_SMSG_INT_MASK 0x0086ffff 455 #define TSI721_SMSG_INT_UNS_RSP 0x00800000 456 #define TSI721_SMSG_INT_ECC_NCOR 0x00040000 457 #define TSI721_SMSG_INT_ECC_COR 0x00020000 458 #define TSI721_SMSG_INT_ECC_NCOR_CH 0x0000ff00 459 #define TSI721_SMSG_INT_ECC_COR_CH 0x000000ff 460 461 #define TSI721_SMSG_ECC_LOG 0x6a014 462 #define TSI721_SMSG_ECC_LOG_MASK 0x00070007 463 #define TSI721_SMSG_ECC_LOG_ECC_NCOR_M 0x00070000 464 #define TSI721_SMSG_ECC_LOG_ECC_COR_M 0x00000007 465 466 #define TSI721_RETRY_GEN_CNT 0x6a100 467 #define TSI721_RETRY_GEN_CNT_MASK 0xffffffff 468 469 #define TSI721_RETRY_RX_CNT 0x6a104 470 #define TSI721_RETRY_RX_CNT_MASK 0xffffffff 471 472 #define TSI721_SMSG_ECC_COR_LOG(x) (0x6a300 + (x) * 4) 473 #define TSI721_SMSG_ECC_COR_LOG_MASK 0x000000ff 474 475 #define TSI721_SMSG_ECC_NCOR(x) (0x6a340 + (x) * 4) 476 #define TSI721_SMSG_ECC_NCOR_MASK 0x000000ff 477 478 /* 479 * Block DMA Descriptors 480 */ 481 482 struct tsi721_dma_desc { 483 __le32 type_id; 484 485 #define TSI721_DMAD_DEVID 0x0000ffff 486 #define TSI721_DMAD_CRF 0x00010000 487 #define TSI721_DMAD_PRIO 0x00060000 488 #define TSI721_DMAD_RTYPE 0x00780000 489 #define TSI721_DMAD_IOF 0x08000000 490 #define TSI721_DMAD_DTYPE 0xe0000000 491 492 __le32 bcount; 493 494 #define TSI721_DMAD_BCOUNT1 0x03ffffff /* if DTYPE == 1 */ 495 #define TSI721_DMAD_BCOUNT2 0x0000000f /* if DTYPE == 2 */ 496 #define TSI721_DMAD_TT 0x0c000000 497 #define TSI721_DMAD_RADDR0 0xc0000000 498 499 union { 500 __le32 raddr_lo; /* if DTYPE == (1 || 2) */ 501 __le32 next_lo; /* if DTYPE == 3 */ 502 }; 503 504 #define TSI721_DMAD_CFGOFF 0x00ffffff 505 #define TSI721_DMAD_HOPCNT 0xff000000 506 507 union { 508 __le32 raddr_hi; /* if DTYPE == (1 || 2) */ 509 __le32 next_hi; /* if DTYPE == 3 */ 510 }; 511 512 union { 513 struct { /* if DTYPE == 1 */ 514 __le32 bufptr_lo; 515 __le32 bufptr_hi; 516 __le32 s_dist; 517 __le32 s_size; 518 } t1; 519 __le32 data[4]; /* if DTYPE == 2 */ 520 u32 reserved[4]; /* if DTYPE == 3 */ 521 }; 522 } __aligned(32); 523 524 /* 525 * Inbound Messaging Descriptor 526 */ 527 struct tsi721_imsg_desc { 528 __le32 type_id; 529 530 #define TSI721_IMD_DEVID 0x0000ffff 531 #define TSI721_IMD_CRF 0x00010000 532 #define TSI721_IMD_PRIO 0x00060000 533 #define TSI721_IMD_TT 0x00180000 534 #define TSI721_IMD_DTYPE 0xe0000000 535 536 __le32 msg_info; 537 538 #define TSI721_IMD_BCOUNT 0x00000ff8 539 #define TSI721_IMD_SSIZE 0x0000f000 540 #define TSI721_IMD_LETER 0x00030000 541 #define TSI721_IMD_XMBOX 0x003c0000 542 #define TSI721_IMD_MBOX 0x00c00000 543 #define TSI721_IMD_CS 0x78000000 544 #define TSI721_IMD_HO 0x80000000 545 546 __le32 bufptr_lo; 547 __le32 bufptr_hi; 548 u32 reserved[12]; 549 550 } __aligned(64); 551 552 /* 553 * Outbound Messaging Descriptor 554 */ 555 struct tsi721_omsg_desc { 556 __le32 type_id; 557 558 #define TSI721_OMD_DEVID 0x0000ffff 559 #define TSI721_OMD_CRF 0x00010000 560 #define TSI721_OMD_PRIO 0x00060000 561 #define TSI721_OMD_IOF 0x08000000 562 #define TSI721_OMD_DTYPE 0xe0000000 563 #define TSI721_OMD_RSRVD 0x17f80000 564 565 __le32 msg_info; 566 567 #define TSI721_OMD_BCOUNT 0x00000ff8 568 #define TSI721_OMD_SSIZE 0x0000f000 569 #define TSI721_OMD_LETER 0x00030000 570 #define TSI721_OMD_XMBOX 0x003c0000 571 #define TSI721_OMD_MBOX 0x00c00000 572 #define TSI721_OMD_TT 0x0c000000 573 574 union { 575 __le32 bufptr_lo; /* if DTYPE == 4 */ 576 __le32 next_lo; /* if DTYPE == 5 */ 577 }; 578 579 union { 580 __le32 bufptr_hi; /* if DTYPE == 4 */ 581 __le32 next_hi; /* if DTYPE == 5 */ 582 }; 583 584 } __aligned(16); 585 586 struct tsi721_dma_sts { 587 __le64 desc_sts[8]; 588 } __aligned(64); 589 590 struct tsi721_desc_sts_fifo { 591 union { 592 __le64 da64; 593 struct { 594 __le32 lo; 595 __le32 hi; 596 } da32; 597 } stat[8]; 598 } __aligned(64); 599 600 /* Descriptor types for BDMA and Messaging blocks */ 601 enum dma_dtype { 602 DTYPE1 = 1, /* Data Transfer DMA Descriptor */ 603 DTYPE2 = 2, /* Immediate Data Transfer DMA Descriptor */ 604 DTYPE3 = 3, /* Block Pointer DMA Descriptor */ 605 DTYPE4 = 4, /* Outbound Msg DMA Descriptor */ 606 DTYPE5 = 5, /* OB Messaging Block Pointer Descriptor */ 607 DTYPE6 = 6 /* Inbound Messaging Descriptor */ 608 }; 609 610 enum dma_rtype { 611 NREAD = 0, 612 LAST_NWRITE_R = 1, 613 ALL_NWRITE = 2, 614 ALL_NWRITE_R = 3, 615 MAINT_RD = 4, 616 MAINT_WR = 5 617 }; 618 619 /* 620 * mport Driver Definitions 621 */ 622 #define TSI721_DMA_CHNUM TSI721_DMA_MAXCH 623 624 #define TSI721_DMACH_MAINT 0 /* DMA channel for maint requests */ 625 #define TSI721_DMACH_MAINT_NBD 32 /* Number of BDs for maint requests */ 626 627 #define TSI721_DMACH_DMA 1 /* DMA channel for data transfers */ 628 629 #define MSG_DMA_ENTRY_INX_TO_SIZE(x) ((0x10 << (x)) & 0xFFFF0) 630 631 enum tsi721_smsg_int_flag { 632 SMSG_INT_NONE = 0x00000000, 633 SMSG_INT_ECC_COR_CH = 0x000000ff, 634 SMSG_INT_ECC_NCOR_CH = 0x0000ff00, 635 SMSG_INT_ECC_COR = 0x00020000, 636 SMSG_INT_ECC_NCOR = 0x00040000, 637 SMSG_INT_UNS_RSP = 0x00800000, 638 SMSG_INT_ALL = 0x0006ffff 639 }; 640 641 /* Structures */ 642 643 #ifdef CONFIG_RAPIDIO_DMA_ENGINE 644 645 #define TSI721_BDMA_MAX_BCOUNT (TSI721_DMAD_BCOUNT1 + 1) 646 647 struct tsi721_tx_desc { 648 struct dma_async_tx_descriptor txd; 649 u16 destid; 650 /* low 64-bits of 66-bit RIO address */ 651 u64 rio_addr; 652 /* upper 2-bits of 66-bit RIO address */ 653 u8 rio_addr_u; 654 enum dma_rtype rtype; 655 struct list_head desc_node; 656 struct scatterlist *sg; 657 unsigned int sg_len; 658 enum dma_status status; 659 }; 660 661 struct tsi721_bdma_chan { 662 int id; 663 void __iomem *regs; 664 int bd_num; /* number of HW buffer descriptors */ 665 void *bd_base; /* start of DMA descriptors */ 666 dma_addr_t bd_phys; 667 void *sts_base; /* start of DMA BD status FIFO */ 668 dma_addr_t sts_phys; 669 int sts_size; 670 u32 sts_rdptr; 671 u32 wr_count; 672 u32 wr_count_next; 673 674 struct dma_chan dchan; 675 struct tsi721_tx_desc *tx_desc; 676 spinlock_t lock; 677 struct list_head active_list; 678 struct list_head queue; 679 struct list_head free_list; 680 struct tasklet_struct tasklet; 681 bool active; 682 }; 683 684 #endif /* CONFIG_RAPIDIO_DMA_ENGINE */ 685 686 struct tsi721_bdma_maint { 687 int ch_id; /* BDMA channel number */ 688 int bd_num; /* number of buffer descriptors */ 689 void *bd_base; /* start of DMA descriptors */ 690 dma_addr_t bd_phys; 691 void *sts_base; /* start of DMA BD status FIFO */ 692 dma_addr_t sts_phys; 693 int sts_size; 694 }; 695 696 struct tsi721_imsg_ring { 697 u32 size; 698 /* VA/PA of data buffers for incoming messages */ 699 void *buf_base; 700 dma_addr_t buf_phys; 701 /* VA/PA of circular free buffer list */ 702 void *imfq_base; 703 dma_addr_t imfq_phys; 704 /* VA/PA of Inbound message descriptors */ 705 void *imd_base; 706 dma_addr_t imd_phys; 707 /* Inbound Queue buffer pointers */ 708 void *imq_base[TSI721_IMSGD_RING_SIZE]; 709 710 u32 rx_slot; 711 void *dev_id; 712 u32 fq_wrptr; 713 u32 desc_rdptr; 714 spinlock_t lock; 715 }; 716 717 struct tsi721_omsg_ring { 718 u32 size; 719 /* VA/PA of OB Msg descriptors */ 720 void *omd_base; 721 dma_addr_t omd_phys; 722 /* VA/PA of OB Msg data buffers */ 723 void *omq_base[TSI721_OMSGD_RING_SIZE]; 724 dma_addr_t omq_phys[TSI721_OMSGD_RING_SIZE]; 725 /* VA/PA of OB Msg descriptor status FIFO */ 726 void *sts_base; 727 dma_addr_t sts_phys; 728 u32 sts_size; /* # of allocated status entries */ 729 u32 sts_rdptr; 730 731 u32 tx_slot; 732 void *dev_id; 733 u32 wr_count; 734 spinlock_t lock; 735 }; 736 737 enum tsi721_flags { 738 TSI721_USING_MSI = (1 << 0), 739 TSI721_USING_MSIX = (1 << 1), 740 TSI721_IMSGID_SET = (1 << 2), 741 }; 742 743 #ifdef CONFIG_PCI_MSI 744 /* 745 * MSI-X Table Entries (0 ... 69) 746 */ 747 #define TSI721_MSIX_DMACH_DONE(x) (0 + (x)) 748 #define TSI721_MSIX_DMACH_INT(x) (8 + (x)) 749 #define TSI721_MSIX_BDMA_INT 16 750 #define TSI721_MSIX_OMSG_DONE(x) (17 + (x)) 751 #define TSI721_MSIX_OMSG_INT(x) (25 + (x)) 752 #define TSI721_MSIX_IMSG_DQ_RCV(x) (33 + (x)) 753 #define TSI721_MSIX_IMSG_INT(x) (41 + (x)) 754 #define TSI721_MSIX_MSG_INT 49 755 #define TSI721_MSIX_SR2PC_IDBQ_RCV(x) (50 + (x)) 756 #define TSI721_MSIX_SR2PC_CH_INT(x) (58 + (x)) 757 #define TSI721_MSIX_SR2PC_INT 66 758 #define TSI721_MSIX_PC2SR_INT 67 759 #define TSI721_MSIX_SRIO_MAC_INT 68 760 #define TSI721_MSIX_I2C_INT 69 761 762 /* MSI-X vector and init table entry indexes */ 763 enum tsi721_msix_vect { 764 TSI721_VECT_IDB, 765 TSI721_VECT_PWRX, /* PW_RX is part of SRIO MAC Interrupt reporting */ 766 TSI721_VECT_OMB0_DONE, 767 TSI721_VECT_OMB1_DONE, 768 TSI721_VECT_OMB2_DONE, 769 TSI721_VECT_OMB3_DONE, 770 TSI721_VECT_OMB0_INT, 771 TSI721_VECT_OMB1_INT, 772 TSI721_VECT_OMB2_INT, 773 TSI721_VECT_OMB3_INT, 774 TSI721_VECT_IMB0_RCV, 775 TSI721_VECT_IMB1_RCV, 776 TSI721_VECT_IMB2_RCV, 777 TSI721_VECT_IMB3_RCV, 778 TSI721_VECT_IMB0_INT, 779 TSI721_VECT_IMB1_INT, 780 TSI721_VECT_IMB2_INT, 781 TSI721_VECT_IMB3_INT, 782 #ifdef CONFIG_RAPIDIO_DMA_ENGINE 783 TSI721_VECT_DMA0_DONE, 784 TSI721_VECT_DMA1_DONE, 785 TSI721_VECT_DMA2_DONE, 786 TSI721_VECT_DMA3_DONE, 787 TSI721_VECT_DMA4_DONE, 788 TSI721_VECT_DMA5_DONE, 789 TSI721_VECT_DMA6_DONE, 790 TSI721_VECT_DMA7_DONE, 791 TSI721_VECT_DMA0_INT, 792 TSI721_VECT_DMA1_INT, 793 TSI721_VECT_DMA2_INT, 794 TSI721_VECT_DMA3_INT, 795 TSI721_VECT_DMA4_INT, 796 TSI721_VECT_DMA5_INT, 797 TSI721_VECT_DMA6_INT, 798 TSI721_VECT_DMA7_INT, 799 #endif /* CONFIG_RAPIDIO_DMA_ENGINE */ 800 TSI721_VECT_MAX 801 }; 802 803 #define IRQ_DEVICE_NAME_MAX 64 804 805 struct msix_irq { 806 u16 vector; 807 char irq_name[IRQ_DEVICE_NAME_MAX]; 808 }; 809 #endif /* CONFIG_PCI_MSI */ 810 811 struct tsi721_device { 812 struct pci_dev *pdev; 813 struct rio_mport *mport; 814 u32 flags; 815 void __iomem *regs; 816 #ifdef CONFIG_PCI_MSI 817 struct msix_irq msix[TSI721_VECT_MAX]; 818 #endif 819 /* Doorbells */ 820 void __iomem *odb_base; 821 void *idb_base; 822 dma_addr_t idb_dma; 823 struct work_struct idb_work; 824 u32 db_discard_count; 825 826 /* Inbound Port-Write */ 827 struct work_struct pw_work; 828 struct kfifo pw_fifo; 829 spinlock_t pw_fifo_lock; 830 u32 pw_discard_count; 831 832 /* BDMA Engine */ 833 struct tsi721_bdma_maint mdma; /* Maintenance rd/wr request channel */ 834 835 #ifdef CONFIG_RAPIDIO_DMA_ENGINE 836 struct tsi721_bdma_chan bdma[TSI721_DMA_CHNUM]; 837 #endif 838 839 /* Inbound Messaging */ 840 int imsg_init[TSI721_IMSG_CHNUM]; 841 struct tsi721_imsg_ring imsg_ring[TSI721_IMSG_CHNUM]; 842 843 /* Outbound Messaging */ 844 int omsg_init[TSI721_OMSG_CHNUM]; 845 struct tsi721_omsg_ring omsg_ring[TSI721_OMSG_CHNUM]; 846 }; 847 848 #ifdef CONFIG_RAPIDIO_DMA_ENGINE 849 extern void tsi721_bdma_handler(struct tsi721_bdma_chan *bdma_chan); 850 extern int tsi721_register_dma(struct tsi721_device *priv); 851 #endif 852 853 #endif 854