1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/pwm/pwm-vt8500.c 4 * 5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> 6 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> 7 */ 8 9 #include <linux/mod_devicetable.h> 10 #include <linux/module.h> 11 #include <linux/kernel.h> 12 #include <linux/platform_device.h> 13 #include <linux/slab.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/pwm.h> 17 #include <linux/delay.h> 18 #include <linux/clk.h> 19 20 #include <asm/div64.h> 21 22 /* 23 * SoC architecture allocates register space for 4 PWMs but only 24 * 2 are currently implemented. 25 */ 26 #define VT8500_NR_PWMS 2 27 28 #define REG_CTRL(pwm) (((pwm) << 4) + 0x00) 29 #define REG_SCALAR(pwm) (((pwm) << 4) + 0x04) 30 #define REG_PERIOD(pwm) (((pwm) << 4) + 0x08) 31 #define REG_DUTY(pwm) (((pwm) << 4) + 0x0C) 32 #define REG_STATUS 0x40 33 34 #define CTRL_ENABLE BIT(0) 35 #define CTRL_INVERT BIT(1) 36 #define CTRL_AUTOLOAD BIT(2) 37 #define CTRL_STOP_IMM BIT(3) 38 #define CTRL_LOAD_PRESCALE BIT(4) 39 #define CTRL_LOAD_PERIOD BIT(5) 40 41 #define STATUS_CTRL_UPDATE BIT(0) 42 #define STATUS_SCALAR_UPDATE BIT(1) 43 #define STATUS_PERIOD_UPDATE BIT(2) 44 #define STATUS_DUTY_UPDATE BIT(3) 45 #define STATUS_ALL_UPDATE 0x0F 46 47 struct vt8500_chip { 48 struct pwm_chip chip; 49 void __iomem *base; 50 struct clk *clk; 51 }; 52 53 #define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip) 54 55 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 56 static inline void vt8500_pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask) 57 { 58 int loops = msecs_to_loops(10); 59 u32 mask = bitmask << (nr << 8); 60 61 while ((readl(vt8500->base + REG_STATUS) & mask) && --loops) 62 cpu_relax(); 63 64 if (unlikely(!loops)) 65 dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n", 66 mask); 67 } 68 69 static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 70 u64 duty_ns, u64 period_ns) 71 { 72 struct vt8500_chip *vt8500 = to_vt8500_chip(chip); 73 unsigned long long c; 74 unsigned long period_cycles, prescale, pv, dc; 75 int err; 76 u32 val; 77 78 err = clk_enable(vt8500->clk); 79 if (err < 0) { 80 dev_err(chip->dev, "failed to enable clock\n"); 81 return err; 82 } 83 84 c = clk_get_rate(vt8500->clk); 85 c = c * period_ns; 86 do_div(c, 1000000000); 87 period_cycles = c; 88 89 if (period_cycles < 1) 90 period_cycles = 1; 91 prescale = (period_cycles - 1) / 4096; 92 pv = period_cycles / (prescale + 1) - 1; 93 if (pv > 4095) 94 pv = 4095; 95 96 if (prescale > 1023) { 97 clk_disable(vt8500->clk); 98 return -EINVAL; 99 } 100 101 c = (unsigned long long)pv * duty_ns; 102 103 dc = div64_u64(c, period_ns); 104 105 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); 106 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE); 107 108 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); 109 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE); 110 111 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); 112 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE); 113 114 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); 115 val |= CTRL_AUTOLOAD; 116 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); 117 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); 118 119 clk_disable(vt8500->clk); 120 return 0; 121 } 122 123 static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 124 { 125 struct vt8500_chip *vt8500 = to_vt8500_chip(chip); 126 int err; 127 u32 val; 128 129 err = clk_enable(vt8500->clk); 130 if (err < 0) { 131 dev_err(chip->dev, "failed to enable clock\n"); 132 return err; 133 } 134 135 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); 136 val |= CTRL_ENABLE; 137 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); 138 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); 139 140 return 0; 141 } 142 143 static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 144 { 145 struct vt8500_chip *vt8500 = to_vt8500_chip(chip); 146 u32 val; 147 148 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); 149 val &= ~CTRL_ENABLE; 150 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); 151 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); 152 153 clk_disable(vt8500->clk); 154 } 155 156 static int vt8500_pwm_set_polarity(struct pwm_chip *chip, 157 struct pwm_device *pwm, 158 enum pwm_polarity polarity) 159 { 160 struct vt8500_chip *vt8500 = to_vt8500_chip(chip); 161 u32 val; 162 163 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); 164 165 if (polarity == PWM_POLARITY_INVERSED) 166 val |= CTRL_INVERT; 167 else 168 val &= ~CTRL_INVERT; 169 170 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); 171 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); 172 173 return 0; 174 } 175 176 static int vt8500_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 177 const struct pwm_state *state) 178 { 179 int err; 180 bool enabled = pwm->state.enabled; 181 182 if (state->polarity != pwm->state.polarity) { 183 /* 184 * Changing the polarity of a running PWM is only allowed when 185 * the PWM driver implements ->apply(). 186 */ 187 if (enabled) { 188 vt8500_pwm_disable(chip, pwm); 189 190 enabled = false; 191 } 192 193 err = vt8500_pwm_set_polarity(chip, pwm, state->polarity); 194 if (err) 195 return err; 196 } 197 198 if (!state->enabled) { 199 if (enabled) 200 vt8500_pwm_disable(chip, pwm); 201 202 return 0; 203 } 204 205 /* 206 * We cannot skip calling ->config even if state->period == 207 * pwm->state.period && state->duty_cycle == pwm->state.duty_cycle 208 * because we might have exited early in the last call to 209 * pwm_apply_state because of !state->enabled and so the two values in 210 * pwm->state might not be configured in hardware. 211 */ 212 err = vt8500_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period); 213 if (err) 214 return err; 215 216 if (!enabled) 217 err = vt8500_pwm_enable(chip, pwm); 218 219 return err; 220 } 221 222 static const struct pwm_ops vt8500_pwm_ops = { 223 .apply = vt8500_pwm_apply, 224 .owner = THIS_MODULE, 225 }; 226 227 static const struct of_device_id vt8500_pwm_dt_ids[] = { 228 { .compatible = "via,vt8500-pwm", }, 229 { /* Sentinel */ } 230 }; 231 MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids); 232 233 static int vt8500_pwm_probe(struct platform_device *pdev) 234 { 235 struct vt8500_chip *vt8500; 236 struct device_node *np = pdev->dev.of_node; 237 int ret; 238 239 if (!np) { 240 dev_err(&pdev->dev, "invalid devicetree node\n"); 241 return -EINVAL; 242 } 243 244 vt8500 = devm_kzalloc(&pdev->dev, sizeof(*vt8500), GFP_KERNEL); 245 if (vt8500 == NULL) 246 return -ENOMEM; 247 248 vt8500->chip.dev = &pdev->dev; 249 vt8500->chip.ops = &vt8500_pwm_ops; 250 vt8500->chip.npwm = VT8500_NR_PWMS; 251 252 vt8500->clk = devm_clk_get(&pdev->dev, NULL); 253 if (IS_ERR(vt8500->clk)) { 254 dev_err(&pdev->dev, "clock source not specified\n"); 255 return PTR_ERR(vt8500->clk); 256 } 257 258 vt8500->base = devm_platform_ioremap_resource(pdev, 0); 259 if (IS_ERR(vt8500->base)) 260 return PTR_ERR(vt8500->base); 261 262 ret = clk_prepare(vt8500->clk); 263 if (ret < 0) { 264 dev_err(&pdev->dev, "failed to prepare clock\n"); 265 return ret; 266 } 267 268 ret = pwmchip_add(&vt8500->chip); 269 if (ret < 0) { 270 dev_err(&pdev->dev, "failed to add PWM chip\n"); 271 clk_unprepare(vt8500->clk); 272 return ret; 273 } 274 275 platform_set_drvdata(pdev, vt8500); 276 return ret; 277 } 278 279 static void vt8500_pwm_remove(struct platform_device *pdev) 280 { 281 struct vt8500_chip *vt8500 = platform_get_drvdata(pdev); 282 283 pwmchip_remove(&vt8500->chip); 284 285 clk_unprepare(vt8500->clk); 286 } 287 288 static struct platform_driver vt8500_pwm_driver = { 289 .probe = vt8500_pwm_probe, 290 .remove_new = vt8500_pwm_remove, 291 .driver = { 292 .name = "vt8500-pwm", 293 .of_match_table = vt8500_pwm_dt_ids, 294 }, 295 }; 296 module_platform_driver(vt8500_pwm_driver); 297 298 MODULE_DESCRIPTION("VT8500 PWM Driver"); 299 MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>"); 300 MODULE_LICENSE("GPL v2"); 301