1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/pwm/pwm-tegra.c 4 * 5 * Tegra pulse-width-modulation controller driver 6 * 7 * Copyright (c) 2010-2020, NVIDIA Corporation. 8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de> 9 * 10 * Overview of Tegra Pulse Width Modulator Register: 11 * 1. 13-bit: Frequency division (SCALE) 12 * 2. 8-bit : Pulse division (DUTY) 13 * 3. 1-bit : Enable bit 14 * 15 * The PWM clock frequency is divided by 256 before subdividing it based 16 * on the programmable frequency division value to generate the required 17 * frequency for PWM output. The maximum output frequency that can be 18 * achieved is (max rate of source clock) / 256. 19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be: 20 * 408 MHz/256 = 1.6 MHz. 21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM. 22 * 23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width. 24 * To achieve 100% duty cycle, program Bit [24] of this register to 25 * 1’b1. In which case the other bits [23:16] are set to don't care. 26 * 27 * Limitations: 28 * - When PWM is disabled, the output is driven to inactive. 29 * - It does not allow the current PWM period to complete and 30 * stops abruptly. 31 * 32 * - If the register is reconfigured while PWM is running, 33 * it does not complete the currently running period. 34 * 35 * - If the user input duty is beyond acceptible limits, 36 * -EINVAL is returned. 37 */ 38 39 #include <linux/clk.h> 40 #include <linux/err.h> 41 #include <linux/io.h> 42 #include <linux/module.h> 43 #include <linux/of.h> 44 #include <linux/of_device.h> 45 #include <linux/pm_opp.h> 46 #include <linux/pwm.h> 47 #include <linux/platform_device.h> 48 #include <linux/pinctrl/consumer.h> 49 #include <linux/pm_runtime.h> 50 #include <linux/slab.h> 51 #include <linux/reset.h> 52 53 #include <soc/tegra/common.h> 54 55 #define PWM_ENABLE (1 << 31) 56 #define PWM_DUTY_WIDTH 8 57 #define PWM_DUTY_SHIFT 16 58 #define PWM_SCALE_WIDTH 13 59 #define PWM_SCALE_SHIFT 0 60 61 struct tegra_pwm_soc { 62 unsigned int num_channels; 63 64 /* Maximum IP frequency for given SoCs */ 65 unsigned long max_frequency; 66 }; 67 68 struct tegra_pwm_chip { 69 struct pwm_chip chip; 70 struct device *dev; 71 72 struct clk *clk; 73 struct reset_control*rst; 74 75 unsigned long clk_rate; 76 unsigned long min_period_ns; 77 78 void __iomem *regs; 79 80 const struct tegra_pwm_soc *soc; 81 }; 82 83 static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) 84 { 85 return container_of(chip, struct tegra_pwm_chip, chip); 86 } 87 88 static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset) 89 { 90 return readl(pc->regs + (offset << 4)); 91 } 92 93 static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value) 94 { 95 writel(value, pc->regs + (offset << 4)); 96 } 97 98 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 99 int duty_ns, int period_ns) 100 { 101 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 102 unsigned long long c = duty_ns, hz; 103 unsigned long rate, required_clk_rate; 104 u32 val = 0; 105 int err; 106 107 /* 108 * Convert from duty_ns / period_ns to a fixed number of duty ticks 109 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the 110 * nearest integer during division. 111 */ 112 c *= (1 << PWM_DUTY_WIDTH); 113 c = DIV_ROUND_CLOSEST_ULL(c, period_ns); 114 115 val = (u32)c << PWM_DUTY_SHIFT; 116 117 /* 118 * min period = max clock limit >> PWM_DUTY_WIDTH 119 */ 120 if (period_ns < pc->min_period_ns) 121 return -EINVAL; 122 123 /* 124 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) 125 * cycles at the PWM clock rate will take period_ns nanoseconds. 126 * 127 * num_channels: If single instance of PWM controller has multiple 128 * channels (e.g. Tegra210 or older) then it is not possible to 129 * configure separate clock rates to each of the channels, in such 130 * case the value stored during probe will be referred. 131 * 132 * If every PWM controller instance has one channel respectively, i.e. 133 * nums_channels == 1 then only the clock rate can be modified 134 * dynamically (e.g. Tegra186 or Tegra194). 135 */ 136 if (pc->soc->num_channels == 1) { 137 /* 138 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches 139 * with the maximum possible rate that the controller can 140 * provide. Any further lower value can be derived by setting 141 * PFM bits[0:12]. 142 * 143 * required_clk_rate is a reference rate for source clock and 144 * it is derived based on user requested period. By setting the 145 * source clock rate as required_clk_rate, PWM controller will 146 * be able to configure the requested period. 147 */ 148 required_clk_rate = 149 (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH; 150 151 err = dev_pm_opp_set_rate(pc->dev, required_clk_rate); 152 if (err < 0) 153 return -EINVAL; 154 155 /* Store the new rate for further references */ 156 pc->clk_rate = clk_get_rate(pc->clk); 157 } 158 159 rate = pc->clk_rate >> PWM_DUTY_WIDTH; 160 161 /* Consider precision in PWM_SCALE_WIDTH rate calculation */ 162 hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns); 163 rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz); 164 165 /* 166 * Since the actual PWM divider is the register's frequency divider 167 * field plus 1, we need to decrement to get the correct value to 168 * write to the register. 169 */ 170 if (rate > 0) 171 rate--; 172 173 /* 174 * Make sure that the rate will fit in the register's frequency 175 * divider field. 176 */ 177 if (rate >> PWM_SCALE_WIDTH) 178 return -EINVAL; 179 180 val |= rate << PWM_SCALE_SHIFT; 181 182 /* 183 * If the PWM channel is disabled, make sure to turn on the clock 184 * before writing the register. Otherwise, keep it enabled. 185 */ 186 if (!pwm_is_enabled(pwm)) { 187 err = pm_runtime_resume_and_get(pc->dev); 188 if (err) 189 return err; 190 } else 191 val |= PWM_ENABLE; 192 193 pwm_writel(pc, pwm->hwpwm, val); 194 195 /* 196 * If the PWM is not enabled, turn the clock off again to save power. 197 */ 198 if (!pwm_is_enabled(pwm)) 199 pm_runtime_put(pc->dev); 200 201 return 0; 202 } 203 204 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 205 { 206 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 207 int rc = 0; 208 u32 val; 209 210 rc = pm_runtime_resume_and_get(pc->dev); 211 if (rc) 212 return rc; 213 214 val = pwm_readl(pc, pwm->hwpwm); 215 val |= PWM_ENABLE; 216 pwm_writel(pc, pwm->hwpwm, val); 217 218 return 0; 219 } 220 221 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 222 { 223 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 224 u32 val; 225 226 val = pwm_readl(pc, pwm->hwpwm); 227 val &= ~PWM_ENABLE; 228 pwm_writel(pc, pwm->hwpwm, val); 229 230 pm_runtime_put_sync(pc->dev); 231 } 232 233 static const struct pwm_ops tegra_pwm_ops = { 234 .config = tegra_pwm_config, 235 .enable = tegra_pwm_enable, 236 .disable = tegra_pwm_disable, 237 .owner = THIS_MODULE, 238 }; 239 240 static int tegra_pwm_probe(struct platform_device *pdev) 241 { 242 struct tegra_pwm_chip *pc; 243 int ret; 244 245 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 246 if (!pc) 247 return -ENOMEM; 248 249 pc->soc = of_device_get_match_data(&pdev->dev); 250 pc->dev = &pdev->dev; 251 252 pc->regs = devm_platform_ioremap_resource(pdev, 0); 253 if (IS_ERR(pc->regs)) 254 return PTR_ERR(pc->regs); 255 256 platform_set_drvdata(pdev, pc); 257 258 pc->clk = devm_clk_get(&pdev->dev, NULL); 259 if (IS_ERR(pc->clk)) 260 return PTR_ERR(pc->clk); 261 262 ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 263 if (ret) 264 return ret; 265 266 pm_runtime_enable(&pdev->dev); 267 ret = pm_runtime_resume_and_get(&pdev->dev); 268 if (ret) 269 return ret; 270 271 /* Set maximum frequency of the IP */ 272 ret = dev_pm_opp_set_rate(pc->dev, pc->soc->max_frequency); 273 if (ret < 0) { 274 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); 275 goto put_pm; 276 } 277 278 /* 279 * The requested and configured frequency may differ due to 280 * clock register resolutions. Get the configured frequency 281 * so that PWM period can be calculated more accurately. 282 */ 283 pc->clk_rate = clk_get_rate(pc->clk); 284 285 /* Set minimum limit of PWM period for the IP */ 286 pc->min_period_ns = 287 (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1; 288 289 pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); 290 if (IS_ERR(pc->rst)) { 291 ret = PTR_ERR(pc->rst); 292 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret); 293 goto put_pm; 294 } 295 296 reset_control_deassert(pc->rst); 297 298 pc->chip.dev = &pdev->dev; 299 pc->chip.ops = &tegra_pwm_ops; 300 pc->chip.npwm = pc->soc->num_channels; 301 302 ret = pwmchip_add(&pc->chip); 303 if (ret < 0) { 304 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 305 reset_control_assert(pc->rst); 306 goto put_pm; 307 } 308 309 pm_runtime_put(&pdev->dev); 310 311 return 0; 312 put_pm: 313 pm_runtime_put_sync_suspend(&pdev->dev); 314 pm_runtime_force_suspend(&pdev->dev); 315 return ret; 316 } 317 318 static int tegra_pwm_remove(struct platform_device *pdev) 319 { 320 struct tegra_pwm_chip *pc = platform_get_drvdata(pdev); 321 322 pwmchip_remove(&pc->chip); 323 324 reset_control_assert(pc->rst); 325 326 pm_runtime_force_suspend(&pdev->dev); 327 328 return 0; 329 } 330 331 static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev) 332 { 333 struct tegra_pwm_chip *pc = dev_get_drvdata(dev); 334 int err; 335 336 clk_disable_unprepare(pc->clk); 337 338 err = pinctrl_pm_select_sleep_state(dev); 339 if (err) { 340 clk_prepare_enable(pc->clk); 341 return err; 342 } 343 344 return 0; 345 } 346 347 static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev) 348 { 349 struct tegra_pwm_chip *pc = dev_get_drvdata(dev); 350 int err; 351 352 err = pinctrl_pm_select_default_state(dev); 353 if (err) 354 return err; 355 356 err = clk_prepare_enable(pc->clk); 357 if (err) { 358 pinctrl_pm_select_sleep_state(dev); 359 return err; 360 } 361 362 return 0; 363 } 364 365 static const struct tegra_pwm_soc tegra20_pwm_soc = { 366 .num_channels = 4, 367 .max_frequency = 48000000UL, 368 }; 369 370 static const struct tegra_pwm_soc tegra186_pwm_soc = { 371 .num_channels = 1, 372 .max_frequency = 102000000UL, 373 }; 374 375 static const struct tegra_pwm_soc tegra194_pwm_soc = { 376 .num_channels = 1, 377 .max_frequency = 408000000UL, 378 }; 379 380 static const struct of_device_id tegra_pwm_of_match[] = { 381 { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc }, 382 { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc }, 383 { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc }, 384 { } 385 }; 386 MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); 387 388 static const struct dev_pm_ops tegra_pwm_pm_ops = { 389 SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume, 390 NULL) 391 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 392 pm_runtime_force_resume) 393 }; 394 395 static struct platform_driver tegra_pwm_driver = { 396 .driver = { 397 .name = "tegra-pwm", 398 .of_match_table = tegra_pwm_of_match, 399 .pm = &tegra_pwm_pm_ops, 400 }, 401 .probe = tegra_pwm_probe, 402 .remove = tegra_pwm_remove, 403 }; 404 405 module_platform_driver(tegra_pwm_driver); 406 407 MODULE_LICENSE("GPL"); 408 MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>"); 409 MODULE_DESCRIPTION("Tegra PWM controller driver"); 410 MODULE_ALIAS("platform:tegra-pwm"); 411