1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/pwm/pwm-tegra.c 4 * 5 * Tegra pulse-width-modulation controller driver 6 * 7 * Copyright (c) 2010-2020, NVIDIA Corporation. 8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de> 9 * 10 * Overview of Tegra Pulse Width Modulator Register: 11 * 1. 13-bit: Frequency division (SCALE) 12 * 2. 8-bit : Pulse division (DUTY) 13 * 3. 1-bit : Enable bit 14 * 15 * The PWM clock frequency is divided by 256 before subdividing it based 16 * on the programmable frequency division value to generate the required 17 * frequency for PWM output. The maximum output frequency that can be 18 * achieved is (max rate of source clock) / 256. 19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be: 20 * 408 MHz/256 = 1.6 MHz. 21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM. 22 * 23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width. 24 * To achieve 100% duty cycle, program Bit [24] of this register to 25 * 1’b1. In which case the other bits [23:16] are set to don't care. 26 * 27 * Limitations: 28 * - When PWM is disabled, the output is driven to inactive. 29 * - It does not allow the current PWM period to complete and 30 * stops abruptly. 31 * 32 * - If the register is reconfigured while PWM is running, 33 * it does not complete the currently running period. 34 * 35 * - If the user input duty is beyond acceptible limits, 36 * -EINVAL is returned. 37 */ 38 39 #include <linux/clk.h> 40 #include <linux/err.h> 41 #include <linux/io.h> 42 #include <linux/module.h> 43 #include <linux/of.h> 44 #include <linux/of_device.h> 45 #include <linux/pm_opp.h> 46 #include <linux/pwm.h> 47 #include <linux/platform_device.h> 48 #include <linux/pinctrl/consumer.h> 49 #include <linux/pm_runtime.h> 50 #include <linux/slab.h> 51 #include <linux/reset.h> 52 53 #include <soc/tegra/common.h> 54 55 #define PWM_ENABLE (1 << 31) 56 #define PWM_DUTY_WIDTH 8 57 #define PWM_DUTY_SHIFT 16 58 #define PWM_SCALE_WIDTH 13 59 #define PWM_SCALE_SHIFT 0 60 61 struct tegra_pwm_soc { 62 unsigned int num_channels; 63 64 /* Maximum IP frequency for given SoCs */ 65 unsigned long max_frequency; 66 }; 67 68 struct tegra_pwm_chip { 69 struct pwm_chip chip; 70 struct device *dev; 71 72 struct clk *clk; 73 struct reset_control*rst; 74 75 unsigned long clk_rate; 76 unsigned long min_period_ns; 77 78 void __iomem *regs; 79 80 const struct tegra_pwm_soc *soc; 81 }; 82 83 static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) 84 { 85 return container_of(chip, struct tegra_pwm_chip, chip); 86 } 87 88 static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset) 89 { 90 return readl(pc->regs + (offset << 4)); 91 } 92 93 static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value) 94 { 95 writel(value, pc->regs + (offset << 4)); 96 } 97 98 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 99 int duty_ns, int period_ns) 100 { 101 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 102 unsigned long long c = duty_ns; 103 unsigned long rate, required_clk_rate; 104 u32 val = 0; 105 int err; 106 107 /* 108 * Convert from duty_ns / period_ns to a fixed number of duty ticks 109 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the 110 * nearest integer during division. 111 */ 112 c *= (1 << PWM_DUTY_WIDTH); 113 c = DIV_ROUND_CLOSEST_ULL(c, period_ns); 114 115 val = (u32)c << PWM_DUTY_SHIFT; 116 117 /* 118 * min period = max clock limit >> PWM_DUTY_WIDTH 119 */ 120 if (period_ns < pc->min_period_ns) 121 return -EINVAL; 122 123 /* 124 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) 125 * cycles at the PWM clock rate will take period_ns nanoseconds. 126 * 127 * num_channels: If single instance of PWM controller has multiple 128 * channels (e.g. Tegra210 or older) then it is not possible to 129 * configure separate clock rates to each of the channels, in such 130 * case the value stored during probe will be referred. 131 * 132 * If every PWM controller instance has one channel respectively, i.e. 133 * nums_channels == 1 then only the clock rate can be modified 134 * dynamically (e.g. Tegra186 or Tegra194). 135 */ 136 if (pc->soc->num_channels == 1) { 137 /* 138 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches 139 * with the maximum possible rate that the controller can 140 * provide. Any further lower value can be derived by setting 141 * PFM bits[0:12]. 142 * 143 * required_clk_rate is a reference rate for source clock and 144 * it is derived based on user requested period. By setting the 145 * source clock rate as required_clk_rate, PWM controller will 146 * be able to configure the requested period. 147 */ 148 required_clk_rate = 149 (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH; 150 151 err = dev_pm_opp_set_rate(pc->dev, required_clk_rate); 152 if (err < 0) 153 return -EINVAL; 154 155 /* Store the new rate for further references */ 156 pc->clk_rate = clk_get_rate(pc->clk); 157 } 158 159 /* Consider precision in PWM_SCALE_WIDTH rate calculation */ 160 rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns, 161 (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH); 162 163 /* 164 * Since the actual PWM divider is the register's frequency divider 165 * field plus 1, we need to decrement to get the correct value to 166 * write to the register. 167 */ 168 if (rate > 0) 169 rate--; 170 else 171 return -EINVAL; 172 173 /* 174 * Make sure that the rate will fit in the register's frequency 175 * divider field. 176 */ 177 if (rate >> PWM_SCALE_WIDTH) 178 return -EINVAL; 179 180 val |= rate << PWM_SCALE_SHIFT; 181 182 /* 183 * If the PWM channel is disabled, make sure to turn on the clock 184 * before writing the register. Otherwise, keep it enabled. 185 */ 186 if (!pwm_is_enabled(pwm)) { 187 err = pm_runtime_resume_and_get(pc->dev); 188 if (err) 189 return err; 190 } else 191 val |= PWM_ENABLE; 192 193 pwm_writel(pc, pwm->hwpwm, val); 194 195 /* 196 * If the PWM is not enabled, turn the clock off again to save power. 197 */ 198 if (!pwm_is_enabled(pwm)) 199 pm_runtime_put(pc->dev); 200 201 return 0; 202 } 203 204 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 205 { 206 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 207 int rc = 0; 208 u32 val; 209 210 rc = pm_runtime_resume_and_get(pc->dev); 211 if (rc) 212 return rc; 213 214 val = pwm_readl(pc, pwm->hwpwm); 215 val |= PWM_ENABLE; 216 pwm_writel(pc, pwm->hwpwm, val); 217 218 return 0; 219 } 220 221 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 222 { 223 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 224 u32 val; 225 226 val = pwm_readl(pc, pwm->hwpwm); 227 val &= ~PWM_ENABLE; 228 pwm_writel(pc, pwm->hwpwm, val); 229 230 pm_runtime_put_sync(pc->dev); 231 } 232 233 static int tegra_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 234 const struct pwm_state *state) 235 { 236 int err; 237 bool enabled = pwm->state.enabled; 238 239 if (state->polarity != PWM_POLARITY_NORMAL) 240 return -EINVAL; 241 242 if (!state->enabled) { 243 if (enabled) 244 tegra_pwm_disable(chip, pwm); 245 246 return 0; 247 } 248 249 err = tegra_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period); 250 if (err) 251 return err; 252 253 if (!enabled) 254 err = tegra_pwm_enable(chip, pwm); 255 256 return err; 257 } 258 259 static const struct pwm_ops tegra_pwm_ops = { 260 .apply = tegra_pwm_apply, 261 .owner = THIS_MODULE, 262 }; 263 264 static int tegra_pwm_probe(struct platform_device *pdev) 265 { 266 struct tegra_pwm_chip *pc; 267 int ret; 268 269 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 270 if (!pc) 271 return -ENOMEM; 272 273 pc->soc = of_device_get_match_data(&pdev->dev); 274 pc->dev = &pdev->dev; 275 276 pc->regs = devm_platform_ioremap_resource(pdev, 0); 277 if (IS_ERR(pc->regs)) 278 return PTR_ERR(pc->regs); 279 280 platform_set_drvdata(pdev, pc); 281 282 pc->clk = devm_clk_get(&pdev->dev, NULL); 283 if (IS_ERR(pc->clk)) 284 return PTR_ERR(pc->clk); 285 286 ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 287 if (ret) 288 return ret; 289 290 pm_runtime_enable(&pdev->dev); 291 ret = pm_runtime_resume_and_get(&pdev->dev); 292 if (ret) 293 return ret; 294 295 /* Set maximum frequency of the IP */ 296 ret = dev_pm_opp_set_rate(pc->dev, pc->soc->max_frequency); 297 if (ret < 0) { 298 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); 299 goto put_pm; 300 } 301 302 /* 303 * The requested and configured frequency may differ due to 304 * clock register resolutions. Get the configured frequency 305 * so that PWM period can be calculated more accurately. 306 */ 307 pc->clk_rate = clk_get_rate(pc->clk); 308 309 /* Set minimum limit of PWM period for the IP */ 310 pc->min_period_ns = 311 (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1; 312 313 pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); 314 if (IS_ERR(pc->rst)) { 315 ret = PTR_ERR(pc->rst); 316 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret); 317 goto put_pm; 318 } 319 320 reset_control_deassert(pc->rst); 321 322 pc->chip.dev = &pdev->dev; 323 pc->chip.ops = &tegra_pwm_ops; 324 pc->chip.npwm = pc->soc->num_channels; 325 326 ret = pwmchip_add(&pc->chip); 327 if (ret < 0) { 328 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 329 reset_control_assert(pc->rst); 330 goto put_pm; 331 } 332 333 pm_runtime_put(&pdev->dev); 334 335 return 0; 336 put_pm: 337 pm_runtime_put_sync_suspend(&pdev->dev); 338 pm_runtime_force_suspend(&pdev->dev); 339 return ret; 340 } 341 342 static int tegra_pwm_remove(struct platform_device *pdev) 343 { 344 struct tegra_pwm_chip *pc = platform_get_drvdata(pdev); 345 346 pwmchip_remove(&pc->chip); 347 348 reset_control_assert(pc->rst); 349 350 pm_runtime_force_suspend(&pdev->dev); 351 352 return 0; 353 } 354 355 static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev) 356 { 357 struct tegra_pwm_chip *pc = dev_get_drvdata(dev); 358 int err; 359 360 clk_disable_unprepare(pc->clk); 361 362 err = pinctrl_pm_select_sleep_state(dev); 363 if (err) { 364 clk_prepare_enable(pc->clk); 365 return err; 366 } 367 368 return 0; 369 } 370 371 static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev) 372 { 373 struct tegra_pwm_chip *pc = dev_get_drvdata(dev); 374 int err; 375 376 err = pinctrl_pm_select_default_state(dev); 377 if (err) 378 return err; 379 380 err = clk_prepare_enable(pc->clk); 381 if (err) { 382 pinctrl_pm_select_sleep_state(dev); 383 return err; 384 } 385 386 return 0; 387 } 388 389 static const struct tegra_pwm_soc tegra20_pwm_soc = { 390 .num_channels = 4, 391 .max_frequency = 48000000UL, 392 }; 393 394 static const struct tegra_pwm_soc tegra186_pwm_soc = { 395 .num_channels = 1, 396 .max_frequency = 102000000UL, 397 }; 398 399 static const struct tegra_pwm_soc tegra194_pwm_soc = { 400 .num_channels = 1, 401 .max_frequency = 408000000UL, 402 }; 403 404 static const struct of_device_id tegra_pwm_of_match[] = { 405 { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc }, 406 { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc }, 407 { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc }, 408 { } 409 }; 410 MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); 411 412 static const struct dev_pm_ops tegra_pwm_pm_ops = { 413 SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume, 414 NULL) 415 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 416 pm_runtime_force_resume) 417 }; 418 419 static struct platform_driver tegra_pwm_driver = { 420 .driver = { 421 .name = "tegra-pwm", 422 .of_match_table = tegra_pwm_of_match, 423 .pm = &tegra_pwm_pm_ops, 424 }, 425 .probe = tegra_pwm_probe, 426 .remove = tegra_pwm_remove, 427 }; 428 429 module_platform_driver(tegra_pwm_driver); 430 431 MODULE_LICENSE("GPL"); 432 MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>"); 433 MODULE_DESCRIPTION("Tegra PWM controller driver"); 434 MODULE_ALIAS("platform:tegra-pwm"); 435