1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/pwm/pwm-tegra.c 4 * 5 * Tegra pulse-width-modulation controller driver 6 * 7 * Copyright (c) 2010-2020, NVIDIA Corporation. 8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de> 9 * 10 * Overview of Tegra Pulse Width Modulator Register: 11 * 1. 13-bit: Frequency division (SCALE) 12 * 2. 8-bit : Pulse division (DUTY) 13 * 3. 1-bit : Enable bit 14 * 15 * The PWM clock frequency is divided by 256 before subdividing it based 16 * on the programmable frequency division value to generate the required 17 * frequency for PWM output. The maximum output frequency that can be 18 * achieved is (max rate of source clock) / 256. 19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be: 20 * 408 MHz/256 = 1.6 MHz. 21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM. 22 * 23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width. 24 * To achieve 100% duty cycle, program Bit [24] of this register to 25 * 1’b1. In which case the other bits [23:16] are set to don't care. 26 * 27 * Limitations: 28 * - When PWM is disabled, the output is driven to inactive. 29 * - It does not allow the current PWM period to complete and 30 * stops abruptly. 31 * 32 * - If the register is reconfigured while PWM is running, 33 * it does not complete the currently running period. 34 * 35 * - If the user input duty is beyond acceptible limits, 36 * -EINVAL is returned. 37 */ 38 39 #include <linux/clk.h> 40 #include <linux/err.h> 41 #include <linux/io.h> 42 #include <linux/module.h> 43 #include <linux/of.h> 44 #include <linux/of_device.h> 45 #include <linux/pm_opp.h> 46 #include <linux/pwm.h> 47 #include <linux/platform_device.h> 48 #include <linux/pinctrl/consumer.h> 49 #include <linux/pm_runtime.h> 50 #include <linux/slab.h> 51 #include <linux/reset.h> 52 53 #include <soc/tegra/common.h> 54 55 #define PWM_ENABLE (1 << 31) 56 #define PWM_DUTY_WIDTH 8 57 #define PWM_DUTY_SHIFT 16 58 #define PWM_SCALE_WIDTH 13 59 #define PWM_SCALE_SHIFT 0 60 61 struct tegra_pwm_soc { 62 unsigned int num_channels; 63 64 /* Maximum IP frequency for given SoCs */ 65 unsigned long max_frequency; 66 }; 67 68 struct tegra_pwm_chip { 69 struct pwm_chip chip; 70 struct device *dev; 71 72 struct clk *clk; 73 struct reset_control*rst; 74 75 unsigned long clk_rate; 76 unsigned long min_period_ns; 77 78 void __iomem *regs; 79 80 const struct tegra_pwm_soc *soc; 81 }; 82 83 static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) 84 { 85 return container_of(chip, struct tegra_pwm_chip, chip); 86 } 87 88 static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num) 89 { 90 return readl(chip->regs + (num << 4)); 91 } 92 93 static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num, 94 unsigned long val) 95 { 96 writel(val, chip->regs + (num << 4)); 97 } 98 99 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 100 int duty_ns, int period_ns) 101 { 102 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 103 unsigned long long c = duty_ns, hz; 104 unsigned long rate, required_clk_rate; 105 u32 val = 0; 106 int err; 107 108 /* 109 * Convert from duty_ns / period_ns to a fixed number of duty ticks 110 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the 111 * nearest integer during division. 112 */ 113 c *= (1 << PWM_DUTY_WIDTH); 114 c = DIV_ROUND_CLOSEST_ULL(c, period_ns); 115 116 val = (u32)c << PWM_DUTY_SHIFT; 117 118 /* 119 * min period = max clock limit >> PWM_DUTY_WIDTH 120 */ 121 if (period_ns < pc->min_period_ns) 122 return -EINVAL; 123 124 /* 125 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) 126 * cycles at the PWM clock rate will take period_ns nanoseconds. 127 * 128 * num_channels: If single instance of PWM controller has multiple 129 * channels (e.g. Tegra210 or older) then it is not possible to 130 * configure separate clock rates to each of the channels, in such 131 * case the value stored during probe will be referred. 132 * 133 * If every PWM controller instance has one channel respectively, i.e. 134 * nums_channels == 1 then only the clock rate can be modified 135 * dynamically (e.g. Tegra186 or Tegra194). 136 */ 137 if (pc->soc->num_channels == 1) { 138 /* 139 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches 140 * with the maximum possible rate that the controller can 141 * provide. Any further lower value can be derived by setting 142 * PFM bits[0:12]. 143 * 144 * required_clk_rate is a reference rate for source clock and 145 * it is derived based on user requested period. By setting the 146 * source clock rate as required_clk_rate, PWM controller will 147 * be able to configure the requested period. 148 */ 149 required_clk_rate = 150 (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH; 151 152 err = dev_pm_opp_set_rate(pc->dev, required_clk_rate); 153 if (err < 0) 154 return -EINVAL; 155 156 /* Store the new rate for further references */ 157 pc->clk_rate = clk_get_rate(pc->clk); 158 } 159 160 rate = pc->clk_rate >> PWM_DUTY_WIDTH; 161 162 /* Consider precision in PWM_SCALE_WIDTH rate calculation */ 163 hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns); 164 rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz); 165 166 /* 167 * Since the actual PWM divider is the register's frequency divider 168 * field plus 1, we need to decrement to get the correct value to 169 * write to the register. 170 */ 171 if (rate > 0) 172 rate--; 173 174 /* 175 * Make sure that the rate will fit in the register's frequency 176 * divider field. 177 */ 178 if (rate >> PWM_SCALE_WIDTH) 179 return -EINVAL; 180 181 val |= rate << PWM_SCALE_SHIFT; 182 183 /* 184 * If the PWM channel is disabled, make sure to turn on the clock 185 * before writing the register. Otherwise, keep it enabled. 186 */ 187 if (!pwm_is_enabled(pwm)) { 188 err = pm_runtime_resume_and_get(pc->dev); 189 if (err) 190 return err; 191 } else 192 val |= PWM_ENABLE; 193 194 pwm_writel(pc, pwm->hwpwm, val); 195 196 /* 197 * If the PWM is not enabled, turn the clock off again to save power. 198 */ 199 if (!pwm_is_enabled(pwm)) 200 pm_runtime_put(pc->dev); 201 202 return 0; 203 } 204 205 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 206 { 207 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 208 int rc = 0; 209 u32 val; 210 211 rc = pm_runtime_resume_and_get(pc->dev); 212 if (rc) 213 return rc; 214 215 val = pwm_readl(pc, pwm->hwpwm); 216 val |= PWM_ENABLE; 217 pwm_writel(pc, pwm->hwpwm, val); 218 219 return 0; 220 } 221 222 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 223 { 224 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 225 u32 val; 226 227 val = pwm_readl(pc, pwm->hwpwm); 228 val &= ~PWM_ENABLE; 229 pwm_writel(pc, pwm->hwpwm, val); 230 231 pm_runtime_put_sync(pc->dev); 232 } 233 234 static const struct pwm_ops tegra_pwm_ops = { 235 .config = tegra_pwm_config, 236 .enable = tegra_pwm_enable, 237 .disable = tegra_pwm_disable, 238 .owner = THIS_MODULE, 239 }; 240 241 static int tegra_pwm_probe(struct platform_device *pdev) 242 { 243 struct tegra_pwm_chip *pwm; 244 int ret; 245 246 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); 247 if (!pwm) 248 return -ENOMEM; 249 250 pwm->soc = of_device_get_match_data(&pdev->dev); 251 pwm->dev = &pdev->dev; 252 253 pwm->regs = devm_platform_ioremap_resource(pdev, 0); 254 if (IS_ERR(pwm->regs)) 255 return PTR_ERR(pwm->regs); 256 257 platform_set_drvdata(pdev, pwm); 258 259 pwm->clk = devm_clk_get(&pdev->dev, NULL); 260 if (IS_ERR(pwm->clk)) 261 return PTR_ERR(pwm->clk); 262 263 ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 264 if (ret) 265 return ret; 266 267 pm_runtime_enable(&pdev->dev); 268 ret = pm_runtime_resume_and_get(&pdev->dev); 269 if (ret) 270 return ret; 271 272 /* Set maximum frequency of the IP */ 273 ret = dev_pm_opp_set_rate(pwm->dev, pwm->soc->max_frequency); 274 if (ret < 0) { 275 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); 276 goto put_pm; 277 } 278 279 /* 280 * The requested and configured frequency may differ due to 281 * clock register resolutions. Get the configured frequency 282 * so that PWM period can be calculated more accurately. 283 */ 284 pwm->clk_rate = clk_get_rate(pwm->clk); 285 286 /* Set minimum limit of PWM period for the IP */ 287 pwm->min_period_ns = 288 (NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1; 289 290 pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); 291 if (IS_ERR(pwm->rst)) { 292 ret = PTR_ERR(pwm->rst); 293 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret); 294 goto put_pm; 295 } 296 297 reset_control_deassert(pwm->rst); 298 299 pwm->chip.dev = &pdev->dev; 300 pwm->chip.ops = &tegra_pwm_ops; 301 pwm->chip.npwm = pwm->soc->num_channels; 302 303 ret = pwmchip_add(&pwm->chip); 304 if (ret < 0) { 305 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 306 reset_control_assert(pwm->rst); 307 goto put_pm; 308 } 309 310 pm_runtime_put(&pdev->dev); 311 312 return 0; 313 put_pm: 314 pm_runtime_put_sync_suspend(&pdev->dev); 315 pm_runtime_force_suspend(&pdev->dev); 316 return ret; 317 } 318 319 static int tegra_pwm_remove(struct platform_device *pdev) 320 { 321 struct tegra_pwm_chip *pc = platform_get_drvdata(pdev); 322 323 pwmchip_remove(&pc->chip); 324 325 reset_control_assert(pc->rst); 326 327 pm_runtime_force_suspend(&pdev->dev); 328 329 return 0; 330 } 331 332 static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev) 333 { 334 struct tegra_pwm_chip *pc = dev_get_drvdata(dev); 335 int err; 336 337 clk_disable_unprepare(pc->clk); 338 339 err = pinctrl_pm_select_sleep_state(dev); 340 if (err) { 341 clk_prepare_enable(pc->clk); 342 return err; 343 } 344 345 return 0; 346 } 347 348 static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev) 349 { 350 struct tegra_pwm_chip *pc = dev_get_drvdata(dev); 351 int err; 352 353 err = pinctrl_pm_select_default_state(dev); 354 if (err) 355 return err; 356 357 err = clk_prepare_enable(pc->clk); 358 if (err) { 359 pinctrl_pm_select_sleep_state(dev); 360 return err; 361 } 362 363 return 0; 364 } 365 366 static const struct tegra_pwm_soc tegra20_pwm_soc = { 367 .num_channels = 4, 368 .max_frequency = 48000000UL, 369 }; 370 371 static const struct tegra_pwm_soc tegra186_pwm_soc = { 372 .num_channels = 1, 373 .max_frequency = 102000000UL, 374 }; 375 376 static const struct tegra_pwm_soc tegra194_pwm_soc = { 377 .num_channels = 1, 378 .max_frequency = 408000000UL, 379 }; 380 381 static const struct of_device_id tegra_pwm_of_match[] = { 382 { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc }, 383 { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc }, 384 { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc }, 385 { } 386 }; 387 MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); 388 389 static const struct dev_pm_ops tegra_pwm_pm_ops = { 390 SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume, 391 NULL) 392 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 393 pm_runtime_force_resume) 394 }; 395 396 static struct platform_driver tegra_pwm_driver = { 397 .driver = { 398 .name = "tegra-pwm", 399 .of_match_table = tegra_pwm_of_match, 400 .pm = &tegra_pwm_pm_ops, 401 }, 402 .probe = tegra_pwm_probe, 403 .remove = tegra_pwm_remove, 404 }; 405 406 module_platform_driver(tegra_pwm_driver); 407 408 MODULE_LICENSE("GPL"); 409 MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>"); 410 MODULE_DESCRIPTION("Tegra PWM controller driver"); 411 MODULE_ALIAS("platform:tegra-pwm"); 412