1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for Allwinner sun4i Pulse Width Modulation Controller 4 * 5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> 6 * 7 * Limitations: 8 * - When outputing the source clock directly, the PWM logic will be bypassed 9 * and the currently running period is not guaranteed to be completed 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/jiffies.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/platform_device.h> 22 #include <linux/pwm.h> 23 #include <linux/reset.h> 24 #include <linux/slab.h> 25 #include <linux/spinlock.h> 26 #include <linux/time.h> 27 28 #define PWM_CTRL_REG 0x0 29 30 #define PWM_CH_PRD_BASE 0x4 31 #define PWM_CH_PRD_OFFSET 0x4 32 #define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch)) 33 34 #define PWMCH_OFFSET 15 35 #define PWM_PRESCAL_MASK GENMASK(3, 0) 36 #define PWM_PRESCAL_OFF 0 37 #define PWM_EN BIT(4) 38 #define PWM_ACT_STATE BIT(5) 39 #define PWM_CLK_GATING BIT(6) 40 #define PWM_MODE BIT(7) 41 #define PWM_PULSE BIT(8) 42 #define PWM_BYPASS BIT(9) 43 44 #define PWM_RDY_BASE 28 45 #define PWM_RDY_OFFSET 1 46 #define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch)) 47 48 #define PWM_PRD(prd) (((prd) - 1) << 16) 49 #define PWM_PRD_MASK GENMASK(15, 0) 50 51 #define PWM_DTY_MASK GENMASK(15, 0) 52 53 #define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1) 54 #define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK) 55 #define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK) 56 57 #define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET)) 58 59 static const u32 prescaler_table[] = { 60 120, 61 180, 62 240, 63 360, 64 480, 65 0, 66 0, 67 0, 68 12000, 69 24000, 70 36000, 71 48000, 72 72000, 73 0, 74 0, 75 0, /* Actually 1 but tested separately */ 76 }; 77 78 struct sun4i_pwm_data { 79 bool has_prescaler_bypass; 80 bool has_direct_mod_clk_output; 81 unsigned int npwm; 82 }; 83 84 struct sun4i_pwm_chip { 85 struct pwm_chip chip; 86 struct clk *bus_clk; 87 struct clk *clk; 88 struct reset_control *rst; 89 void __iomem *base; 90 spinlock_t ctrl_lock; 91 const struct sun4i_pwm_data *data; 92 }; 93 94 static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip) 95 { 96 return container_of(chip, struct sun4i_pwm_chip, chip); 97 } 98 99 static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip, 100 unsigned long offset) 101 { 102 return readl(chip->base + offset); 103 } 104 105 static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip, 106 u32 val, unsigned long offset) 107 { 108 writel(val, chip->base + offset); 109 } 110 111 static void sun4i_pwm_get_state(struct pwm_chip *chip, 112 struct pwm_device *pwm, 113 struct pwm_state *state) 114 { 115 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); 116 u64 clk_rate, tmp; 117 u32 val; 118 unsigned int prescaler; 119 120 clk_rate = clk_get_rate(sun4i_pwm->clk); 121 122 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); 123 124 /* 125 * PWM chapter in H6 manual has a diagram which explains that if bypass 126 * bit is set, no other setting has any meaning. Even more, experiment 127 * proved that also enable bit is ignored in this case. 128 */ 129 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && 130 sun4i_pwm->data->has_direct_mod_clk_output) { 131 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); 132 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); 133 state->polarity = PWM_POLARITY_NORMAL; 134 state->enabled = true; 135 return; 136 } 137 138 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && 139 sun4i_pwm->data->has_prescaler_bypass) 140 prescaler = 1; 141 else 142 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; 143 144 if (prescaler == 0) 145 return; 146 147 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) 148 state->polarity = PWM_POLARITY_NORMAL; 149 else 150 state->polarity = PWM_POLARITY_INVERSED; 151 152 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == 153 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) 154 state->enabled = true; 155 else 156 state->enabled = false; 157 158 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm)); 159 160 tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val); 161 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 162 163 tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val); 164 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 165 } 166 167 static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm, 168 const struct pwm_state *state, 169 u32 *dty, u32 *prd, unsigned int *prsclr, 170 bool *bypass) 171 { 172 u64 clk_rate, div = 0; 173 unsigned int prescaler = 0; 174 175 clk_rate = clk_get_rate(sun4i_pwm->clk); 176 177 *bypass = sun4i_pwm->data->has_direct_mod_clk_output && 178 state->enabled && 179 (state->period * clk_rate >= NSEC_PER_SEC) && 180 (state->period * clk_rate < 2 * NSEC_PER_SEC) && 181 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); 182 183 /* Skip calculation of other parameters if we bypass them */ 184 if (*bypass) 185 return 0; 186 187 if (sun4i_pwm->data->has_prescaler_bypass) { 188 /* First, test without any prescaler when available */ 189 prescaler = PWM_PRESCAL_MASK; 190 /* 191 * When not using any prescaler, the clock period in nanoseconds 192 * is not an integer so round it half up instead of 193 * truncating to get less surprising values. 194 */ 195 div = clk_rate * state->period + NSEC_PER_SEC / 2; 196 do_div(div, NSEC_PER_SEC); 197 if (div - 1 > PWM_PRD_MASK) 198 prescaler = 0; 199 } 200 201 if (prescaler == 0) { 202 /* Go up from the first divider */ 203 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) { 204 unsigned int pval = prescaler_table[prescaler]; 205 206 if (!pval) 207 continue; 208 209 div = clk_rate; 210 do_div(div, pval); 211 div = div * state->period; 212 do_div(div, NSEC_PER_SEC); 213 if (div - 1 <= PWM_PRD_MASK) 214 break; 215 } 216 217 if (div - 1 > PWM_PRD_MASK) 218 return -EINVAL; 219 } 220 221 *prd = div; 222 div *= state->duty_cycle; 223 do_div(div, state->period); 224 *dty = div; 225 *prsclr = prescaler; 226 227 return 0; 228 } 229 230 static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 231 const struct pwm_state *state) 232 { 233 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); 234 struct pwm_state cstate; 235 u32 ctrl, duty = 0, period = 0, val; 236 int ret; 237 unsigned int delay_us, prescaler = 0; 238 bool bypass; 239 240 pwm_get_state(pwm, &cstate); 241 242 if (!cstate.enabled) { 243 ret = clk_prepare_enable(sun4i_pwm->clk); 244 if (ret) { 245 dev_err(chip->dev, "failed to enable PWM clock\n"); 246 return ret; 247 } 248 } 249 250 ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler, 251 &bypass); 252 if (ret) { 253 dev_err(chip->dev, "period exceeds the maximum value\n"); 254 if (!cstate.enabled) 255 clk_disable_unprepare(sun4i_pwm->clk); 256 return ret; 257 } 258 259 spin_lock(&sun4i_pwm->ctrl_lock); 260 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); 261 262 if (sun4i_pwm->data->has_direct_mod_clk_output) { 263 if (bypass) { 264 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); 265 /* We can skip other parameter */ 266 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); 267 spin_unlock(&sun4i_pwm->ctrl_lock); 268 return 0; 269 } 270 271 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); 272 } 273 274 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { 275 /* Prescaler changed, the clock has to be gated */ 276 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); 277 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); 278 279 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); 280 ctrl |= BIT_CH(prescaler, pwm->hwpwm); 281 } 282 283 val = (duty & PWM_DTY_MASK) | PWM_PRD(period); 284 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); 285 286 if (state->polarity != PWM_POLARITY_NORMAL) 287 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); 288 else 289 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); 290 291 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); 292 293 if (state->enabled) 294 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); 295 296 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); 297 298 spin_unlock(&sun4i_pwm->ctrl_lock); 299 300 if (state->enabled) 301 return 0; 302 303 /* We need a full period to elapse before disabling the channel. */ 304 delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC); 305 if ((delay_us / 500) > MAX_UDELAY_MS) 306 msleep(delay_us / 1000 + 1); 307 else 308 usleep_range(delay_us, delay_us * 2); 309 310 spin_lock(&sun4i_pwm->ctrl_lock); 311 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); 312 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); 313 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm); 314 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); 315 spin_unlock(&sun4i_pwm->ctrl_lock); 316 317 clk_disable_unprepare(sun4i_pwm->clk); 318 319 return 0; 320 } 321 322 static const struct pwm_ops sun4i_pwm_ops = { 323 .apply = sun4i_pwm_apply, 324 .get_state = sun4i_pwm_get_state, 325 .owner = THIS_MODULE, 326 }; 327 328 static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = { 329 .has_prescaler_bypass = false, 330 .npwm = 2, 331 }; 332 333 static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = { 334 .has_prescaler_bypass = true, 335 .npwm = 2, 336 }; 337 338 static const struct sun4i_pwm_data sun4i_pwm_single_bypass = { 339 .has_prescaler_bypass = true, 340 .npwm = 1, 341 }; 342 343 static const struct sun4i_pwm_data sun50i_a64_pwm_data = { 344 .has_prescaler_bypass = true, 345 .has_direct_mod_clk_output = true, 346 .npwm = 1, 347 }; 348 349 static const struct sun4i_pwm_data sun50i_h6_pwm_data = { 350 .has_prescaler_bypass = true, 351 .has_direct_mod_clk_output = true, 352 .npwm = 2, 353 }; 354 355 static const struct of_device_id sun4i_pwm_dt_ids[] = { 356 { 357 .compatible = "allwinner,sun4i-a10-pwm", 358 .data = &sun4i_pwm_dual_nobypass, 359 }, { 360 .compatible = "allwinner,sun5i-a10s-pwm", 361 .data = &sun4i_pwm_dual_bypass, 362 }, { 363 .compatible = "allwinner,sun5i-a13-pwm", 364 .data = &sun4i_pwm_single_bypass, 365 }, { 366 .compatible = "allwinner,sun7i-a20-pwm", 367 .data = &sun4i_pwm_dual_bypass, 368 }, { 369 .compatible = "allwinner,sun8i-h3-pwm", 370 .data = &sun4i_pwm_single_bypass, 371 }, { 372 .compatible = "allwinner,sun50i-a64-pwm", 373 .data = &sun50i_a64_pwm_data, 374 }, { 375 .compatible = "allwinner,sun50i-h6-pwm", 376 .data = &sun50i_h6_pwm_data, 377 }, { 378 /* sentinel */ 379 }, 380 }; 381 MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids); 382 383 static int sun4i_pwm_probe(struct platform_device *pdev) 384 { 385 struct sun4i_pwm_chip *sun4ichip; 386 int ret; 387 388 sun4ichip = devm_kzalloc(&pdev->dev, sizeof(*sun4ichip), GFP_KERNEL); 389 if (!sun4ichip) 390 return -ENOMEM; 391 392 sun4ichip->data = of_device_get_match_data(&pdev->dev); 393 if (!sun4ichip->data) 394 return -ENODEV; 395 396 sun4ichip->base = devm_platform_ioremap_resource(pdev, 0); 397 if (IS_ERR(sun4ichip->base)) 398 return PTR_ERR(sun4ichip->base); 399 400 /* 401 * All hardware variants need a source clock that is divided and 402 * then feeds the counter that defines the output wave form. In the 403 * device tree this clock is either unnamed or called "mod". 404 * Some variants (e.g. H6) need another clock to access the 405 * hardware registers; this is called "bus". 406 * So we request "mod" first (and ignore the corner case that a 407 * parent provides a "mod" clock while the right one would be the 408 * unnamed one of the PWM device) and if this is not found we fall 409 * back to the first clock of the PWM. 410 */ 411 sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod"); 412 if (IS_ERR(sun4ichip->clk)) 413 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk), 414 "get mod clock failed\n"); 415 416 if (!sun4ichip->clk) { 417 sun4ichip->clk = devm_clk_get(&pdev->dev, NULL); 418 if (IS_ERR(sun4ichip->clk)) 419 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk), 420 "get unnamed clock failed\n"); 421 } 422 423 sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); 424 if (IS_ERR(sun4ichip->bus_clk)) 425 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk), 426 "get bus clock failed\n"); 427 428 sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); 429 if (IS_ERR(sun4ichip->rst)) 430 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst), 431 "get reset failed\n"); 432 433 /* Deassert reset */ 434 ret = reset_control_deassert(sun4ichip->rst); 435 if (ret) { 436 dev_err(&pdev->dev, "cannot deassert reset control: %pe\n", 437 ERR_PTR(ret)); 438 return ret; 439 } 440 441 /* 442 * We're keeping the bus clock on for the sake of simplicity. 443 * Actually it only needs to be on for hardware register accesses. 444 */ 445 ret = clk_prepare_enable(sun4ichip->bus_clk); 446 if (ret) { 447 dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n", 448 ERR_PTR(ret)); 449 goto err_bus; 450 } 451 452 sun4ichip->chip.dev = &pdev->dev; 453 sun4ichip->chip.ops = &sun4i_pwm_ops; 454 sun4ichip->chip.npwm = sun4ichip->data->npwm; 455 456 spin_lock_init(&sun4ichip->ctrl_lock); 457 458 ret = pwmchip_add(&sun4ichip->chip); 459 if (ret < 0) { 460 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); 461 goto err_pwm_add; 462 } 463 464 platform_set_drvdata(pdev, sun4ichip); 465 466 return 0; 467 468 err_pwm_add: 469 clk_disable_unprepare(sun4ichip->bus_clk); 470 err_bus: 471 reset_control_assert(sun4ichip->rst); 472 473 return ret; 474 } 475 476 static int sun4i_pwm_remove(struct platform_device *pdev) 477 { 478 struct sun4i_pwm_chip *sun4ichip = platform_get_drvdata(pdev); 479 480 pwmchip_remove(&sun4ichip->chip); 481 482 clk_disable_unprepare(sun4ichip->bus_clk); 483 reset_control_assert(sun4ichip->rst); 484 485 return 0; 486 } 487 488 static struct platform_driver sun4i_pwm_driver = { 489 .driver = { 490 .name = "sun4i-pwm", 491 .of_match_table = sun4i_pwm_dt_ids, 492 }, 493 .probe = sun4i_pwm_probe, 494 .remove = sun4i_pwm_remove, 495 }; 496 module_platform_driver(sun4i_pwm_driver); 497 498 MODULE_ALIAS("platform:sun4i-pwm"); 499 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>"); 500 MODULE_DESCRIPTION("Allwinner sun4i PWM driver"); 501 MODULE_LICENSE("GPL v2"); 502