1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2016 4 * 5 * Author: Gerald Baeza <gerald.baeza@st.com> 6 * 7 * Inspired by timer-stm32.c from Maxime Coquelin 8 * pwm-atmel.c from Bo Shen 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/mfd/stm32-timers.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/platform_device.h> 17 #include <linux/pwm.h> 18 19 #define CCMR_CHANNEL_SHIFT 8 20 #define CCMR_CHANNEL_MASK 0xFF 21 #define MAX_BREAKINPUT 2 22 23 struct stm32_breakinput { 24 u32 index; 25 u32 level; 26 u32 filter; 27 }; 28 29 struct stm32_pwm { 30 struct pwm_chip chip; 31 struct mutex lock; /* protect pwm config/enable */ 32 struct clk *clk; 33 struct regmap *regmap; 34 u32 max_arr; 35 bool have_complementary_output; 36 struct stm32_breakinput breakinputs[MAX_BREAKINPUT]; 37 unsigned int num_breakinputs; 38 u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */ 39 }; 40 41 static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip) 42 { 43 return container_of(chip, struct stm32_pwm, chip); 44 } 45 46 static u32 active_channels(struct stm32_pwm *dev) 47 { 48 u32 ccer; 49 50 regmap_read(dev->regmap, TIM_CCER, &ccer); 51 52 return ccer & TIM_CCER_CCXE; 53 } 54 55 static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value) 56 { 57 switch (ch) { 58 case 0: 59 return regmap_write(dev->regmap, TIM_CCR1, value); 60 case 1: 61 return regmap_write(dev->regmap, TIM_CCR2, value); 62 case 2: 63 return regmap_write(dev->regmap, TIM_CCR3, value); 64 case 3: 65 return regmap_write(dev->regmap, TIM_CCR4, value); 66 } 67 return -EINVAL; 68 } 69 70 #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P) 71 #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E) 72 #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P) 73 #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E) 74 75 /* 76 * Capture using PWM input mode: 77 * ___ ___ 78 * TI[1, 2, 3 or 4]: ........._| |________| 79 * ^0 ^1 ^2 80 * . . . 81 * . . XXXXX 82 * . . XXXXX | 83 * . XXXXX . | 84 * XXXXX . . | 85 * COUNTER: ______XXXXX . . . |_XXX 86 * start^ . . . ^stop 87 * . . . . 88 * v v . v 89 * v 90 * CCR1/CCR3: tx..........t0...........t2 91 * CCR2/CCR4: tx..............t1......... 92 * 93 * DMA burst transfer: | | 94 * v v 95 * DMA buffer: { t0, tx } { t2, t1 } 96 * DMA done: ^ 97 * 98 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 99 * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care) 100 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4 101 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 102 * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1) 103 * 104 * DMA done, compute: 105 * - Period = t2 - t0 106 * - Duty cycle = t1 - t0 107 */ 108 static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm, 109 unsigned long tmo_ms, u32 *raw_prd, 110 u32 *raw_dty) 111 { 112 struct device *parent = priv->chip.dev->parent; 113 enum stm32_timers_dmas dma_id; 114 u32 ccen, ccr; 115 int ret; 116 117 /* Ensure registers have been updated, enable counter and capture */ 118 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 119 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); 120 121 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */ 122 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; 123 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; 124 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; 125 regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen); 126 127 /* 128 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both 129 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event. 130 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 } 131 * or { CCR3, CCR4 }, { CCR3, CCR4 } 132 */ 133 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2, 134 2, tmo_ms); 135 if (ret) 136 goto stop; 137 138 /* Period: t2 - t0 (take care of counter overflow) */ 139 if (priv->capture[0] <= priv->capture[2]) 140 *raw_prd = priv->capture[2] - priv->capture[0]; 141 else 142 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2]; 143 144 /* Duty cycle capture requires at least two capture units */ 145 if (pwm->chip->npwm < 2) 146 *raw_dty = 0; 147 else if (priv->capture[0] <= priv->capture[3]) 148 *raw_dty = priv->capture[3] - priv->capture[0]; 149 else 150 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3]; 151 152 if (*raw_dty > *raw_prd) { 153 /* 154 * Race beetween PWM input and DMA: it may happen 155 * falling edge triggers new capture on TI2/4 before DMA 156 * had a chance to read CCR2/4. It means capture[1] 157 * contains period + duty_cycle. So, subtract period. 158 */ 159 *raw_dty -= *raw_prd; 160 } 161 162 stop: 163 regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0); 164 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 165 166 return ret; 167 } 168 169 static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, 170 struct pwm_capture *result, unsigned long tmo_ms) 171 { 172 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 173 unsigned long long prd, div, dty; 174 unsigned long rate; 175 unsigned int psc = 0, icpsc, scale; 176 u32 raw_prd = 0, raw_dty = 0; 177 int ret = 0; 178 179 mutex_lock(&priv->lock); 180 181 if (active_channels(priv)) { 182 ret = -EBUSY; 183 goto unlock; 184 } 185 186 ret = clk_enable(priv->clk); 187 if (ret) { 188 dev_err(priv->chip.dev, "failed to enable counter clock\n"); 189 goto unlock; 190 } 191 192 rate = clk_get_rate(priv->clk); 193 if (!rate) { 194 ret = -EINVAL; 195 goto clk_dis; 196 } 197 198 /* prescaler: fit timeout window provided by upper layer */ 199 div = (unsigned long long)rate * (unsigned long long)tmo_ms; 200 do_div(div, MSEC_PER_SEC); 201 prd = div; 202 while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) { 203 psc++; 204 div = prd; 205 do_div(div, psc + 1); 206 } 207 regmap_write(priv->regmap, TIM_ARR, priv->max_arr); 208 regmap_write(priv->regmap, TIM_PSC, psc); 209 210 /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */ 211 regmap_update_bits(priv->regmap, 212 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 213 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ? 214 TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 : 215 TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1); 216 217 /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */ 218 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ? 219 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ? 220 TIM_CCER_CC2P : TIM_CCER_CC4P); 221 222 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty); 223 if (ret) 224 goto stop; 225 226 /* 227 * Got a capture. Try to improve accuracy at high rates: 228 * - decrease counter clock prescaler, scale up to max rate. 229 * - use input prescaler, capture once every /2 /4 or /8 edges. 230 */ 231 if (raw_prd) { 232 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */ 233 234 scale = max_arr / min(max_arr, raw_prd); 235 } else { 236 scale = priv->max_arr; /* bellow resolution, use max scale */ 237 } 238 239 if (psc && scale > 1) { 240 /* 2nd measure with new scale */ 241 psc /= scale; 242 regmap_write(priv->regmap, TIM_PSC, psc); 243 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, 244 &raw_dty); 245 if (ret) 246 goto stop; 247 } 248 249 /* Compute intermediate period not to exceed timeout at low rates */ 250 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; 251 do_div(prd, rate); 252 253 for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) { 254 /* input prescaler: also keep arbitrary margin */ 255 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1)) 256 break; 257 if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2)) 258 break; 259 } 260 261 if (!icpsc) 262 goto done; 263 264 /* Last chance to improve period accuracy, using input prescaler */ 265 regmap_update_bits(priv->regmap, 266 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 267 TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC, 268 FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) | 269 FIELD_PREP(TIM_CCMR_IC2PSC, icpsc)); 270 271 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty); 272 if (ret) 273 goto stop; 274 275 if (raw_dty >= (raw_prd >> icpsc)) { 276 /* 277 * We may fall here using input prescaler, when input 278 * capture starts on high side (before falling edge). 279 * Example with icpsc to capture on each 4 events: 280 * 281 * start 1st capture 2nd capture 282 * v v v 283 * ___ _____ _____ _____ _____ ____ 284 * TI1..4 |__| |__| |__| |__| |__| 285 * v v . . . . . v v 286 * icpsc1/3: . 0 . 1 . 2 . 3 . 0 287 * icpsc2/4: 0 1 2 3 0 288 * v v v v 289 * CCR1/3 ......t0..............................t2 290 * CCR2/4 ..t1..............................t1'... 291 * . . . 292 * Capture0: .<----------------------------->. 293 * Capture1: .<-------------------------->. . 294 * . . . 295 * Period: .<------> . . 296 * Low side: .<>. 297 * 298 * Result: 299 * - Period = Capture0 / icpsc 300 * - Duty = Period - Low side = Period - (Capture0 - Capture1) 301 */ 302 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty); 303 } 304 305 done: 306 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; 307 result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc); 308 dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC; 309 result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); 310 stop: 311 regmap_write(priv->regmap, TIM_CCER, 0); 312 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0); 313 regmap_write(priv->regmap, TIM_PSC, 0); 314 clk_dis: 315 clk_disable(priv->clk); 316 unlock: 317 mutex_unlock(&priv->lock); 318 319 return ret; 320 } 321 322 static int stm32_pwm_config(struct stm32_pwm *priv, int ch, 323 int duty_ns, int period_ns) 324 { 325 unsigned long long prd, div, dty; 326 unsigned int prescaler = 0; 327 u32 ccmr, mask, shift; 328 329 /* Period and prescaler values depends on clock rate */ 330 div = (unsigned long long)clk_get_rate(priv->clk) * period_ns; 331 332 do_div(div, NSEC_PER_SEC); 333 prd = div; 334 335 while (div > priv->max_arr) { 336 prescaler++; 337 div = prd; 338 do_div(div, prescaler + 1); 339 } 340 341 prd = div; 342 343 if (prescaler > MAX_TIM_PSC) 344 return -EINVAL; 345 346 /* 347 * All channels share the same prescaler and counter so when two 348 * channels are active at the same time we can't change them 349 */ 350 if (active_channels(priv) & ~(1 << ch * 4)) { 351 u32 psc, arr; 352 353 regmap_read(priv->regmap, TIM_PSC, &psc); 354 regmap_read(priv->regmap, TIM_ARR, &arr); 355 356 if ((psc != prescaler) || (arr != prd - 1)) 357 return -EBUSY; 358 } 359 360 regmap_write(priv->regmap, TIM_PSC, prescaler); 361 regmap_write(priv->regmap, TIM_ARR, prd - 1); 362 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); 363 364 /* Calculate the duty cycles */ 365 dty = prd * duty_ns; 366 do_div(dty, period_ns); 367 368 write_ccrx(priv, ch, dty); 369 370 /* Configure output mode */ 371 shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT; 372 ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift; 373 mask = CCMR_CHANNEL_MASK << shift; 374 375 if (ch < 2) 376 regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr); 377 else 378 regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); 379 380 regmap_update_bits(priv->regmap, TIM_BDTR, 381 TIM_BDTR_MOE | TIM_BDTR_AOE, 382 TIM_BDTR_MOE | TIM_BDTR_AOE); 383 384 return 0; 385 } 386 387 static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch, 388 enum pwm_polarity polarity) 389 { 390 u32 mask; 391 392 mask = TIM_CCER_CC1P << (ch * 4); 393 if (priv->have_complementary_output) 394 mask |= TIM_CCER_CC1NP << (ch * 4); 395 396 regmap_update_bits(priv->regmap, TIM_CCER, mask, 397 polarity == PWM_POLARITY_NORMAL ? 0 : mask); 398 399 return 0; 400 } 401 402 static int stm32_pwm_enable(struct stm32_pwm *priv, int ch) 403 { 404 u32 mask; 405 int ret; 406 407 ret = clk_enable(priv->clk); 408 if (ret) 409 return ret; 410 411 /* Enable channel */ 412 mask = TIM_CCER_CC1E << (ch * 4); 413 if (priv->have_complementary_output) 414 mask |= TIM_CCER_CC1NE << (ch * 4); 415 416 regmap_update_bits(priv->regmap, TIM_CCER, mask, mask); 417 418 /* Make sure that registers are updated */ 419 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 420 421 /* Enable controller */ 422 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); 423 424 return 0; 425 } 426 427 static void stm32_pwm_disable(struct stm32_pwm *priv, int ch) 428 { 429 u32 mask; 430 431 /* Disable channel */ 432 mask = TIM_CCER_CC1E << (ch * 4); 433 if (priv->have_complementary_output) 434 mask |= TIM_CCER_CC1NE << (ch * 4); 435 436 regmap_update_bits(priv->regmap, TIM_CCER, mask, 0); 437 438 /* When all channels are disabled, we can disable the controller */ 439 if (!active_channels(priv)) 440 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 441 442 clk_disable(priv->clk); 443 } 444 445 static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 446 const struct pwm_state *state) 447 { 448 bool enabled; 449 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 450 int ret; 451 452 enabled = pwm->state.enabled; 453 454 if (enabled && !state->enabled) { 455 stm32_pwm_disable(priv, pwm->hwpwm); 456 return 0; 457 } 458 459 if (state->polarity != pwm->state.polarity) 460 stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity); 461 462 ret = stm32_pwm_config(priv, pwm->hwpwm, 463 state->duty_cycle, state->period); 464 if (ret) 465 return ret; 466 467 if (!enabled && state->enabled) 468 ret = stm32_pwm_enable(priv, pwm->hwpwm); 469 470 return ret; 471 } 472 473 static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm, 474 const struct pwm_state *state) 475 { 476 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 477 int ret; 478 479 /* protect common prescaler for all active channels */ 480 mutex_lock(&priv->lock); 481 ret = stm32_pwm_apply(chip, pwm, state); 482 mutex_unlock(&priv->lock); 483 484 return ret; 485 } 486 487 static const struct pwm_ops stm32pwm_ops = { 488 .owner = THIS_MODULE, 489 .apply = stm32_pwm_apply_locked, 490 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL, 491 }; 492 493 static int stm32_pwm_set_breakinput(struct stm32_pwm *priv, 494 const struct stm32_breakinput *bi) 495 { 496 u32 shift = TIM_BDTR_BKF_SHIFT(bi->index); 497 u32 bke = TIM_BDTR_BKE(bi->index); 498 u32 bkp = TIM_BDTR_BKP(bi->index); 499 u32 bkf = TIM_BDTR_BKF(bi->index); 500 u32 mask = bkf | bkp | bke; 501 u32 bdtr; 502 503 bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke; 504 505 if (bi->level) 506 bdtr |= bkp; 507 508 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr); 509 510 regmap_read(priv->regmap, TIM_BDTR, &bdtr); 511 512 return (bdtr & bke) ? 0 : -EINVAL; 513 } 514 515 static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv) 516 { 517 unsigned int i; 518 int ret; 519 520 for (i = 0; i < priv->num_breakinputs; i++) { 521 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]); 522 if (ret < 0) 523 return ret; 524 } 525 526 return 0; 527 } 528 529 static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv, 530 struct device_node *np) 531 { 532 int nb, ret, array_size; 533 unsigned int i; 534 535 nb = of_property_count_elems_of_size(np, "st,breakinput", 536 sizeof(struct stm32_breakinput)); 537 538 /* 539 * Because "st,breakinput" parameter is optional do not make probe 540 * failed if it doesn't exist. 541 */ 542 if (nb <= 0) 543 return 0; 544 545 if (nb > MAX_BREAKINPUT) 546 return -EINVAL; 547 548 priv->num_breakinputs = nb; 549 array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32); 550 ret = of_property_read_u32_array(np, "st,breakinput", 551 (u32 *)priv->breakinputs, array_size); 552 if (ret) 553 return ret; 554 555 for (i = 0; i < priv->num_breakinputs; i++) { 556 if (priv->breakinputs[i].index > 1 || 557 priv->breakinputs[i].level > 1 || 558 priv->breakinputs[i].filter > 15) 559 return -EINVAL; 560 } 561 562 return stm32_pwm_apply_breakinputs(priv); 563 } 564 565 static void stm32_pwm_detect_complementary(struct stm32_pwm *priv) 566 { 567 u32 ccer; 568 569 /* 570 * If complementary bit doesn't exist writing 1 will have no 571 * effect so we can detect it. 572 */ 573 regmap_update_bits(priv->regmap, 574 TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE); 575 regmap_read(priv->regmap, TIM_CCER, &ccer); 576 regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0); 577 578 priv->have_complementary_output = (ccer != 0); 579 } 580 581 static int stm32_pwm_detect_channels(struct stm32_pwm *priv) 582 { 583 u32 ccer; 584 int npwm = 0; 585 586 /* 587 * If channels enable bits don't exist writing 1 will have no 588 * effect so we can detect and count them. 589 */ 590 regmap_update_bits(priv->regmap, 591 TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE); 592 regmap_read(priv->regmap, TIM_CCER, &ccer); 593 regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0); 594 595 if (ccer & TIM_CCER_CC1E) 596 npwm++; 597 598 if (ccer & TIM_CCER_CC2E) 599 npwm++; 600 601 if (ccer & TIM_CCER_CC3E) 602 npwm++; 603 604 if (ccer & TIM_CCER_CC4E) 605 npwm++; 606 607 return npwm; 608 } 609 610 static int stm32_pwm_probe(struct platform_device *pdev) 611 { 612 struct device *dev = &pdev->dev; 613 struct device_node *np = dev->of_node; 614 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); 615 struct stm32_pwm *priv; 616 int ret; 617 618 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 619 if (!priv) 620 return -ENOMEM; 621 622 mutex_init(&priv->lock); 623 priv->regmap = ddata->regmap; 624 priv->clk = ddata->clk; 625 priv->max_arr = ddata->max_arr; 626 priv->chip.of_xlate = of_pwm_xlate_with_flags; 627 priv->chip.of_pwm_n_cells = 3; 628 629 if (!priv->regmap || !priv->clk) 630 return -EINVAL; 631 632 ret = stm32_pwm_probe_breakinputs(priv, np); 633 if (ret) 634 return ret; 635 636 stm32_pwm_detect_complementary(priv); 637 638 priv->chip.base = -1; 639 priv->chip.dev = dev; 640 priv->chip.ops = &stm32pwm_ops; 641 priv->chip.npwm = stm32_pwm_detect_channels(priv); 642 643 ret = pwmchip_add(&priv->chip); 644 if (ret < 0) 645 return ret; 646 647 platform_set_drvdata(pdev, priv); 648 649 return 0; 650 } 651 652 static int stm32_pwm_remove(struct platform_device *pdev) 653 { 654 struct stm32_pwm *priv = platform_get_drvdata(pdev); 655 unsigned int i; 656 657 for (i = 0; i < priv->chip.npwm; i++) 658 pwm_disable(&priv->chip.pwms[i]); 659 660 pwmchip_remove(&priv->chip); 661 662 return 0; 663 } 664 665 static int __maybe_unused stm32_pwm_suspend(struct device *dev) 666 { 667 struct stm32_pwm *priv = dev_get_drvdata(dev); 668 unsigned int i; 669 u32 ccer, mask; 670 671 /* Look for active channels */ 672 ccer = active_channels(priv); 673 674 for (i = 0; i < priv->chip.npwm; i++) { 675 mask = TIM_CCER_CC1E << (i * 4); 676 if (ccer & mask) { 677 dev_err(dev, "PWM %u still in use by consumer %s\n", 678 i, priv->chip.pwms[i].label); 679 return -EBUSY; 680 } 681 } 682 683 return pinctrl_pm_select_sleep_state(dev); 684 } 685 686 static int __maybe_unused stm32_pwm_resume(struct device *dev) 687 { 688 struct stm32_pwm *priv = dev_get_drvdata(dev); 689 int ret; 690 691 ret = pinctrl_pm_select_default_state(dev); 692 if (ret) 693 return ret; 694 695 /* restore breakinput registers that may have been lost in low power */ 696 return stm32_pwm_apply_breakinputs(priv); 697 } 698 699 static SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume); 700 701 static const struct of_device_id stm32_pwm_of_match[] = { 702 { .compatible = "st,stm32-pwm", }, 703 { /* end node */ }, 704 }; 705 MODULE_DEVICE_TABLE(of, stm32_pwm_of_match); 706 707 static struct platform_driver stm32_pwm_driver = { 708 .probe = stm32_pwm_probe, 709 .remove = stm32_pwm_remove, 710 .driver = { 711 .name = "stm32-pwm", 712 .of_match_table = stm32_pwm_of_match, 713 .pm = &stm32_pwm_pm_ops, 714 }, 715 }; 716 module_platform_driver(stm32_pwm_driver); 717 718 MODULE_ALIAS("platform:stm32-pwm"); 719 MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver"); 720 MODULE_LICENSE("GPL v2"); 721