1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2019 Spreadtrum Communications Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/err.h> 8 #include <linux/io.h> 9 #include <linux/math64.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pwm.h> 14 15 #define SPRD_PWM_PRESCALE 0x0 16 #define SPRD_PWM_MOD 0x4 17 #define SPRD_PWM_DUTY 0x8 18 #define SPRD_PWM_ENABLE 0x18 19 20 #define SPRD_PWM_MOD_MAX GENMASK(7, 0) 21 #define SPRD_PWM_DUTY_MSK GENMASK(15, 0) 22 #define SPRD_PWM_PRESCALE_MSK GENMASK(7, 0) 23 #define SPRD_PWM_ENABLE_BIT BIT(0) 24 25 #define SPRD_PWM_CHN_NUM 4 26 #define SPRD_PWM_REGS_SHIFT 5 27 #define SPRD_PWM_CHN_CLKS_NUM 2 28 #define SPRD_PWM_CHN_OUTPUT_CLK 1 29 30 struct sprd_pwm_chn { 31 struct clk_bulk_data clks[SPRD_PWM_CHN_CLKS_NUM]; 32 u32 clk_rate; 33 }; 34 35 struct sprd_pwm_chip { 36 void __iomem *base; 37 struct device *dev; 38 struct pwm_chip chip; 39 int num_pwms; 40 struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM]; 41 }; 42 43 /* 44 * The list of clocks required by PWM channels, and each channel has 2 clocks: 45 * enable clock and pwm clock. 46 */ 47 static const char * const sprd_pwm_clks[] = { 48 "enable0", "pwm0", 49 "enable1", "pwm1", 50 "enable2", "pwm2", 51 "enable3", "pwm3", 52 }; 53 54 static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg) 55 { 56 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); 57 58 return readl_relaxed(spc->base + offset); 59 } 60 61 static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid, 62 u32 reg, u32 val) 63 { 64 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); 65 66 writel_relaxed(val, spc->base + offset); 67 } 68 69 static int sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 70 struct pwm_state *state) 71 { 72 struct sprd_pwm_chip *spc = 73 container_of(chip, struct sprd_pwm_chip, chip); 74 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 75 u32 val, duty, prescale; 76 u64 tmp; 77 int ret; 78 79 /* 80 * The clocks to PWM channel has to be enabled first before 81 * reading to the registers. 82 */ 83 ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, chn->clks); 84 if (ret) { 85 dev_err(spc->dev, "failed to enable pwm%u clocks\n", 86 pwm->hwpwm); 87 return ret; 88 } 89 90 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); 91 if (val & SPRD_PWM_ENABLE_BIT) 92 state->enabled = true; 93 else 94 state->enabled = false; 95 96 /* 97 * The hardware provides a counter that is feed by the source clock. 98 * The period length is (PRESCALE + 1) * MOD counter steps. 99 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. 100 * Thus the period_ns and duty_ns calculation formula should be: 101 * period_ns = NSEC_PER_SEC * (prescale + 1) * mod / clk_rate 102 * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate 103 */ 104 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); 105 prescale = val & SPRD_PWM_PRESCALE_MSK; 106 tmp = (prescale + 1) * NSEC_PER_SEC * SPRD_PWM_MOD_MAX; 107 state->period = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); 108 109 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); 110 duty = val & SPRD_PWM_DUTY_MSK; 111 tmp = (prescale + 1) * NSEC_PER_SEC * duty; 112 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); 113 state->polarity = PWM_POLARITY_NORMAL; 114 115 /* Disable PWM clocks if the PWM channel is not in enable state. */ 116 if (!state->enabled) 117 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks); 118 119 return 0; 120 } 121 122 static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm, 123 int duty_ns, int period_ns) 124 { 125 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 126 u32 prescale, duty; 127 u64 tmp; 128 129 /* 130 * The hardware provides a counter that is feed by the source clock. 131 * The period length is (PRESCALE + 1) * MOD counter steps. 132 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. 133 * 134 * To keep the maths simple we're always using MOD = SPRD_PWM_MOD_MAX. 135 * The value for PRESCALE is selected such that the resulting period 136 * gets the maximal length not bigger than the requested one with the 137 * given settings (MOD = SPRD_PWM_MOD_MAX and input clock). 138 */ 139 duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns; 140 141 tmp = (u64)chn->clk_rate * period_ns; 142 do_div(tmp, NSEC_PER_SEC); 143 prescale = DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1; 144 if (prescale > SPRD_PWM_PRESCALE_MSK) 145 prescale = SPRD_PWM_PRESCALE_MSK; 146 147 /* 148 * Note: Writing DUTY triggers the hardware to actually apply the 149 * values written to MOD and DUTY to the output, so must keep writing 150 * DUTY last. 151 * 152 * The hardware can ensures that current running period is completed 153 * before changing a new configuration to avoid mixed settings. 154 */ 155 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); 156 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); 157 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); 158 159 return 0; 160 } 161 162 static int sprd_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 163 const struct pwm_state *state) 164 { 165 struct sprd_pwm_chip *spc = 166 container_of(chip, struct sprd_pwm_chip, chip); 167 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 168 struct pwm_state *cstate = &pwm->state; 169 int ret; 170 171 if (state->polarity != PWM_POLARITY_NORMAL) 172 return -EINVAL; 173 174 if (state->enabled) { 175 if (!cstate->enabled) { 176 /* 177 * The clocks to PWM channel has to be enabled first 178 * before writing to the registers. 179 */ 180 ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, 181 chn->clks); 182 if (ret) { 183 dev_err(spc->dev, 184 "failed to enable pwm%u clocks\n", 185 pwm->hwpwm); 186 return ret; 187 } 188 } 189 190 ret = sprd_pwm_config(spc, pwm, state->duty_cycle, 191 state->period); 192 if (ret) 193 return ret; 194 195 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1); 196 } else if (cstate->enabled) { 197 /* 198 * Note: After setting SPRD_PWM_ENABLE to zero, the controller 199 * will not wait for current period to be completed, instead it 200 * will stop the PWM channel immediately. 201 */ 202 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0); 203 204 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks); 205 } 206 207 return 0; 208 } 209 210 static const struct pwm_ops sprd_pwm_ops = { 211 .apply = sprd_pwm_apply, 212 .get_state = sprd_pwm_get_state, 213 .owner = THIS_MODULE, 214 }; 215 216 static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc) 217 { 218 struct clk *clk_pwm; 219 int ret, i; 220 221 for (i = 0; i < SPRD_PWM_CHN_NUM; i++) { 222 struct sprd_pwm_chn *chn = &spc->chn[i]; 223 int j; 224 225 for (j = 0; j < SPRD_PWM_CHN_CLKS_NUM; ++j) 226 chn->clks[j].id = 227 sprd_pwm_clks[i * SPRD_PWM_CHN_CLKS_NUM + j]; 228 229 ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_CHN_CLKS_NUM, 230 chn->clks); 231 if (ret) { 232 if (ret == -ENOENT) 233 break; 234 235 return dev_err_probe(spc->dev, ret, 236 "failed to get channel clocks\n"); 237 } 238 239 clk_pwm = chn->clks[SPRD_PWM_CHN_OUTPUT_CLK].clk; 240 chn->clk_rate = clk_get_rate(clk_pwm); 241 } 242 243 if (!i) { 244 dev_err(spc->dev, "no available PWM channels\n"); 245 return -ENODEV; 246 } 247 248 spc->num_pwms = i; 249 250 return 0; 251 } 252 253 static int sprd_pwm_probe(struct platform_device *pdev) 254 { 255 struct sprd_pwm_chip *spc; 256 int ret; 257 258 spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL); 259 if (!spc) 260 return -ENOMEM; 261 262 spc->base = devm_platform_ioremap_resource(pdev, 0); 263 if (IS_ERR(spc->base)) 264 return PTR_ERR(spc->base); 265 266 spc->dev = &pdev->dev; 267 platform_set_drvdata(pdev, spc); 268 269 ret = sprd_pwm_clk_init(spc); 270 if (ret) 271 return ret; 272 273 spc->chip.dev = &pdev->dev; 274 spc->chip.ops = &sprd_pwm_ops; 275 spc->chip.npwm = spc->num_pwms; 276 277 ret = pwmchip_add(&spc->chip); 278 if (ret) 279 dev_err(&pdev->dev, "failed to add PWM chip\n"); 280 281 return ret; 282 } 283 284 static void sprd_pwm_remove(struct platform_device *pdev) 285 { 286 struct sprd_pwm_chip *spc = platform_get_drvdata(pdev); 287 288 pwmchip_remove(&spc->chip); 289 } 290 291 static const struct of_device_id sprd_pwm_of_match[] = { 292 { .compatible = "sprd,ums512-pwm", }, 293 { }, 294 }; 295 MODULE_DEVICE_TABLE(of, sprd_pwm_of_match); 296 297 static struct platform_driver sprd_pwm_driver = { 298 .driver = { 299 .name = "sprd-pwm", 300 .of_match_table = sprd_pwm_of_match, 301 }, 302 .probe = sprd_pwm_probe, 303 .remove_new = sprd_pwm_remove, 304 }; 305 306 module_platform_driver(sprd_pwm_driver); 307 308 MODULE_DESCRIPTION("Spreadtrum PWM Driver"); 309 MODULE_LICENSE("GPL v2"); 310