18aae4b02SBaolin Wang // SPDX-License-Identifier: GPL-2.0 28aae4b02SBaolin Wang /* 38aae4b02SBaolin Wang * Copyright (C) 2019 Spreadtrum Communications Inc. 48aae4b02SBaolin Wang */ 58aae4b02SBaolin Wang 68aae4b02SBaolin Wang #include <linux/clk.h> 78aae4b02SBaolin Wang #include <linux/err.h> 88aae4b02SBaolin Wang #include <linux/io.h> 98aae4b02SBaolin Wang #include <linux/math64.h> 108aae4b02SBaolin Wang #include <linux/module.h> 118aae4b02SBaolin Wang #include <linux/platform_device.h> 128aae4b02SBaolin Wang #include <linux/pwm.h> 138aae4b02SBaolin Wang 148aae4b02SBaolin Wang #define SPRD_PWM_PRESCALE 0x0 158aae4b02SBaolin Wang #define SPRD_PWM_MOD 0x4 168aae4b02SBaolin Wang #define SPRD_PWM_DUTY 0x8 178aae4b02SBaolin Wang #define SPRD_PWM_ENABLE 0x18 188aae4b02SBaolin Wang 198aae4b02SBaolin Wang #define SPRD_PWM_MOD_MAX GENMASK(7, 0) 208aae4b02SBaolin Wang #define SPRD_PWM_DUTY_MSK GENMASK(15, 0) 218aae4b02SBaolin Wang #define SPRD_PWM_PRESCALE_MSK GENMASK(7, 0) 228aae4b02SBaolin Wang #define SPRD_PWM_ENABLE_BIT BIT(0) 238aae4b02SBaolin Wang 248aae4b02SBaolin Wang #define SPRD_PWM_CHN_NUM 4 258aae4b02SBaolin Wang #define SPRD_PWM_REGS_SHIFT 5 268aae4b02SBaolin Wang #define SPRD_PWM_CHN_CLKS_NUM 2 278aae4b02SBaolin Wang #define SPRD_PWM_CHN_OUTPUT_CLK 1 288aae4b02SBaolin Wang 298aae4b02SBaolin Wang struct sprd_pwm_chn { 308aae4b02SBaolin Wang struct clk_bulk_data clks[SPRD_PWM_CHN_CLKS_NUM]; 318aae4b02SBaolin Wang u32 clk_rate; 328aae4b02SBaolin Wang }; 338aae4b02SBaolin Wang 348aae4b02SBaolin Wang struct sprd_pwm_chip { 358aae4b02SBaolin Wang void __iomem *base; 368aae4b02SBaolin Wang struct device *dev; 378aae4b02SBaolin Wang struct pwm_chip chip; 388aae4b02SBaolin Wang int num_pwms; 398aae4b02SBaolin Wang struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM]; 408aae4b02SBaolin Wang }; 418aae4b02SBaolin Wang 428aae4b02SBaolin Wang /* 438aae4b02SBaolin Wang * The list of clocks required by PWM channels, and each channel has 2 clocks: 448aae4b02SBaolin Wang * enable clock and pwm clock. 458aae4b02SBaolin Wang */ 468aae4b02SBaolin Wang static const char * const sprd_pwm_clks[] = { 478aae4b02SBaolin Wang "enable0", "pwm0", 488aae4b02SBaolin Wang "enable1", "pwm1", 498aae4b02SBaolin Wang "enable2", "pwm2", 508aae4b02SBaolin Wang "enable3", "pwm3", 518aae4b02SBaolin Wang }; 528aae4b02SBaolin Wang 538aae4b02SBaolin Wang static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg) 548aae4b02SBaolin Wang { 558aae4b02SBaolin Wang u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); 568aae4b02SBaolin Wang 578aae4b02SBaolin Wang return readl_relaxed(spc->base + offset); 588aae4b02SBaolin Wang } 598aae4b02SBaolin Wang 608aae4b02SBaolin Wang static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid, 618aae4b02SBaolin Wang u32 reg, u32 val) 628aae4b02SBaolin Wang { 638aae4b02SBaolin Wang u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); 648aae4b02SBaolin Wang 658aae4b02SBaolin Wang writel_relaxed(val, spc->base + offset); 668aae4b02SBaolin Wang } 678aae4b02SBaolin Wang 688aae4b02SBaolin Wang static void sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 698aae4b02SBaolin Wang struct pwm_state *state) 708aae4b02SBaolin Wang { 718aae4b02SBaolin Wang struct sprd_pwm_chip *spc = 728aae4b02SBaolin Wang container_of(chip, struct sprd_pwm_chip, chip); 738aae4b02SBaolin Wang struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 748aae4b02SBaolin Wang u32 val, duty, prescale; 758aae4b02SBaolin Wang u64 tmp; 768aae4b02SBaolin Wang int ret; 778aae4b02SBaolin Wang 788aae4b02SBaolin Wang /* 798aae4b02SBaolin Wang * The clocks to PWM channel has to be enabled first before 808aae4b02SBaolin Wang * reading to the registers. 818aae4b02SBaolin Wang */ 828aae4b02SBaolin Wang ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, chn->clks); 838aae4b02SBaolin Wang if (ret) { 848aae4b02SBaolin Wang dev_err(spc->dev, "failed to enable pwm%u clocks\n", 858aae4b02SBaolin Wang pwm->hwpwm); 868aae4b02SBaolin Wang return; 878aae4b02SBaolin Wang } 888aae4b02SBaolin Wang 898aae4b02SBaolin Wang val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); 908aae4b02SBaolin Wang if (val & SPRD_PWM_ENABLE_BIT) 918aae4b02SBaolin Wang state->enabled = true; 928aae4b02SBaolin Wang else 938aae4b02SBaolin Wang state->enabled = false; 948aae4b02SBaolin Wang 958aae4b02SBaolin Wang /* 968aae4b02SBaolin Wang * The hardware provides a counter that is feed by the source clock. 978aae4b02SBaolin Wang * The period length is (PRESCALE + 1) * MOD counter steps. 988aae4b02SBaolin Wang * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. 998aae4b02SBaolin Wang * Thus the period_ns and duty_ns calculation formula should be: 1008aae4b02SBaolin Wang * period_ns = NSEC_PER_SEC * (prescale + 1) * mod / clk_rate 1018aae4b02SBaolin Wang * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate 1028aae4b02SBaolin Wang */ 1038aae4b02SBaolin Wang val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); 1048aae4b02SBaolin Wang prescale = val & SPRD_PWM_PRESCALE_MSK; 1058aae4b02SBaolin Wang tmp = (prescale + 1) * NSEC_PER_SEC * SPRD_PWM_MOD_MAX; 1068aae4b02SBaolin Wang state->period = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); 1078aae4b02SBaolin Wang 1088aae4b02SBaolin Wang val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); 1098aae4b02SBaolin Wang duty = val & SPRD_PWM_DUTY_MSK; 1108aae4b02SBaolin Wang tmp = (prescale + 1) * NSEC_PER_SEC * duty; 1118aae4b02SBaolin Wang state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); 1128aae4b02SBaolin Wang 1138aae4b02SBaolin Wang /* Disable PWM clocks if the PWM channel is not in enable state. */ 1148aae4b02SBaolin Wang if (!state->enabled) 1158aae4b02SBaolin Wang clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks); 1168aae4b02SBaolin Wang } 1178aae4b02SBaolin Wang 1188aae4b02SBaolin Wang static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm, 1198aae4b02SBaolin Wang int duty_ns, int period_ns) 1208aae4b02SBaolin Wang { 1218aae4b02SBaolin Wang struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 1228aae4b02SBaolin Wang u32 prescale, duty; 1238aae4b02SBaolin Wang u64 tmp; 1248aae4b02SBaolin Wang 1258aae4b02SBaolin Wang /* 1268aae4b02SBaolin Wang * The hardware provides a counter that is feed by the source clock. 1278aae4b02SBaolin Wang * The period length is (PRESCALE + 1) * MOD counter steps. 1288aae4b02SBaolin Wang * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. 1298aae4b02SBaolin Wang * 1308aae4b02SBaolin Wang * To keep the maths simple we're always using MOD = SPRD_PWM_MOD_MAX. 1318aae4b02SBaolin Wang * The value for PRESCALE is selected such that the resulting period 1328aae4b02SBaolin Wang * gets the maximal length not bigger than the requested one with the 1338aae4b02SBaolin Wang * given settings (MOD = SPRD_PWM_MOD_MAX and input clock). 1348aae4b02SBaolin Wang */ 1358aae4b02SBaolin Wang duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns; 1368aae4b02SBaolin Wang 1378aae4b02SBaolin Wang tmp = (u64)chn->clk_rate * period_ns; 1388aae4b02SBaolin Wang do_div(tmp, NSEC_PER_SEC); 1398aae4b02SBaolin Wang prescale = DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1; 1408aae4b02SBaolin Wang if (prescale > SPRD_PWM_PRESCALE_MSK) 1418aae4b02SBaolin Wang prescale = SPRD_PWM_PRESCALE_MSK; 1428aae4b02SBaolin Wang 1438aae4b02SBaolin Wang /* 1448aae4b02SBaolin Wang * Note: Writing DUTY triggers the hardware to actually apply the 1458aae4b02SBaolin Wang * values written to MOD and DUTY to the output, so must keep writing 1468aae4b02SBaolin Wang * DUTY last. 1478aae4b02SBaolin Wang * 1488aae4b02SBaolin Wang * The hardware can ensures that current running period is completed 1498aae4b02SBaolin Wang * before changing a new configuration to avoid mixed settings. 1508aae4b02SBaolin Wang */ 1518aae4b02SBaolin Wang sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); 1528aae4b02SBaolin Wang sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); 1538aae4b02SBaolin Wang sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); 1548aae4b02SBaolin Wang 1558aae4b02SBaolin Wang return 0; 1568aae4b02SBaolin Wang } 1578aae4b02SBaolin Wang 1588aae4b02SBaolin Wang static int sprd_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 15971523d18SUwe Kleine-König const struct pwm_state *state) 1608aae4b02SBaolin Wang { 1618aae4b02SBaolin Wang struct sprd_pwm_chip *spc = 1628aae4b02SBaolin Wang container_of(chip, struct sprd_pwm_chip, chip); 1638aae4b02SBaolin Wang struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 1648aae4b02SBaolin Wang struct pwm_state *cstate = &pwm->state; 1658aae4b02SBaolin Wang int ret; 1668aae4b02SBaolin Wang 167*09081c9bSUwe Kleine-König if (state->polarity != PWM_POLARITY_NORMAL) 168*09081c9bSUwe Kleine-König return -EINVAL; 169*09081c9bSUwe Kleine-König 1708aae4b02SBaolin Wang if (state->enabled) { 1718aae4b02SBaolin Wang if (!cstate->enabled) { 1728aae4b02SBaolin Wang /* 1738aae4b02SBaolin Wang * The clocks to PWM channel has to be enabled first 1748aae4b02SBaolin Wang * before writing to the registers. 1758aae4b02SBaolin Wang */ 1768aae4b02SBaolin Wang ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, 1778aae4b02SBaolin Wang chn->clks); 1788aae4b02SBaolin Wang if (ret) { 1798aae4b02SBaolin Wang dev_err(spc->dev, 1808aae4b02SBaolin Wang "failed to enable pwm%u clocks\n", 1818aae4b02SBaolin Wang pwm->hwpwm); 1828aae4b02SBaolin Wang return ret; 1838aae4b02SBaolin Wang } 1848aae4b02SBaolin Wang } 1858aae4b02SBaolin Wang 1868aae4b02SBaolin Wang if (state->period != cstate->period || 1878aae4b02SBaolin Wang state->duty_cycle != cstate->duty_cycle) { 1888aae4b02SBaolin Wang ret = sprd_pwm_config(spc, pwm, state->duty_cycle, 1898aae4b02SBaolin Wang state->period); 1908aae4b02SBaolin Wang if (ret) 1918aae4b02SBaolin Wang return ret; 1928aae4b02SBaolin Wang } 1938aae4b02SBaolin Wang 1948aae4b02SBaolin Wang sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1); 1958aae4b02SBaolin Wang } else if (cstate->enabled) { 1968aae4b02SBaolin Wang /* 1978aae4b02SBaolin Wang * Note: After setting SPRD_PWM_ENABLE to zero, the controller 1988aae4b02SBaolin Wang * will not wait for current period to be completed, instead it 1998aae4b02SBaolin Wang * will stop the PWM channel immediately. 2008aae4b02SBaolin Wang */ 2018aae4b02SBaolin Wang sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0); 2028aae4b02SBaolin Wang 2038aae4b02SBaolin Wang clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks); 2048aae4b02SBaolin Wang } 2058aae4b02SBaolin Wang 2068aae4b02SBaolin Wang return 0; 2078aae4b02SBaolin Wang } 2088aae4b02SBaolin Wang 2098aae4b02SBaolin Wang static const struct pwm_ops sprd_pwm_ops = { 2108aae4b02SBaolin Wang .apply = sprd_pwm_apply, 2118aae4b02SBaolin Wang .get_state = sprd_pwm_get_state, 2128aae4b02SBaolin Wang .owner = THIS_MODULE, 2138aae4b02SBaolin Wang }; 2148aae4b02SBaolin Wang 2158aae4b02SBaolin Wang static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc) 2168aae4b02SBaolin Wang { 2178aae4b02SBaolin Wang struct clk *clk_pwm; 2188aae4b02SBaolin Wang int ret, i; 2198aae4b02SBaolin Wang 2208aae4b02SBaolin Wang for (i = 0; i < SPRD_PWM_CHN_NUM; i++) { 2218aae4b02SBaolin Wang struct sprd_pwm_chn *chn = &spc->chn[i]; 2228aae4b02SBaolin Wang int j; 2238aae4b02SBaolin Wang 2248aae4b02SBaolin Wang for (j = 0; j < SPRD_PWM_CHN_CLKS_NUM; ++j) 2258aae4b02SBaolin Wang chn->clks[j].id = 2268aae4b02SBaolin Wang sprd_pwm_clks[i * SPRD_PWM_CHN_CLKS_NUM + j]; 2278aae4b02SBaolin Wang 2288aae4b02SBaolin Wang ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_CHN_CLKS_NUM, 2298aae4b02SBaolin Wang chn->clks); 2308aae4b02SBaolin Wang if (ret) { 2318aae4b02SBaolin Wang if (ret == -ENOENT) 2328aae4b02SBaolin Wang break; 2338aae4b02SBaolin Wang 234793bb636SKrzysztof Kozlowski return dev_err_probe(spc->dev, ret, 2358aae4b02SBaolin Wang "failed to get channel clocks\n"); 2368aae4b02SBaolin Wang } 2378aae4b02SBaolin Wang 2388aae4b02SBaolin Wang clk_pwm = chn->clks[SPRD_PWM_CHN_OUTPUT_CLK].clk; 2398aae4b02SBaolin Wang chn->clk_rate = clk_get_rate(clk_pwm); 2408aae4b02SBaolin Wang } 2418aae4b02SBaolin Wang 2428aae4b02SBaolin Wang if (!i) { 2438aae4b02SBaolin Wang dev_err(spc->dev, "no available PWM channels\n"); 2448aae4b02SBaolin Wang return -ENODEV; 2458aae4b02SBaolin Wang } 2468aae4b02SBaolin Wang 2478aae4b02SBaolin Wang spc->num_pwms = i; 2488aae4b02SBaolin Wang 2498aae4b02SBaolin Wang return 0; 2508aae4b02SBaolin Wang } 2518aae4b02SBaolin Wang 2528aae4b02SBaolin Wang static int sprd_pwm_probe(struct platform_device *pdev) 2538aae4b02SBaolin Wang { 2548aae4b02SBaolin Wang struct sprd_pwm_chip *spc; 2558aae4b02SBaolin Wang int ret; 2568aae4b02SBaolin Wang 2578aae4b02SBaolin Wang spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL); 2588aae4b02SBaolin Wang if (!spc) 2598aae4b02SBaolin Wang return -ENOMEM; 2608aae4b02SBaolin Wang 2618aae4b02SBaolin Wang spc->base = devm_platform_ioremap_resource(pdev, 0); 2628aae4b02SBaolin Wang if (IS_ERR(spc->base)) 2638aae4b02SBaolin Wang return PTR_ERR(spc->base); 2648aae4b02SBaolin Wang 2658aae4b02SBaolin Wang spc->dev = &pdev->dev; 2668aae4b02SBaolin Wang platform_set_drvdata(pdev, spc); 2678aae4b02SBaolin Wang 2688aae4b02SBaolin Wang ret = sprd_pwm_clk_init(spc); 2698aae4b02SBaolin Wang if (ret) 2708aae4b02SBaolin Wang return ret; 2718aae4b02SBaolin Wang 2728aae4b02SBaolin Wang spc->chip.dev = &pdev->dev; 2738aae4b02SBaolin Wang spc->chip.ops = &sprd_pwm_ops; 2748aae4b02SBaolin Wang spc->chip.npwm = spc->num_pwms; 2758aae4b02SBaolin Wang 2768aae4b02SBaolin Wang ret = pwmchip_add(&spc->chip); 2778aae4b02SBaolin Wang if (ret) 2788aae4b02SBaolin Wang dev_err(&pdev->dev, "failed to add PWM chip\n"); 2798aae4b02SBaolin Wang 2808aae4b02SBaolin Wang return ret; 2818aae4b02SBaolin Wang } 2828aae4b02SBaolin Wang 2838aae4b02SBaolin Wang static int sprd_pwm_remove(struct platform_device *pdev) 2848aae4b02SBaolin Wang { 2858aae4b02SBaolin Wang struct sprd_pwm_chip *spc = platform_get_drvdata(pdev); 2868aae4b02SBaolin Wang 2878aae4b02SBaolin Wang return pwmchip_remove(&spc->chip); 2888aae4b02SBaolin Wang } 2898aae4b02SBaolin Wang 2908aae4b02SBaolin Wang static const struct of_device_id sprd_pwm_of_match[] = { 2918aae4b02SBaolin Wang { .compatible = "sprd,ums512-pwm", }, 2928aae4b02SBaolin Wang { }, 2938aae4b02SBaolin Wang }; 2948aae4b02SBaolin Wang MODULE_DEVICE_TABLE(of, sprd_pwm_of_match); 2958aae4b02SBaolin Wang 2968aae4b02SBaolin Wang static struct platform_driver sprd_pwm_driver = { 2978aae4b02SBaolin Wang .driver = { 2988aae4b02SBaolin Wang .name = "sprd-pwm", 2998aae4b02SBaolin Wang .of_match_table = sprd_pwm_of_match, 3008aae4b02SBaolin Wang }, 3018aae4b02SBaolin Wang .probe = sprd_pwm_probe, 3028aae4b02SBaolin Wang .remove = sprd_pwm_remove, 3038aae4b02SBaolin Wang }; 3048aae4b02SBaolin Wang 3058aae4b02SBaolin Wang module_platform_driver(sprd_pwm_driver); 3068aae4b02SBaolin Wang 3078aae4b02SBaolin Wang MODULE_DESCRIPTION("Spreadtrum PWM Driver"); 3088aae4b02SBaolin Wang MODULE_LICENSE("GPL v2"); 309