1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * sl28cpld PWM driver 4 * 5 * Copyright (c) 2020 Michael Walle <michael@walle.cc> 6 * 7 * There is no public datasheet available for this PWM core. But it is easy 8 * enough to be briefly explained. It consists of one 8-bit counter. The PWM 9 * supports four distinct frequencies by selecting when to reset the counter. 10 * With the prescaler setting you can select which bit of the counter is used 11 * to reset it. This implies that the higher the frequency the less remaining 12 * bits are available for the actual counter. 13 * 14 * Let cnt[7:0] be the counter, clocked at 32kHz: 15 * +-----------+--------+--------------+-----------+---------------+ 16 * | prescaler | reset | counter bits | frequency | period length | 17 * +-----------+--------+--------------+-----------+---------------+ 18 * | 0 | cnt[7] | cnt[6:0] | 250 Hz | 4000000 ns | 19 * | 1 | cnt[6] | cnt[5:0] | 500 Hz | 2000000 ns | 20 * | 2 | cnt[5] | cnt[4:0] | 1 kHz | 1000000 ns | 21 * | 3 | cnt[4] | cnt[3:0] | 2 kHz | 500000 ns | 22 * +-----------+--------+--------------+-----------+---------------+ 23 * 24 * Limitations: 25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0. 26 * - The hardware cannot atomically set the prescaler and the counter value, 27 * which might lead to glitches and inconsistent states if a write fails. 28 * - The counter is not reset if you switch the prescaler which leads 29 * to glitches, too. 30 * - The duty cycle will switch immediately and not after a complete cycle. 31 * - Depending on the actual implementation, disabling the PWM might have 32 * side effects. For example, if the output pin is shared with a GPIO pin 33 * it will automatically switch back to GPIO mode. 34 */ 35 36 #include <linux/bitfield.h> 37 #include <linux/kernel.h> 38 #include <linux/mod_devicetable.h> 39 #include <linux/module.h> 40 #include <linux/platform_device.h> 41 #include <linux/pwm.h> 42 #include <linux/regmap.h> 43 44 /* 45 * PWM timer block registers. 46 */ 47 #define SL28CPLD_PWM_CTRL 0x00 48 #define SL28CPLD_PWM_CTRL_ENABLE BIT(7) 49 #define SL28CPLD_PWM_CTRL_PRESCALER_MASK GENMASK(1, 0) 50 #define SL28CPLD_PWM_CYCLE 0x01 51 #define SL28CPLD_PWM_CYCLE_MAX GENMASK(6, 0) 52 53 #define SL28CPLD_PWM_CLK 32000 /* 32 kHz */ 54 #define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler) (1 << (7 - (prescaler))) 55 #define SL28CPLD_PWM_PERIOD(prescaler) \ 56 (NSEC_PER_SEC / SL28CPLD_PWM_CLK * SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)) 57 58 /* 59 * We calculate the duty cycle like this: 60 * duty_cycle_ns = pwm_cycle_reg * max_period_ns / max_duty_cycle 61 * 62 * With 63 * max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC 64 * max_duty_cycle = 1 << (7 - prescaler) 65 * this then simplifies to: 66 * duty_cycle_ns = pwm_cycle_reg / SL28CPLD_PWM_CLK * NSEC_PER_SEC 67 * = NSEC_PER_SEC / SL28CPLD_PWM_CLK * pwm_cycle_reg 68 * 69 * NSEC_PER_SEC is a multiple of SL28CPLD_PWM_CLK, therefore we're not losing 70 * precision by doing the divison first. 71 */ 72 #define SL28CPLD_PWM_TO_DUTY_CYCLE(reg) \ 73 (NSEC_PER_SEC / SL28CPLD_PWM_CLK * (reg)) 74 #define SL28CPLD_PWM_FROM_DUTY_CYCLE(duty_cycle) \ 75 (DIV_ROUND_DOWN_ULL((duty_cycle), NSEC_PER_SEC / SL28CPLD_PWM_CLK)) 76 77 #define sl28cpld_pwm_read(priv, reg, val) \ 78 regmap_read((priv)->regmap, (priv)->offset + (reg), (val)) 79 #define sl28cpld_pwm_write(priv, reg, val) \ 80 regmap_write((priv)->regmap, (priv)->offset + (reg), (val)) 81 82 struct sl28cpld_pwm { 83 struct pwm_chip pwm_chip; 84 struct regmap *regmap; 85 u32 offset; 86 }; 87 88 static void sl28cpld_pwm_get_state(struct pwm_chip *chip, 89 struct pwm_device *pwm, 90 struct pwm_state *state) 91 { 92 struct sl28cpld_pwm *priv = dev_get_drvdata(chip->dev); 93 unsigned int reg; 94 int prescaler; 95 96 sl28cpld_pwm_read(priv, SL28CPLD_PWM_CTRL, ®); 97 98 state->enabled = reg & SL28CPLD_PWM_CTRL_ENABLE; 99 100 prescaler = FIELD_GET(SL28CPLD_PWM_CTRL_PRESCALER_MASK, reg); 101 state->period = SL28CPLD_PWM_PERIOD(prescaler); 102 103 sl28cpld_pwm_read(priv, SL28CPLD_PWM_CYCLE, ®); 104 state->duty_cycle = SL28CPLD_PWM_TO_DUTY_CYCLE(reg); 105 state->polarity = PWM_POLARITY_NORMAL; 106 107 /* 108 * Sanitize values for the PWM core. Depending on the prescaler it 109 * might happen that we calculate a duty_cycle greater than the actual 110 * period. This might happen if someone (e.g. the bootloader) sets an 111 * invalid combination of values. The behavior of the hardware is 112 * undefined in this case. But we need to report sane values back to 113 * the PWM core. 114 */ 115 state->duty_cycle = min(state->duty_cycle, state->period); 116 } 117 118 static int sl28cpld_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 119 const struct pwm_state *state) 120 { 121 struct sl28cpld_pwm *priv = dev_get_drvdata(chip->dev); 122 unsigned int cycle, prescaler; 123 bool write_duty_cycle_first; 124 int ret; 125 u8 ctrl; 126 127 /* Polarity inversion is not supported */ 128 if (state->polarity != PWM_POLARITY_NORMAL) 129 return -EINVAL; 130 131 /* 132 * Calculate the prescaler. Pick the biggest period that isn't 133 * bigger than the requested period. 134 */ 135 prescaler = DIV_ROUND_UP_ULL(SL28CPLD_PWM_PERIOD(0), state->period); 136 prescaler = order_base_2(prescaler); 137 138 if (prescaler > field_max(SL28CPLD_PWM_CTRL_PRESCALER_MASK)) 139 return -ERANGE; 140 141 ctrl = FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, prescaler); 142 if (state->enabled) 143 ctrl |= SL28CPLD_PWM_CTRL_ENABLE; 144 145 cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle); 146 cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)); 147 148 /* 149 * Work around the hardware limitation. See also above. Trap 100% duty 150 * cycle if the prescaler is 0. Set prescaler to 1 instead. We don't 151 * care about the frequency because its "all-one" in either case. 152 * 153 * We don't need to check the actual prescaler setting, because only 154 * if the prescaler is 0 we can have this particular value. 155 */ 156 if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) { 157 ctrl &= ~SL28CPLD_PWM_CTRL_PRESCALER_MASK; 158 ctrl |= FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, 1); 159 cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1); 160 } 161 162 /* 163 * To avoid glitches when we switch the prescaler, we have to make sure 164 * we have a valid duty cycle for the new mode. 165 * 166 * Take the current prescaler (or the current period length) into 167 * account to decide whether we have to write the duty cycle or the new 168 * prescaler first. If the period length is decreasing we have to 169 * write the duty cycle first. 170 */ 171 write_duty_cycle_first = pwm->state.period > state->period; 172 173 if (write_duty_cycle_first) { 174 ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle); 175 if (ret) 176 return ret; 177 } 178 179 ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CTRL, ctrl); 180 if (ret) 181 return ret; 182 183 if (!write_duty_cycle_first) { 184 ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle); 185 if (ret) 186 return ret; 187 } 188 189 return 0; 190 } 191 192 static const struct pwm_ops sl28cpld_pwm_ops = { 193 .apply = sl28cpld_pwm_apply, 194 .get_state = sl28cpld_pwm_get_state, 195 .owner = THIS_MODULE, 196 }; 197 198 static int sl28cpld_pwm_probe(struct platform_device *pdev) 199 { 200 struct sl28cpld_pwm *priv; 201 struct pwm_chip *chip; 202 int ret; 203 204 if (!pdev->dev.parent) { 205 dev_err(&pdev->dev, "no parent device\n"); 206 return -ENODEV; 207 } 208 209 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 210 if (!priv) 211 return -ENOMEM; 212 213 priv->regmap = dev_get_regmap(pdev->dev.parent, NULL); 214 if (!priv->regmap) { 215 dev_err(&pdev->dev, "could not get parent regmap\n"); 216 return -ENODEV; 217 } 218 219 ret = device_property_read_u32(&pdev->dev, "reg", &priv->offset); 220 if (ret) { 221 dev_err(&pdev->dev, "no 'reg' property found (%pe)\n", 222 ERR_PTR(ret)); 223 return -EINVAL; 224 } 225 226 /* Initialize the pwm_chip structure */ 227 chip = &priv->pwm_chip; 228 chip->dev = &pdev->dev; 229 chip->ops = &sl28cpld_pwm_ops; 230 chip->base = -1; 231 chip->npwm = 1; 232 233 ret = pwmchip_add(&priv->pwm_chip); 234 if (ret) { 235 dev_err(&pdev->dev, "failed to add PWM chip (%pe)", 236 ERR_PTR(ret)); 237 return ret; 238 } 239 240 platform_set_drvdata(pdev, priv); 241 242 return 0; 243 } 244 245 static int sl28cpld_pwm_remove(struct platform_device *pdev) 246 { 247 struct sl28cpld_pwm *priv = platform_get_drvdata(pdev); 248 249 return pwmchip_remove(&priv->pwm_chip); 250 } 251 252 static const struct of_device_id sl28cpld_pwm_of_match[] = { 253 { .compatible = "kontron,sl28cpld-pwm" }, 254 {} 255 }; 256 MODULE_DEVICE_TABLE(of, sl28cpld_pwm_of_match); 257 258 static struct platform_driver sl28cpld_pwm_driver = { 259 .probe = sl28cpld_pwm_probe, 260 .remove = sl28cpld_pwm_remove, 261 .driver = { 262 .name = "sl28cpld-pwm", 263 .of_match_table = sl28cpld_pwm_of_match, 264 }, 265 }; 266 module_platform_driver(sl28cpld_pwm_driver); 267 268 MODULE_DESCRIPTION("sl28cpld PWM Driver"); 269 MODULE_AUTHOR("Michael Walle <michael@walle.cc>"); 270 MODULE_LICENSE("GPL"); 271