1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2017-2018 SiFive 4 * For SiFive's PWM IP block documentation please refer Chapter 14 of 5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf 6 * 7 * Limitations: 8 * - When changing both duty cycle and period, we cannot prevent in 9 * software that the output might produce a period with mixed 10 * settings (new period length and old duty cycle). 11 * - The hardware cannot generate a 100% duty cycle. 12 * - The hardware generates only inverted output. 13 */ 14 #include <linux/clk.h> 15 #include <linux/io.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/pwm.h> 20 #include <linux/slab.h> 21 #include <linux/bitfield.h> 22 23 /* Register offsets */ 24 #define PWM_SIFIVE_PWMCFG 0x0 25 #define PWM_SIFIVE_PWMCOUNT 0x8 26 #define PWM_SIFIVE_PWMS 0x10 27 #define PWM_SIFIVE_PWMCMP(i) (0x20 + 4 * (i)) 28 29 /* PWMCFG fields */ 30 #define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0) 31 #define PWM_SIFIVE_PWMCFG_STICKY BIT(8) 32 #define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9) 33 #define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10) 34 #define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12) 35 #define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13) 36 #define PWM_SIFIVE_PWMCFG_CENTER BIT(16) 37 #define PWM_SIFIVE_PWMCFG_GANG BIT(24) 38 #define PWM_SIFIVE_PWMCFG_IP BIT(28) 39 40 #define PWM_SIFIVE_CMPWIDTH 16 41 #define PWM_SIFIVE_DEFAULT_PERIOD 10000000 42 43 struct pwm_sifive_ddata { 44 struct pwm_chip chip; 45 struct mutex lock; /* lock to protect user_count and approx_period */ 46 struct notifier_block notifier; 47 struct clk *clk; 48 void __iomem *regs; 49 unsigned int real_period; 50 unsigned int approx_period; 51 int user_count; 52 }; 53 54 static inline 55 struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *chip) 56 { 57 return container_of(chip, struct pwm_sifive_ddata, chip); 58 } 59 60 static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm) 61 { 62 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip); 63 64 mutex_lock(&ddata->lock); 65 ddata->user_count++; 66 mutex_unlock(&ddata->lock); 67 68 return 0; 69 } 70 71 static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm) 72 { 73 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip); 74 75 mutex_lock(&ddata->lock); 76 ddata->user_count--; 77 mutex_unlock(&ddata->lock); 78 } 79 80 /* Called holding ddata->lock */ 81 static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata, 82 unsigned long rate) 83 { 84 unsigned long long num; 85 unsigned long scale_pow; 86 int scale; 87 u32 val; 88 /* 89 * The PWM unit is used with pwmzerocmp=0, so the only way to modify the 90 * period length is using pwmscale which provides the number of bits the 91 * counter is shifted before being feed to the comparators. A period 92 * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks. 93 * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period 94 */ 95 scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC); 96 scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf); 97 98 val = PWM_SIFIVE_PWMCFG_EN_ALWAYS | 99 FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale); 100 writel(val, ddata->regs + PWM_SIFIVE_PWMCFG); 101 102 /* As scale <= 15 the shift operation cannot overflow. */ 103 num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale); 104 ddata->real_period = div64_ul(num, rate); 105 dev_dbg(ddata->chip.dev, 106 "New real_period = %u ns\n", ddata->real_period); 107 } 108 109 static int pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 110 struct pwm_state *state) 111 { 112 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip); 113 u32 duty, val; 114 115 duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm)); 116 117 state->enabled = duty > 0; 118 119 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG); 120 if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS)) 121 state->enabled = false; 122 123 state->period = ddata->real_period; 124 state->duty_cycle = 125 (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH; 126 state->polarity = PWM_POLARITY_INVERSED; 127 128 return 0; 129 } 130 131 static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm, 132 const struct pwm_state *state) 133 { 134 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip); 135 struct pwm_state cur_state; 136 unsigned int duty_cycle; 137 unsigned long long num; 138 bool enabled; 139 int ret = 0; 140 u32 frac; 141 142 if (state->polarity != PWM_POLARITY_INVERSED) 143 return -EINVAL; 144 145 cur_state = pwm->state; 146 enabled = cur_state.enabled; 147 148 duty_cycle = state->duty_cycle; 149 if (!state->enabled) 150 duty_cycle = 0; 151 152 /* 153 * The problem of output producing mixed setting as mentioned at top, 154 * occurs here. To minimize the window for this problem, we are 155 * calculating the register values first and then writing them 156 * consecutively 157 */ 158 num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH); 159 frac = DIV64_U64_ROUND_CLOSEST(num, state->period); 160 /* The hardware cannot generate a 100% duty cycle */ 161 frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1); 162 163 mutex_lock(&ddata->lock); 164 if (state->period != ddata->approx_period) { 165 /* 166 * Don't let a 2nd user change the period underneath the 1st user. 167 * However if ddate->approx_period == 0 this is the first time we set 168 * any period, so let whoever gets here first set the period so other 169 * users who agree on the period won't fail. 170 */ 171 if (ddata->user_count != 1 && ddata->approx_period) { 172 mutex_unlock(&ddata->lock); 173 return -EBUSY; 174 } 175 ddata->approx_period = state->period; 176 pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk)); 177 } 178 mutex_unlock(&ddata->lock); 179 180 /* 181 * If the PWM is enabled the clk is already on. So only enable it 182 * conditionally to have it on exactly once afterwards independent of 183 * the PWM state. 184 */ 185 if (!enabled) { 186 ret = clk_enable(ddata->clk); 187 if (ret) { 188 dev_err(ddata->chip.dev, "Enable clk failed\n"); 189 return ret; 190 } 191 } 192 193 writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm)); 194 195 if (!state->enabled) 196 clk_disable(ddata->clk); 197 198 return 0; 199 } 200 201 static const struct pwm_ops pwm_sifive_ops = { 202 .request = pwm_sifive_request, 203 .free = pwm_sifive_free, 204 .get_state = pwm_sifive_get_state, 205 .apply = pwm_sifive_apply, 206 .owner = THIS_MODULE, 207 }; 208 209 static int pwm_sifive_clock_notifier(struct notifier_block *nb, 210 unsigned long event, void *data) 211 { 212 struct clk_notifier_data *ndata = data; 213 struct pwm_sifive_ddata *ddata = 214 container_of(nb, struct pwm_sifive_ddata, notifier); 215 216 if (event == POST_RATE_CHANGE) { 217 mutex_lock(&ddata->lock); 218 pwm_sifive_update_clock(ddata, ndata->new_rate); 219 mutex_unlock(&ddata->lock); 220 } 221 222 return NOTIFY_OK; 223 } 224 225 static int pwm_sifive_probe(struct platform_device *pdev) 226 { 227 struct device *dev = &pdev->dev; 228 struct pwm_sifive_ddata *ddata; 229 struct pwm_chip *chip; 230 int ret; 231 u32 val; 232 unsigned int enabled_pwms = 0, enabled_clks = 1; 233 234 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); 235 if (!ddata) 236 return -ENOMEM; 237 238 mutex_init(&ddata->lock); 239 chip = &ddata->chip; 240 chip->dev = dev; 241 chip->ops = &pwm_sifive_ops; 242 chip->npwm = 4; 243 244 ddata->regs = devm_platform_ioremap_resource(pdev, 0); 245 if (IS_ERR(ddata->regs)) 246 return PTR_ERR(ddata->regs); 247 248 ddata->clk = devm_clk_get_prepared(dev, NULL); 249 if (IS_ERR(ddata->clk)) 250 return dev_err_probe(dev, PTR_ERR(ddata->clk), 251 "Unable to find controller clock\n"); 252 253 ret = clk_enable(ddata->clk); 254 if (ret) { 255 dev_err(dev, "failed to enable clock for pwm: %d\n", ret); 256 return ret; 257 } 258 259 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG); 260 if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) { 261 unsigned int i; 262 263 for (i = 0; i < chip->npwm; ++i) { 264 val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i)); 265 if (val > 0) 266 ++enabled_pwms; 267 } 268 } 269 270 /* The clk should be on once for each running PWM. */ 271 if (enabled_pwms) { 272 while (enabled_clks < enabled_pwms) { 273 /* This is not expected to fail as the clk is already on */ 274 ret = clk_enable(ddata->clk); 275 if (unlikely(ret)) { 276 dev_err_probe(dev, ret, "Failed to enable clk\n"); 277 goto disable_clk; 278 } 279 ++enabled_clks; 280 } 281 } else { 282 clk_disable(ddata->clk); 283 enabled_clks = 0; 284 } 285 286 /* Watch for changes to underlying clock frequency */ 287 ddata->notifier.notifier_call = pwm_sifive_clock_notifier; 288 ret = clk_notifier_register(ddata->clk, &ddata->notifier); 289 if (ret) { 290 dev_err(dev, "failed to register clock notifier: %d\n", ret); 291 goto disable_clk; 292 } 293 294 ret = pwmchip_add(chip); 295 if (ret < 0) { 296 dev_err(dev, "cannot register PWM: %d\n", ret); 297 goto unregister_clk; 298 } 299 300 platform_set_drvdata(pdev, ddata); 301 dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm); 302 303 return 0; 304 305 unregister_clk: 306 clk_notifier_unregister(ddata->clk, &ddata->notifier); 307 disable_clk: 308 while (enabled_clks) { 309 clk_disable(ddata->clk); 310 --enabled_clks; 311 } 312 313 return ret; 314 } 315 316 static void pwm_sifive_remove(struct platform_device *dev) 317 { 318 struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev); 319 struct pwm_device *pwm; 320 int ch; 321 322 pwmchip_remove(&ddata->chip); 323 clk_notifier_unregister(ddata->clk, &ddata->notifier); 324 325 for (ch = 0; ch < ddata->chip.npwm; ch++) { 326 pwm = &ddata->chip.pwms[ch]; 327 if (pwm->state.enabled) 328 clk_disable(ddata->clk); 329 } 330 } 331 332 static const struct of_device_id pwm_sifive_of_match[] = { 333 { .compatible = "sifive,pwm0" }, 334 {}, 335 }; 336 MODULE_DEVICE_TABLE(of, pwm_sifive_of_match); 337 338 static struct platform_driver pwm_sifive_driver = { 339 .probe = pwm_sifive_probe, 340 .remove_new = pwm_sifive_remove, 341 .driver = { 342 .name = "pwm-sifive", 343 .of_match_table = pwm_sifive_of_match, 344 }, 345 }; 346 module_platform_driver(pwm_sifive_driver); 347 348 MODULE_DESCRIPTION("SiFive PWM driver"); 349 MODULE_LICENSE("GPL v2"); 350