1 /* 2 * Copyright (c) 2007 Ben Dooks 3 * Copyright (c) 2008 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> 5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> 6 * Copyright (c) 2017 Samsung Electronics Co., Ltd. 7 * 8 * PWM driver for Samsung SoCs 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License. 13 */ 14 15 #include <linux/bitops.h> 16 #include <linux/clk.h> 17 #include <linux/export.h> 18 #include <linux/err.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/pwm.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 #include <linux/time.h> 28 29 /* For struct samsung_timer_variant and samsung_pwm_lock. */ 30 #include <clocksource/samsung_pwm.h> 31 32 #define REG_TCFG0 0x00 33 #define REG_TCFG1 0x04 34 #define REG_TCON 0x08 35 36 #define REG_TCNTB(chan) (0x0c + ((chan) * 0xc)) 37 #define REG_TCMPB(chan) (0x10 + ((chan) * 0xc)) 38 39 #define TCFG0_PRESCALER_MASK 0xff 40 #define TCFG0_PRESCALER1_SHIFT 8 41 42 #define TCFG1_MUX_MASK 0xf 43 #define TCFG1_SHIFT(chan) (4 * (chan)) 44 45 /* 46 * Each channel occupies 4 bits in TCON register, but there is a gap of 4 47 * bits (one channel) after channel 0, so channels have different numbering 48 * when accessing TCON register. See to_tcon_channel() function. 49 * 50 * In addition, the location of autoreload bit for channel 4 (TCON channel 5) 51 * in its set of bits is 2 as opposed to 3 for other channels. 52 */ 53 #define TCON_START(chan) BIT(4 * (chan) + 0) 54 #define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1) 55 #define TCON_INVERT(chan) BIT(4 * (chan) + 2) 56 #define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3) 57 #define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2) 58 #define TCON_AUTORELOAD(chan) \ 59 ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan)) 60 61 /** 62 * struct samsung_pwm_channel - private data of PWM channel 63 * @period_ns: current period in nanoseconds programmed to the hardware 64 * @duty_ns: current duty time in nanoseconds programmed to the hardware 65 * @tin_ns: time of one timer tick in nanoseconds with current timer rate 66 */ 67 struct samsung_pwm_channel { 68 u32 period_ns; 69 u32 duty_ns; 70 u32 tin_ns; 71 }; 72 73 /** 74 * struct samsung_pwm_chip - private data of PWM chip 75 * @chip: generic PWM chip 76 * @variant: local copy of hardware variant data 77 * @inverter_mask: inverter status for all channels - one bit per channel 78 * @disabled_mask: disabled status for all channels - one bit per channel 79 * @base: base address of mapped PWM registers 80 * @base_clk: base clock used to drive the timers 81 * @tclk0: external clock 0 (can be ERR_PTR if not present) 82 * @tclk1: external clock 1 (can be ERR_PTR if not present) 83 */ 84 struct samsung_pwm_chip { 85 struct pwm_chip chip; 86 struct samsung_pwm_variant variant; 87 u8 inverter_mask; 88 u8 disabled_mask; 89 90 void __iomem *base; 91 struct clk *base_clk; 92 struct clk *tclk0; 93 struct clk *tclk1; 94 }; 95 96 #ifndef CONFIG_CLKSRC_SAMSUNG_PWM 97 /* 98 * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers 99 * and some registers need access synchronization. If both drivers are 100 * compiled in, the spinlock is defined in the clocksource driver, 101 * otherwise following definition is used. 102 * 103 * Currently we do not need any more complex synchronization method 104 * because all the supported SoCs contain only one instance of the PWM 105 * IP. Should this change, both drivers will need to be modified to 106 * properly synchronize accesses to particular instances. 107 */ 108 static DEFINE_SPINLOCK(samsung_pwm_lock); 109 #endif 110 111 static inline 112 struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip) 113 { 114 return container_of(chip, struct samsung_pwm_chip, chip); 115 } 116 117 static inline unsigned int to_tcon_channel(unsigned int channel) 118 { 119 /* TCON register has a gap of 4 bits (1 channel) after channel 0 */ 120 return (channel == 0) ? 0 : (channel + 1); 121 } 122 123 static void pwm_samsung_set_divisor(struct samsung_pwm_chip *pwm, 124 unsigned int channel, u8 divisor) 125 { 126 u8 shift = TCFG1_SHIFT(channel); 127 unsigned long flags; 128 u32 reg; 129 u8 bits; 130 131 bits = (fls(divisor) - 1) - pwm->variant.div_base; 132 133 spin_lock_irqsave(&samsung_pwm_lock, flags); 134 135 reg = readl(pwm->base + REG_TCFG1); 136 reg &= ~(TCFG1_MUX_MASK << shift); 137 reg |= bits << shift; 138 writel(reg, pwm->base + REG_TCFG1); 139 140 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 141 } 142 143 static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *chip, unsigned int chan) 144 { 145 struct samsung_pwm_variant *variant = &chip->variant; 146 u32 reg; 147 148 reg = readl(chip->base + REG_TCFG1); 149 reg >>= TCFG1_SHIFT(chan); 150 reg &= TCFG1_MUX_MASK; 151 152 return (BIT(reg) & variant->tclk_mask) == 0; 153 } 154 155 static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *chip, 156 unsigned int chan) 157 { 158 unsigned long rate; 159 u32 reg; 160 161 rate = clk_get_rate(chip->base_clk); 162 163 reg = readl(chip->base + REG_TCFG0); 164 if (chan >= 2) 165 reg >>= TCFG0_PRESCALER1_SHIFT; 166 reg &= TCFG0_PRESCALER_MASK; 167 168 return rate / (reg + 1); 169 } 170 171 static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *chip, 172 unsigned int chan, unsigned long freq) 173 { 174 struct samsung_pwm_variant *variant = &chip->variant; 175 unsigned long rate; 176 struct clk *clk; 177 u8 div; 178 179 if (!pwm_samsung_is_tdiv(chip, chan)) { 180 clk = (chan < 2) ? chip->tclk0 : chip->tclk1; 181 if (!IS_ERR(clk)) { 182 rate = clk_get_rate(clk); 183 if (rate) 184 return rate; 185 } 186 187 dev_warn(chip->chip.dev, 188 "tclk of PWM %d is inoperational, using tdiv\n", chan); 189 } 190 191 rate = pwm_samsung_get_tin_rate(chip, chan); 192 dev_dbg(chip->chip.dev, "tin parent at %lu\n", rate); 193 194 /* 195 * Compare minimum PWM frequency that can be achieved with possible 196 * divider settings and choose the lowest divisor that can generate 197 * frequencies lower than requested. 198 */ 199 if (variant->bits < 32) { 200 /* Only for s3c24xx */ 201 for (div = variant->div_base; div < 4; ++div) 202 if ((rate >> (variant->bits + div)) < freq) 203 break; 204 } else { 205 /* 206 * Other variants have enough counter bits to generate any 207 * requested rate, so no need to check higher divisors. 208 */ 209 div = variant->div_base; 210 } 211 212 pwm_samsung_set_divisor(chip, chan, BIT(div)); 213 214 return rate >> div; 215 } 216 217 static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm) 218 { 219 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 220 struct samsung_pwm_channel *our_chan; 221 222 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { 223 dev_warn(chip->dev, 224 "tried to request PWM channel %d without output\n", 225 pwm->hwpwm); 226 return -EINVAL; 227 } 228 229 our_chan = kzalloc(sizeof(*our_chan), GFP_KERNEL); 230 if (!our_chan) 231 return -ENOMEM; 232 233 pwm_set_chip_data(pwm, our_chan); 234 235 return 0; 236 } 237 238 static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm) 239 { 240 kfree(pwm_get_chip_data(pwm)); 241 } 242 243 static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm) 244 { 245 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 246 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); 247 unsigned long flags; 248 u32 tcon; 249 250 spin_lock_irqsave(&samsung_pwm_lock, flags); 251 252 tcon = readl(our_chip->base + REG_TCON); 253 254 tcon &= ~TCON_START(tcon_chan); 255 tcon |= TCON_MANUALUPDATE(tcon_chan); 256 writel(tcon, our_chip->base + REG_TCON); 257 258 tcon &= ~TCON_MANUALUPDATE(tcon_chan); 259 tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan); 260 writel(tcon, our_chip->base + REG_TCON); 261 262 our_chip->disabled_mask &= ~BIT(pwm->hwpwm); 263 264 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 265 266 return 0; 267 } 268 269 static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm) 270 { 271 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 272 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); 273 unsigned long flags; 274 u32 tcon; 275 276 spin_lock_irqsave(&samsung_pwm_lock, flags); 277 278 tcon = readl(our_chip->base + REG_TCON); 279 tcon &= ~TCON_AUTORELOAD(tcon_chan); 280 writel(tcon, our_chip->base + REG_TCON); 281 282 our_chip->disabled_mask |= BIT(pwm->hwpwm); 283 284 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 285 } 286 287 static void pwm_samsung_manual_update(struct samsung_pwm_chip *chip, 288 struct pwm_device *pwm) 289 { 290 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); 291 u32 tcon; 292 unsigned long flags; 293 294 spin_lock_irqsave(&samsung_pwm_lock, flags); 295 296 tcon = readl(chip->base + REG_TCON); 297 tcon |= TCON_MANUALUPDATE(tcon_chan); 298 writel(tcon, chip->base + REG_TCON); 299 300 tcon &= ~TCON_MANUALUPDATE(tcon_chan); 301 writel(tcon, chip->base + REG_TCON); 302 303 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 304 } 305 306 static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm, 307 int duty_ns, int period_ns, bool force_period) 308 { 309 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 310 struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm); 311 u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp; 312 313 /* 314 * We currently avoid using 64bit arithmetic by using the 315 * fact that anything faster than 1Hz is easily representable 316 * by 32bits. 317 */ 318 if (period_ns > NSEC_PER_SEC) 319 return -ERANGE; 320 321 tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm)); 322 oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm)); 323 324 /* We need tick count for calculation, not last tick. */ 325 ++tcnt; 326 327 /* Check to see if we are changing the clock rate of the PWM. */ 328 if (chan->period_ns != period_ns || force_period) { 329 unsigned long tin_rate; 330 u32 period; 331 332 period = NSEC_PER_SEC / period_ns; 333 334 dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n", 335 duty_ns, period_ns, period); 336 337 tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period); 338 339 dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate); 340 341 tin_ns = NSEC_PER_SEC / tin_rate; 342 tcnt = period_ns / tin_ns; 343 } 344 345 /* Period is too short. */ 346 if (tcnt <= 1) 347 return -ERANGE; 348 349 /* Note that counters count down. */ 350 tcmp = duty_ns / tin_ns; 351 352 /* 0% duty is not available */ 353 if (!tcmp) 354 ++tcmp; 355 356 tcmp = tcnt - tcmp; 357 358 /* Decrement to get tick numbers, instead of tick counts. */ 359 --tcnt; 360 /* -1UL will give 100% duty. */ 361 --tcmp; 362 363 dev_dbg(our_chip->chip.dev, 364 "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt); 365 366 /* Update PWM registers. */ 367 writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm)); 368 writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm)); 369 370 /* 371 * In case the PWM is currently at 100% duty cycle, force a manual 372 * update to prevent the signal staying high if the PWM is disabled 373 * shortly afer this update (before it autoreloaded the new values). 374 */ 375 if (oldtcmp == (u32) -1) { 376 dev_dbg(our_chip->chip.dev, "Forcing manual update"); 377 pwm_samsung_manual_update(our_chip, pwm); 378 } 379 380 chan->period_ns = period_ns; 381 chan->tin_ns = tin_ns; 382 chan->duty_ns = duty_ns; 383 384 return 0; 385 } 386 387 static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm, 388 int duty_ns, int period_ns) 389 { 390 return __pwm_samsung_config(chip, pwm, duty_ns, period_ns, false); 391 } 392 393 static void pwm_samsung_set_invert(struct samsung_pwm_chip *chip, 394 unsigned int channel, bool invert) 395 { 396 unsigned int tcon_chan = to_tcon_channel(channel); 397 unsigned long flags; 398 u32 tcon; 399 400 spin_lock_irqsave(&samsung_pwm_lock, flags); 401 402 tcon = readl(chip->base + REG_TCON); 403 404 if (invert) { 405 chip->inverter_mask |= BIT(channel); 406 tcon |= TCON_INVERT(tcon_chan); 407 } else { 408 chip->inverter_mask &= ~BIT(channel); 409 tcon &= ~TCON_INVERT(tcon_chan); 410 } 411 412 writel(tcon, chip->base + REG_TCON); 413 414 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 415 } 416 417 static int pwm_samsung_set_polarity(struct pwm_chip *chip, 418 struct pwm_device *pwm, 419 enum pwm_polarity polarity) 420 { 421 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 422 bool invert = (polarity == PWM_POLARITY_NORMAL); 423 424 /* Inverted means normal in the hardware. */ 425 pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert); 426 427 return 0; 428 } 429 430 static const struct pwm_ops pwm_samsung_ops = { 431 .request = pwm_samsung_request, 432 .free = pwm_samsung_free, 433 .enable = pwm_samsung_enable, 434 .disable = pwm_samsung_disable, 435 .config = pwm_samsung_config, 436 .set_polarity = pwm_samsung_set_polarity, 437 .owner = THIS_MODULE, 438 }; 439 440 #ifdef CONFIG_OF 441 static const struct samsung_pwm_variant s3c24xx_variant = { 442 .bits = 16, 443 .div_base = 1, 444 .has_tint_cstat = false, 445 .tclk_mask = BIT(4), 446 }; 447 448 static const struct samsung_pwm_variant s3c64xx_variant = { 449 .bits = 32, 450 .div_base = 0, 451 .has_tint_cstat = true, 452 .tclk_mask = BIT(7) | BIT(6) | BIT(5), 453 }; 454 455 static const struct samsung_pwm_variant s5p64x0_variant = { 456 .bits = 32, 457 .div_base = 0, 458 .has_tint_cstat = true, 459 .tclk_mask = 0, 460 }; 461 462 static const struct samsung_pwm_variant s5pc100_variant = { 463 .bits = 32, 464 .div_base = 0, 465 .has_tint_cstat = true, 466 .tclk_mask = BIT(5), 467 }; 468 469 static const struct of_device_id samsung_pwm_matches[] = { 470 { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant }, 471 { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant }, 472 { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant }, 473 { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant }, 474 { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant }, 475 {}, 476 }; 477 MODULE_DEVICE_TABLE(of, samsung_pwm_matches); 478 479 static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip) 480 { 481 struct device_node *np = chip->chip.dev->of_node; 482 const struct of_device_id *match; 483 struct property *prop; 484 const __be32 *cur; 485 u32 val; 486 487 match = of_match_node(samsung_pwm_matches, np); 488 if (!match) 489 return -ENODEV; 490 491 memcpy(&chip->variant, match->data, sizeof(chip->variant)); 492 493 of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) { 494 if (val >= SAMSUNG_PWM_NUM) { 495 dev_err(chip->chip.dev, 496 "%s: invalid channel index in samsung,pwm-outputs property\n", 497 __func__); 498 continue; 499 } 500 chip->variant.output_mask |= BIT(val); 501 } 502 503 return 0; 504 } 505 #else 506 static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip) 507 { 508 return -ENODEV; 509 } 510 #endif 511 512 static int pwm_samsung_probe(struct platform_device *pdev) 513 { 514 struct device *dev = &pdev->dev; 515 struct samsung_pwm_chip *chip; 516 struct resource *res; 517 unsigned int chan; 518 int ret; 519 520 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 521 if (chip == NULL) 522 return -ENOMEM; 523 524 chip->chip.dev = &pdev->dev; 525 chip->chip.ops = &pwm_samsung_ops; 526 chip->chip.base = -1; 527 chip->chip.npwm = SAMSUNG_PWM_NUM; 528 chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1; 529 530 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { 531 ret = pwm_samsung_parse_dt(chip); 532 if (ret) 533 return ret; 534 535 chip->chip.of_xlate = of_pwm_xlate_with_flags; 536 chip->chip.of_pwm_n_cells = 3; 537 } else { 538 if (!pdev->dev.platform_data) { 539 dev_err(&pdev->dev, "no platform data specified\n"); 540 return -EINVAL; 541 } 542 543 memcpy(&chip->variant, pdev->dev.platform_data, 544 sizeof(chip->variant)); 545 } 546 547 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 548 chip->base = devm_ioremap_resource(&pdev->dev, res); 549 if (IS_ERR(chip->base)) 550 return PTR_ERR(chip->base); 551 552 chip->base_clk = devm_clk_get(&pdev->dev, "timers"); 553 if (IS_ERR(chip->base_clk)) { 554 dev_err(dev, "failed to get timer base clk\n"); 555 return PTR_ERR(chip->base_clk); 556 } 557 558 ret = clk_prepare_enable(chip->base_clk); 559 if (ret < 0) { 560 dev_err(dev, "failed to enable base clock\n"); 561 return ret; 562 } 563 564 for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan) 565 if (chip->variant.output_mask & BIT(chan)) 566 pwm_samsung_set_invert(chip, chan, true); 567 568 /* Following clocks are optional. */ 569 chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0"); 570 chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1"); 571 572 platform_set_drvdata(pdev, chip); 573 574 ret = pwmchip_add(&chip->chip); 575 if (ret < 0) { 576 dev_err(dev, "failed to register PWM chip\n"); 577 clk_disable_unprepare(chip->base_clk); 578 return ret; 579 } 580 581 dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n", 582 clk_get_rate(chip->base_clk), 583 !IS_ERR(chip->tclk0) ? clk_get_rate(chip->tclk0) : 0, 584 !IS_ERR(chip->tclk1) ? clk_get_rate(chip->tclk1) : 0); 585 586 return 0; 587 } 588 589 static int pwm_samsung_remove(struct platform_device *pdev) 590 { 591 struct samsung_pwm_chip *chip = platform_get_drvdata(pdev); 592 int ret; 593 594 ret = pwmchip_remove(&chip->chip); 595 if (ret < 0) 596 return ret; 597 598 clk_disable_unprepare(chip->base_clk); 599 600 return 0; 601 } 602 603 #ifdef CONFIG_PM_SLEEP 604 static int pwm_samsung_resume(struct device *dev) 605 { 606 struct samsung_pwm_chip *our_chip = dev_get_drvdata(dev); 607 struct pwm_chip *chip = &our_chip->chip; 608 unsigned int i; 609 610 for (i = 0; i < SAMSUNG_PWM_NUM; i++) { 611 struct pwm_device *pwm = &chip->pwms[i]; 612 struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm); 613 614 if (!chan) 615 continue; 616 617 if (our_chip->variant.output_mask & BIT(i)) 618 pwm_samsung_set_invert(our_chip, i, 619 our_chip->inverter_mask & BIT(i)); 620 621 if (chan->period_ns) { 622 __pwm_samsung_config(chip, pwm, chan->duty_ns, 623 chan->period_ns, true); 624 /* needed to make PWM disable work on Odroid-XU3 */ 625 pwm_samsung_manual_update(our_chip, pwm); 626 } 627 628 if (our_chip->disabled_mask & BIT(i)) 629 pwm_samsung_disable(chip, pwm); 630 else 631 pwm_samsung_enable(chip, pwm); 632 } 633 634 return 0; 635 } 636 #endif 637 638 static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, NULL, pwm_samsung_resume); 639 640 static struct platform_driver pwm_samsung_driver = { 641 .driver = { 642 .name = "samsung-pwm", 643 .pm = &pwm_samsung_pm_ops, 644 .of_match_table = of_match_ptr(samsung_pwm_matches), 645 }, 646 .probe = pwm_samsung_probe, 647 .remove = pwm_samsung_remove, 648 }; 649 module_platform_driver(pwm_samsung_driver); 650 651 MODULE_LICENSE("GPL"); 652 MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>"); 653 MODULE_ALIAS("platform:samsung-pwm"); 654