1*254d3a72SBiju Das // SPDX-License-Identifier: GPL-2.0 2*254d3a72SBiju Das /* 3*254d3a72SBiju Das * Renesas RZ/G2L MTU3a PWM Timer driver 4*254d3a72SBiju Das * 5*254d3a72SBiju Das * Copyright (C) 2023 Renesas Electronics Corporation 6*254d3a72SBiju Das * 7*254d3a72SBiju Das * Hardware manual for this IP can be found here 8*254d3a72SBiju Das * https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?language=en 9*254d3a72SBiju Das * 10*254d3a72SBiju Das * Limitations: 11*254d3a72SBiju Das * - When PWM is disabled, the output is driven to Hi-Z. 12*254d3a72SBiju Das * - While the hardware supports both polarities, the driver (for now) 13*254d3a72SBiju Das * only handles normal polarity. 14*254d3a72SBiju Das * - HW uses one counter and two match components to configure duty_cycle 15*254d3a72SBiju Das * and period. 16*254d3a72SBiju Das * - Multi-Function Timer Pulse Unit (a.k.a MTU) has 7 HW channels for PWM 17*254d3a72SBiju Das * operations. (The channels are MTU{0..4, 6, 7}.) 18*254d3a72SBiju Das * - MTU{1, 2} channels have a single IO, whereas all other HW channels have 19*254d3a72SBiju Das * 2 IOs. 20*254d3a72SBiju Das * - Each IO is modelled as an independent PWM channel. 21*254d3a72SBiju Das * - rz_mtu3_channel_io_map table is used to map the PWM channel to the 22*254d3a72SBiju Das * corresponding HW channel as there are difference in number of IOs 23*254d3a72SBiju Das * between HW channels. 24*254d3a72SBiju Das */ 25*254d3a72SBiju Das 26*254d3a72SBiju Das #include <linux/bitfield.h> 27*254d3a72SBiju Das #include <linux/clk.h> 28*254d3a72SBiju Das #include <linux/limits.h> 29*254d3a72SBiju Das #include <linux/mfd/rz-mtu3.h> 30*254d3a72SBiju Das #include <linux/module.h> 31*254d3a72SBiju Das #include <linux/platform_device.h> 32*254d3a72SBiju Das #include <linux/pm_runtime.h> 33*254d3a72SBiju Das #include <linux/pwm.h> 34*254d3a72SBiju Das #include <linux/time.h> 35*254d3a72SBiju Das 36*254d3a72SBiju Das #define RZ_MTU3_MAX_PWM_CHANNELS 12 37*254d3a72SBiju Das #define RZ_MTU3_MAX_HW_CHANNELS 7 38*254d3a72SBiju Das 39*254d3a72SBiju Das /** 40*254d3a72SBiju Das * struct rz_mtu3_channel_io_map - MTU3 pwm channel map 41*254d3a72SBiju Das * 42*254d3a72SBiju Das * @base_pwm_number: First PWM of a channel 43*254d3a72SBiju Das * @num: number of IOs on the HW channel. 44*254d3a72SBiju Das */ 45*254d3a72SBiju Das struct rz_mtu3_channel_io_map { 46*254d3a72SBiju Das u8 base_pwm_number; 47*254d3a72SBiju Das u8 num_channel_ios; 48*254d3a72SBiju Das }; 49*254d3a72SBiju Das 50*254d3a72SBiju Das /** 51*254d3a72SBiju Das * struct rz_mtu3_pwm_channel - MTU3 pwm channel data 52*254d3a72SBiju Das * 53*254d3a72SBiju Das * @mtu: MTU3 channel data 54*254d3a72SBiju Das * @map: MTU3 pwm channel map 55*254d3a72SBiju Das */ 56*254d3a72SBiju Das struct rz_mtu3_pwm_channel { 57*254d3a72SBiju Das struct rz_mtu3_channel *mtu; 58*254d3a72SBiju Das const struct rz_mtu3_channel_io_map *map; 59*254d3a72SBiju Das }; 60*254d3a72SBiju Das 61*254d3a72SBiju Das /** 62*254d3a72SBiju Das * struct rz_mtu3_pwm_chip - MTU3 pwm private data 63*254d3a72SBiju Das * 64*254d3a72SBiju Das * @chip: MTU3 pwm chip data 65*254d3a72SBiju Das * @clk: MTU3 module clock 66*254d3a72SBiju Das * @lock: Lock to prevent concurrent access for usage count 67*254d3a72SBiju Das * @rate: MTU3 clock rate 68*254d3a72SBiju Das * @user_count: MTU3 usage count 69*254d3a72SBiju Das * @enable_count: MTU3 enable count 70*254d3a72SBiju Das * @prescale: MTU3 prescale 71*254d3a72SBiju Das * @channel_data: MTU3 pwm channel data 72*254d3a72SBiju Das */ 73*254d3a72SBiju Das 74*254d3a72SBiju Das struct rz_mtu3_pwm_chip { 75*254d3a72SBiju Das struct pwm_chip chip; 76*254d3a72SBiju Das struct clk *clk; 77*254d3a72SBiju Das struct mutex lock; 78*254d3a72SBiju Das unsigned long rate; 79*254d3a72SBiju Das u32 user_count[RZ_MTU3_MAX_HW_CHANNELS]; 80*254d3a72SBiju Das u32 enable_count[RZ_MTU3_MAX_HW_CHANNELS]; 81*254d3a72SBiju Das u8 prescale[RZ_MTU3_MAX_HW_CHANNELS]; 82*254d3a72SBiju Das struct rz_mtu3_pwm_channel channel_data[RZ_MTU3_MAX_HW_CHANNELS]; 83*254d3a72SBiju Das }; 84*254d3a72SBiju Das 85*254d3a72SBiju Das /* 86*254d3a72SBiju Das * The MTU channels are {0..4, 6, 7} and the number of IO on MTU1 87*254d3a72SBiju Das * and MTU2 channel is 1 compared to 2 on others. 88*254d3a72SBiju Das */ 89*254d3a72SBiju Das static const struct rz_mtu3_channel_io_map channel_map[] = { 90*254d3a72SBiju Das { 0, 2 }, { 2, 1 }, { 3, 1 }, { 4, 2 }, { 6, 2 }, { 8, 2 }, { 10, 2 } 91*254d3a72SBiju Das }; 92*254d3a72SBiju Das 93*254d3a72SBiju Das static inline struct rz_mtu3_pwm_chip *to_rz_mtu3_pwm_chip(struct pwm_chip *chip) 94*254d3a72SBiju Das { 95*254d3a72SBiju Das return container_of(chip, struct rz_mtu3_pwm_chip, chip); 96*254d3a72SBiju Das } 97*254d3a72SBiju Das 98*254d3a72SBiju Das static void rz_mtu3_pwm_read_tgr_registers(struct rz_mtu3_pwm_channel *priv, 99*254d3a72SBiju Das u16 reg_pv_offset, u16 *pv_val, 100*254d3a72SBiju Das u16 reg_dc_offset, u16 *dc_val) 101*254d3a72SBiju Das { 102*254d3a72SBiju Das *pv_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_pv_offset); 103*254d3a72SBiju Das *dc_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_dc_offset); 104*254d3a72SBiju Das } 105*254d3a72SBiju Das 106*254d3a72SBiju Das static void rz_mtu3_pwm_write_tgr_registers(struct rz_mtu3_pwm_channel *priv, 107*254d3a72SBiju Das u16 reg_pv_offset, u16 pv_val, 108*254d3a72SBiju Das u16 reg_dc_offset, u16 dc_val) 109*254d3a72SBiju Das { 110*254d3a72SBiju Das rz_mtu3_16bit_ch_write(priv->mtu, reg_pv_offset, pv_val); 111*254d3a72SBiju Das rz_mtu3_16bit_ch_write(priv->mtu, reg_dc_offset, dc_val); 112*254d3a72SBiju Das } 113*254d3a72SBiju Das 114*254d3a72SBiju Das static u8 rz_mtu3_pwm_calculate_prescale(struct rz_mtu3_pwm_chip *rz_mtu3, 115*254d3a72SBiju Das u64 period_cycles) 116*254d3a72SBiju Das { 117*254d3a72SBiju Das u32 prescaled_period_cycles; 118*254d3a72SBiju Das u8 prescale; 119*254d3a72SBiju Das 120*254d3a72SBiju Das /* 121*254d3a72SBiju Das * Supported prescale values are 1, 4, 16 and 64. 122*254d3a72SBiju Das * TODO: Support prescale values 2, 8, 32, 256 and 1024. 123*254d3a72SBiju Das */ 124*254d3a72SBiju Das prescaled_period_cycles = period_cycles >> 16; 125*254d3a72SBiju Das if (prescaled_period_cycles >= 16) 126*254d3a72SBiju Das prescale = 3; 127*254d3a72SBiju Das else 128*254d3a72SBiju Das prescale = (fls(prescaled_period_cycles) + 1) / 2; 129*254d3a72SBiju Das 130*254d3a72SBiju Das return prescale; 131*254d3a72SBiju Das } 132*254d3a72SBiju Das 133*254d3a72SBiju Das static struct rz_mtu3_pwm_channel * 134*254d3a72SBiju Das rz_mtu3_get_channel(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm) 135*254d3a72SBiju Das { 136*254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv = rz_mtu3_pwm->channel_data; 137*254d3a72SBiju Das unsigned int ch; 138*254d3a72SBiju Das 139*254d3a72SBiju Das for (ch = 0; ch < RZ_MTU3_MAX_HW_CHANNELS; ch++, priv++) { 140*254d3a72SBiju Das if (priv->map->base_pwm_number + priv->map->num_channel_ios > hwpwm) 141*254d3a72SBiju Das break; 142*254d3a72SBiju Das } 143*254d3a72SBiju Das 144*254d3a72SBiju Das return priv; 145*254d3a72SBiju Das } 146*254d3a72SBiju Das 147*254d3a72SBiju Das static bool rz_mtu3_pwm_is_ch_enabled(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, 148*254d3a72SBiju Das u32 hwpwm) 149*254d3a72SBiju Das { 150*254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv; 151*254d3a72SBiju Das bool is_channel_en; 152*254d3a72SBiju Das u8 val; 153*254d3a72SBiju Das 154*254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, hwpwm); 155*254d3a72SBiju Das is_channel_en = rz_mtu3_is_enabled(priv->mtu); 156*254d3a72SBiju Das if (!is_channel_en) 157*254d3a72SBiju Das return false; 158*254d3a72SBiju Das 159*254d3a72SBiju Das if (priv->map->base_pwm_number == hwpwm) 160*254d3a72SBiju Das val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORH); 161*254d3a72SBiju Das else 162*254d3a72SBiju Das val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORL); 163*254d3a72SBiju Das 164*254d3a72SBiju Das return val & RZ_MTU3_TIOR_IOA; 165*254d3a72SBiju Das } 166*254d3a72SBiju Das 167*254d3a72SBiju Das static int rz_mtu3_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 168*254d3a72SBiju Das { 169*254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); 170*254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv; 171*254d3a72SBiju Das bool is_mtu3_channel_available; 172*254d3a72SBiju Das u32 ch; 173*254d3a72SBiju Das 174*254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 175*254d3a72SBiju Das ch = priv - rz_mtu3_pwm->channel_data; 176*254d3a72SBiju Das 177*254d3a72SBiju Das mutex_lock(&rz_mtu3_pwm->lock); 178*254d3a72SBiju Das /* 179*254d3a72SBiju Das * Each channel must be requested only once, so if the channel 180*254d3a72SBiju Das * serves two PWMs and the other is already requested, skip over 181*254d3a72SBiju Das * rz_mtu3_request_channel() 182*254d3a72SBiju Das */ 183*254d3a72SBiju Das if (!rz_mtu3_pwm->user_count[ch]) { 184*254d3a72SBiju Das is_mtu3_channel_available = rz_mtu3_request_channel(priv->mtu); 185*254d3a72SBiju Das if (!is_mtu3_channel_available) { 186*254d3a72SBiju Das mutex_unlock(&rz_mtu3_pwm->lock); 187*254d3a72SBiju Das return -EBUSY; 188*254d3a72SBiju Das } 189*254d3a72SBiju Das } 190*254d3a72SBiju Das 191*254d3a72SBiju Das rz_mtu3_pwm->user_count[ch]++; 192*254d3a72SBiju Das mutex_unlock(&rz_mtu3_pwm->lock); 193*254d3a72SBiju Das 194*254d3a72SBiju Das return 0; 195*254d3a72SBiju Das } 196*254d3a72SBiju Das 197*254d3a72SBiju Das static void rz_mtu3_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 198*254d3a72SBiju Das { 199*254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); 200*254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv; 201*254d3a72SBiju Das u32 ch; 202*254d3a72SBiju Das 203*254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 204*254d3a72SBiju Das ch = priv - rz_mtu3_pwm->channel_data; 205*254d3a72SBiju Das 206*254d3a72SBiju Das mutex_lock(&rz_mtu3_pwm->lock); 207*254d3a72SBiju Das rz_mtu3_pwm->user_count[ch]--; 208*254d3a72SBiju Das if (!rz_mtu3_pwm->user_count[ch]) 209*254d3a72SBiju Das rz_mtu3_release_channel(priv->mtu); 210*254d3a72SBiju Das 211*254d3a72SBiju Das mutex_unlock(&rz_mtu3_pwm->lock); 212*254d3a72SBiju Das } 213*254d3a72SBiju Das 214*254d3a72SBiju Das static int rz_mtu3_pwm_enable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, 215*254d3a72SBiju Das struct pwm_device *pwm) 216*254d3a72SBiju Das { 217*254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv; 218*254d3a72SBiju Das u32 ch; 219*254d3a72SBiju Das u8 val; 220*254d3a72SBiju Das int rc; 221*254d3a72SBiju Das 222*254d3a72SBiju Das rc = pm_runtime_resume_and_get(rz_mtu3_pwm->chip.dev); 223*254d3a72SBiju Das if (rc) 224*254d3a72SBiju Das return rc; 225*254d3a72SBiju Das 226*254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 227*254d3a72SBiju Das ch = priv - rz_mtu3_pwm->channel_data; 228*254d3a72SBiju Das val = RZ_MTU3_TIOR_OC_IOB_TOGGLE | RZ_MTU3_TIOR_OC_IOA_H_COMP_MATCH; 229*254d3a72SBiju Das 230*254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_MD_PWMMODE1); 231*254d3a72SBiju Das if (priv->map->base_pwm_number == pwm->hwpwm) 232*254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, val); 233*254d3a72SBiju Das else 234*254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, val); 235*254d3a72SBiju Das 236*254d3a72SBiju Das mutex_lock(&rz_mtu3_pwm->lock); 237*254d3a72SBiju Das if (!rz_mtu3_pwm->enable_count[ch]) 238*254d3a72SBiju Das rz_mtu3_enable(priv->mtu); 239*254d3a72SBiju Das 240*254d3a72SBiju Das rz_mtu3_pwm->enable_count[ch]++; 241*254d3a72SBiju Das mutex_unlock(&rz_mtu3_pwm->lock); 242*254d3a72SBiju Das 243*254d3a72SBiju Das return 0; 244*254d3a72SBiju Das } 245*254d3a72SBiju Das 246*254d3a72SBiju Das static void rz_mtu3_pwm_disable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, 247*254d3a72SBiju Das struct pwm_device *pwm) 248*254d3a72SBiju Das { 249*254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv; 250*254d3a72SBiju Das u32 ch; 251*254d3a72SBiju Das 252*254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 253*254d3a72SBiju Das ch = priv - rz_mtu3_pwm->channel_data; 254*254d3a72SBiju Das 255*254d3a72SBiju Das /* Disable output pins of MTU3 channel */ 256*254d3a72SBiju Das if (priv->map->base_pwm_number == pwm->hwpwm) 257*254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, RZ_MTU3_TIOR_OC_RETAIN); 258*254d3a72SBiju Das else 259*254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, RZ_MTU3_TIOR_OC_RETAIN); 260*254d3a72SBiju Das 261*254d3a72SBiju Das mutex_lock(&rz_mtu3_pwm->lock); 262*254d3a72SBiju Das rz_mtu3_pwm->enable_count[ch]--; 263*254d3a72SBiju Das if (!rz_mtu3_pwm->enable_count[ch]) 264*254d3a72SBiju Das rz_mtu3_disable(priv->mtu); 265*254d3a72SBiju Das 266*254d3a72SBiju Das mutex_unlock(&rz_mtu3_pwm->lock); 267*254d3a72SBiju Das 268*254d3a72SBiju Das pm_runtime_put_sync(rz_mtu3_pwm->chip.dev); 269*254d3a72SBiju Das } 270*254d3a72SBiju Das 271*254d3a72SBiju Das static int rz_mtu3_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 272*254d3a72SBiju Das struct pwm_state *state) 273*254d3a72SBiju Das { 274*254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); 275*254d3a72SBiju Das int rc; 276*254d3a72SBiju Das 277*254d3a72SBiju Das rc = pm_runtime_resume_and_get(chip->dev); 278*254d3a72SBiju Das if (rc) 279*254d3a72SBiju Das return rc; 280*254d3a72SBiju Das 281*254d3a72SBiju Das state->enabled = rz_mtu3_pwm_is_ch_enabled(rz_mtu3_pwm, pwm->hwpwm); 282*254d3a72SBiju Das if (state->enabled) { 283*254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv; 284*254d3a72SBiju Das u8 prescale, val; 285*254d3a72SBiju Das u16 dc, pv; 286*254d3a72SBiju Das u64 tmp; 287*254d3a72SBiju Das 288*254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 289*254d3a72SBiju Das if (priv->map->base_pwm_number == pwm->hwpwm) 290*254d3a72SBiju Das rz_mtu3_pwm_read_tgr_registers(priv, RZ_MTU3_TGRA, &pv, 291*254d3a72SBiju Das RZ_MTU3_TGRB, &dc); 292*254d3a72SBiju Das else 293*254d3a72SBiju Das rz_mtu3_pwm_read_tgr_registers(priv, RZ_MTU3_TGRC, &pv, 294*254d3a72SBiju Das RZ_MTU3_TGRD, &dc); 295*254d3a72SBiju Das 296*254d3a72SBiju Das val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TCR); 297*254d3a72SBiju Das prescale = FIELD_GET(RZ_MTU3_TCR_TPCS, val); 298*254d3a72SBiju Das 299*254d3a72SBiju Das /* With prescale <= 7 and pv <= 0xffff this doesn't overflow. */ 300*254d3a72SBiju Das tmp = NSEC_PER_SEC * (u64)pv << (2 * prescale); 301*254d3a72SBiju Das state->period = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate); 302*254d3a72SBiju Das tmp = NSEC_PER_SEC * (u64)dc << (2 * prescale); 303*254d3a72SBiju Das state->duty_cycle = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate); 304*254d3a72SBiju Das 305*254d3a72SBiju Das if (state->duty_cycle > state->period) 306*254d3a72SBiju Das state->duty_cycle = state->period; 307*254d3a72SBiju Das } 308*254d3a72SBiju Das 309*254d3a72SBiju Das state->polarity = PWM_POLARITY_NORMAL; 310*254d3a72SBiju Das pm_runtime_put(chip->dev); 311*254d3a72SBiju Das 312*254d3a72SBiju Das return 0; 313*254d3a72SBiju Das } 314*254d3a72SBiju Das 315*254d3a72SBiju Das static u16 rz_mtu3_pwm_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale) 316*254d3a72SBiju Das { 317*254d3a72SBiju Das return min(period_or_duty_cycle >> (2 * prescale), (u64)U16_MAX); 318*254d3a72SBiju Das } 319*254d3a72SBiju Das 320*254d3a72SBiju Das static int rz_mtu3_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 321*254d3a72SBiju Das const struct pwm_state *state) 322*254d3a72SBiju Das { 323*254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); 324*254d3a72SBiju Das struct rz_mtu3_pwm_channel *priv; 325*254d3a72SBiju Das u64 period_cycles; 326*254d3a72SBiju Das u64 duty_cycles; 327*254d3a72SBiju Das u8 prescale; 328*254d3a72SBiju Das u16 pv, dc; 329*254d3a72SBiju Das u8 val; 330*254d3a72SBiju Das u32 ch; 331*254d3a72SBiju Das 332*254d3a72SBiju Das priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 333*254d3a72SBiju Das ch = priv - rz_mtu3_pwm->channel_data; 334*254d3a72SBiju Das 335*254d3a72SBiju Das period_cycles = mul_u64_u32_div(state->period, rz_mtu3_pwm->rate, 336*254d3a72SBiju Das NSEC_PER_SEC); 337*254d3a72SBiju Das prescale = rz_mtu3_pwm_calculate_prescale(rz_mtu3_pwm, period_cycles); 338*254d3a72SBiju Das 339*254d3a72SBiju Das /* 340*254d3a72SBiju Das * Prescalar is shared by multiple channels, so prescale can 341*254d3a72SBiju Das * NOT be modified when there are multiple channels in use with 342*254d3a72SBiju Das * different settings. Modify prescalar if other PWM is off or handle 343*254d3a72SBiju Das * it, if current prescale value is less than the one we want to set. 344*254d3a72SBiju Das */ 345*254d3a72SBiju Das if (rz_mtu3_pwm->enable_count[ch] > 1) { 346*254d3a72SBiju Das if (rz_mtu3_pwm->prescale[ch] > prescale) 347*254d3a72SBiju Das return -EBUSY; 348*254d3a72SBiju Das 349*254d3a72SBiju Das prescale = rz_mtu3_pwm->prescale[ch]; 350*254d3a72SBiju Das } 351*254d3a72SBiju Das 352*254d3a72SBiju Das pv = rz_mtu3_pwm_calculate_pv_or_dc(period_cycles, prescale); 353*254d3a72SBiju Das 354*254d3a72SBiju Das duty_cycles = mul_u64_u32_div(state->duty_cycle, rz_mtu3_pwm->rate, 355*254d3a72SBiju Das NSEC_PER_SEC); 356*254d3a72SBiju Das dc = rz_mtu3_pwm_calculate_pv_or_dc(duty_cycles, prescale); 357*254d3a72SBiju Das 358*254d3a72SBiju Das /* 359*254d3a72SBiju Das * If the PWM channel is disabled, make sure to turn on the clock 360*254d3a72SBiju Das * before writing the register. 361*254d3a72SBiju Das */ 362*254d3a72SBiju Das if (!pwm->state.enabled) { 363*254d3a72SBiju Das int rc; 364*254d3a72SBiju Das 365*254d3a72SBiju Das rc = pm_runtime_resume_and_get(chip->dev); 366*254d3a72SBiju Das if (rc) 367*254d3a72SBiju Das return rc; 368*254d3a72SBiju Das } 369*254d3a72SBiju Das 370*254d3a72SBiju Das val = RZ_MTU3_TCR_CKEG_RISING | prescale; 371*254d3a72SBiju Das 372*254d3a72SBiju Das /* Counter must be stopped while updating TCR register */ 373*254d3a72SBiju Das if (rz_mtu3_pwm->prescale[ch] != prescale && rz_mtu3_pwm->enable_count[ch]) 374*254d3a72SBiju Das rz_mtu3_disable(priv->mtu); 375*254d3a72SBiju Das 376*254d3a72SBiju Das if (priv->map->base_pwm_number == pwm->hwpwm) { 377*254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR, 378*254d3a72SBiju Das RZ_MTU3_TCR_CCLR_TGRA | val); 379*254d3a72SBiju Das rz_mtu3_pwm_write_tgr_registers(priv, RZ_MTU3_TGRA, pv, 380*254d3a72SBiju Das RZ_MTU3_TGRB, dc); 381*254d3a72SBiju Das } else { 382*254d3a72SBiju Das rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR, 383*254d3a72SBiju Das RZ_MTU3_TCR_CCLR_TGRC | val); 384*254d3a72SBiju Das rz_mtu3_pwm_write_tgr_registers(priv, RZ_MTU3_TGRC, pv, 385*254d3a72SBiju Das RZ_MTU3_TGRD, dc); 386*254d3a72SBiju Das } 387*254d3a72SBiju Das 388*254d3a72SBiju Das if (rz_mtu3_pwm->prescale[ch] != prescale) { 389*254d3a72SBiju Das /* 390*254d3a72SBiju Das * Prescalar is shared by multiple channels, we cache the 391*254d3a72SBiju Das * prescalar value from first enabled channel and use the same 392*254d3a72SBiju Das * value for both channels. 393*254d3a72SBiju Das */ 394*254d3a72SBiju Das rz_mtu3_pwm->prescale[ch] = prescale; 395*254d3a72SBiju Das 396*254d3a72SBiju Das if (rz_mtu3_pwm->enable_count[ch]) 397*254d3a72SBiju Das rz_mtu3_enable(priv->mtu); 398*254d3a72SBiju Das } 399*254d3a72SBiju Das 400*254d3a72SBiju Das /* If the PWM is not enabled, turn the clock off again to save power. */ 401*254d3a72SBiju Das if (!pwm->state.enabled) 402*254d3a72SBiju Das pm_runtime_put(chip->dev); 403*254d3a72SBiju Das 404*254d3a72SBiju Das return 0; 405*254d3a72SBiju Das } 406*254d3a72SBiju Das 407*254d3a72SBiju Das static int rz_mtu3_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 408*254d3a72SBiju Das const struct pwm_state *state) 409*254d3a72SBiju Das { 410*254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); 411*254d3a72SBiju Das bool enabled = pwm->state.enabled; 412*254d3a72SBiju Das int ret; 413*254d3a72SBiju Das 414*254d3a72SBiju Das if (state->polarity != PWM_POLARITY_NORMAL) 415*254d3a72SBiju Das return -EINVAL; 416*254d3a72SBiju Das 417*254d3a72SBiju Das if (!state->enabled) { 418*254d3a72SBiju Das if (enabled) 419*254d3a72SBiju Das rz_mtu3_pwm_disable(rz_mtu3_pwm, pwm); 420*254d3a72SBiju Das 421*254d3a72SBiju Das return 0; 422*254d3a72SBiju Das } 423*254d3a72SBiju Das 424*254d3a72SBiju Das mutex_lock(&rz_mtu3_pwm->lock); 425*254d3a72SBiju Das ret = rz_mtu3_pwm_config(chip, pwm, state); 426*254d3a72SBiju Das mutex_unlock(&rz_mtu3_pwm->lock); 427*254d3a72SBiju Das if (ret) 428*254d3a72SBiju Das return ret; 429*254d3a72SBiju Das 430*254d3a72SBiju Das if (!enabled) 431*254d3a72SBiju Das ret = rz_mtu3_pwm_enable(rz_mtu3_pwm, pwm); 432*254d3a72SBiju Das 433*254d3a72SBiju Das return ret; 434*254d3a72SBiju Das } 435*254d3a72SBiju Das 436*254d3a72SBiju Das static const struct pwm_ops rz_mtu3_pwm_ops = { 437*254d3a72SBiju Das .request = rz_mtu3_pwm_request, 438*254d3a72SBiju Das .free = rz_mtu3_pwm_free, 439*254d3a72SBiju Das .get_state = rz_mtu3_pwm_get_state, 440*254d3a72SBiju Das .apply = rz_mtu3_pwm_apply, 441*254d3a72SBiju Das .owner = THIS_MODULE, 442*254d3a72SBiju Das }; 443*254d3a72SBiju Das 444*254d3a72SBiju Das static int rz_mtu3_pwm_pm_runtime_suspend(struct device *dev) 445*254d3a72SBiju Das { 446*254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = dev_get_drvdata(dev); 447*254d3a72SBiju Das 448*254d3a72SBiju Das clk_disable_unprepare(rz_mtu3_pwm->clk); 449*254d3a72SBiju Das 450*254d3a72SBiju Das return 0; 451*254d3a72SBiju Das } 452*254d3a72SBiju Das 453*254d3a72SBiju Das static int rz_mtu3_pwm_pm_runtime_resume(struct device *dev) 454*254d3a72SBiju Das { 455*254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = dev_get_drvdata(dev); 456*254d3a72SBiju Das 457*254d3a72SBiju Das return clk_prepare_enable(rz_mtu3_pwm->clk); 458*254d3a72SBiju Das } 459*254d3a72SBiju Das 460*254d3a72SBiju Das static DEFINE_RUNTIME_DEV_PM_OPS(rz_mtu3_pwm_pm_ops, 461*254d3a72SBiju Das rz_mtu3_pwm_pm_runtime_suspend, 462*254d3a72SBiju Das rz_mtu3_pwm_pm_runtime_resume, NULL); 463*254d3a72SBiju Das 464*254d3a72SBiju Das static void rz_mtu3_pwm_pm_disable(void *data) 465*254d3a72SBiju Das { 466*254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm = data; 467*254d3a72SBiju Das 468*254d3a72SBiju Das clk_rate_exclusive_put(rz_mtu3_pwm->clk); 469*254d3a72SBiju Das pm_runtime_disable(rz_mtu3_pwm->chip.dev); 470*254d3a72SBiju Das pm_runtime_set_suspended(rz_mtu3_pwm->chip.dev); 471*254d3a72SBiju Das } 472*254d3a72SBiju Das 473*254d3a72SBiju Das static int rz_mtu3_pwm_probe(struct platform_device *pdev) 474*254d3a72SBiju Das { 475*254d3a72SBiju Das struct rz_mtu3 *parent_ddata = dev_get_drvdata(pdev->dev.parent); 476*254d3a72SBiju Das struct rz_mtu3_pwm_chip *rz_mtu3_pwm; 477*254d3a72SBiju Das struct device *dev = &pdev->dev; 478*254d3a72SBiju Das unsigned int i, j = 0; 479*254d3a72SBiju Das int ret; 480*254d3a72SBiju Das 481*254d3a72SBiju Das rz_mtu3_pwm = devm_kzalloc(&pdev->dev, sizeof(*rz_mtu3_pwm), GFP_KERNEL); 482*254d3a72SBiju Das if (!rz_mtu3_pwm) 483*254d3a72SBiju Das return -ENOMEM; 484*254d3a72SBiju Das 485*254d3a72SBiju Das rz_mtu3_pwm->clk = parent_ddata->clk; 486*254d3a72SBiju Das 487*254d3a72SBiju Das for (i = 0; i < RZ_MTU_NUM_CHANNELS; i++) { 488*254d3a72SBiju Das if (i == RZ_MTU3_CHAN_5 || i == RZ_MTU3_CHAN_8) 489*254d3a72SBiju Das continue; 490*254d3a72SBiju Das 491*254d3a72SBiju Das rz_mtu3_pwm->channel_data[j].mtu = &parent_ddata->channels[i]; 492*254d3a72SBiju Das rz_mtu3_pwm->channel_data[j].mtu->dev = dev; 493*254d3a72SBiju Das rz_mtu3_pwm->channel_data[j].map = &channel_map[j]; 494*254d3a72SBiju Das j++; 495*254d3a72SBiju Das } 496*254d3a72SBiju Das 497*254d3a72SBiju Das mutex_init(&rz_mtu3_pwm->lock); 498*254d3a72SBiju Das platform_set_drvdata(pdev, rz_mtu3_pwm); 499*254d3a72SBiju Das ret = clk_prepare_enable(rz_mtu3_pwm->clk); 500*254d3a72SBiju Das if (ret) 501*254d3a72SBiju Das return dev_err_probe(dev, ret, "Clock enable failed\n"); 502*254d3a72SBiju Das 503*254d3a72SBiju Das clk_rate_exclusive_get(rz_mtu3_pwm->clk); 504*254d3a72SBiju Das 505*254d3a72SBiju Das rz_mtu3_pwm->rate = clk_get_rate(rz_mtu3_pwm->clk); 506*254d3a72SBiju Das /* 507*254d3a72SBiju Das * Refuse clk rates > 1 GHz to prevent overflow later for computing 508*254d3a72SBiju Das * period and duty cycle. 509*254d3a72SBiju Das */ 510*254d3a72SBiju Das if (rz_mtu3_pwm->rate > NSEC_PER_SEC) { 511*254d3a72SBiju Das ret = -EINVAL; 512*254d3a72SBiju Das clk_rate_exclusive_put(rz_mtu3_pwm->clk); 513*254d3a72SBiju Das goto disable_clock; 514*254d3a72SBiju Das } 515*254d3a72SBiju Das 516*254d3a72SBiju Das pm_runtime_set_active(&pdev->dev); 517*254d3a72SBiju Das pm_runtime_enable(&pdev->dev); 518*254d3a72SBiju Das rz_mtu3_pwm->chip.dev = &pdev->dev; 519*254d3a72SBiju Das ret = devm_add_action_or_reset(&pdev->dev, rz_mtu3_pwm_pm_disable, 520*254d3a72SBiju Das rz_mtu3_pwm); 521*254d3a72SBiju Das if (ret < 0) 522*254d3a72SBiju Das return ret; 523*254d3a72SBiju Das 524*254d3a72SBiju Das rz_mtu3_pwm->chip.ops = &rz_mtu3_pwm_ops; 525*254d3a72SBiju Das rz_mtu3_pwm->chip.npwm = RZ_MTU3_MAX_PWM_CHANNELS; 526*254d3a72SBiju Das ret = devm_pwmchip_add(&pdev->dev, &rz_mtu3_pwm->chip); 527*254d3a72SBiju Das if (ret) 528*254d3a72SBiju Das return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n"); 529*254d3a72SBiju Das 530*254d3a72SBiju Das pm_runtime_idle(&pdev->dev); 531*254d3a72SBiju Das 532*254d3a72SBiju Das return 0; 533*254d3a72SBiju Das 534*254d3a72SBiju Das disable_clock: 535*254d3a72SBiju Das clk_disable_unprepare(rz_mtu3_pwm->clk); 536*254d3a72SBiju Das return ret; 537*254d3a72SBiju Das } 538*254d3a72SBiju Das 539*254d3a72SBiju Das static struct platform_driver rz_mtu3_pwm_driver = { 540*254d3a72SBiju Das .driver = { 541*254d3a72SBiju Das .name = "pwm-rz-mtu3", 542*254d3a72SBiju Das .pm = pm_ptr(&rz_mtu3_pwm_pm_ops), 543*254d3a72SBiju Das }, 544*254d3a72SBiju Das .probe = rz_mtu3_pwm_probe, 545*254d3a72SBiju Das }; 546*254d3a72SBiju Das module_platform_driver(rz_mtu3_pwm_driver); 547*254d3a72SBiju Das 548*254d3a72SBiju Das MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 549*254d3a72SBiju Das MODULE_ALIAS("platform:pwm-rz-mtu3"); 550*254d3a72SBiju Das MODULE_DESCRIPTION("Renesas RZ/G2L MTU3a PWM Timer Driver"); 551*254d3a72SBiju Das MODULE_LICENSE("GPL"); 552