1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R-Car PWM Timer driver 4 * 5 * Copyright (C) 2015 Renesas Electronics Corporation 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/pwm.h> 16 #include <linux/slab.h> 17 18 #define RCAR_PWM_MAX_DIVISION 24 19 #define RCAR_PWM_MAX_CYCLE 1023 20 21 #define RCAR_PWMCR 0x00 22 #define RCAR_PWMCR_CC0_MASK 0x000f0000 23 #define RCAR_PWMCR_CC0_SHIFT 16 24 #define RCAR_PWMCR_CCMD BIT(15) 25 #define RCAR_PWMCR_SYNC BIT(11) 26 #define RCAR_PWMCR_SS0 BIT(4) 27 #define RCAR_PWMCR_EN0 BIT(0) 28 29 #define RCAR_PWMCNT 0x04 30 #define RCAR_PWMCNT_CYC0_MASK 0x03ff0000 31 #define RCAR_PWMCNT_CYC0_SHIFT 16 32 #define RCAR_PWMCNT_PH0_MASK 0x000003ff 33 #define RCAR_PWMCNT_PH0_SHIFT 0 34 35 struct rcar_pwm_chip { 36 struct pwm_chip chip; 37 void __iomem *base; 38 struct clk *clk; 39 }; 40 41 static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip) 42 { 43 return container_of(chip, struct rcar_pwm_chip, chip); 44 } 45 46 static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data, 47 unsigned int offset) 48 { 49 writel(data, rp->base + offset); 50 } 51 52 static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset) 53 { 54 return readl(rp->base + offset); 55 } 56 57 static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data, 58 unsigned int offset) 59 { 60 u32 value; 61 62 value = rcar_pwm_read(rp, offset); 63 value &= ~mask; 64 value |= data & mask; 65 rcar_pwm_write(rp, value, offset); 66 } 67 68 static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns) 69 { 70 unsigned long clk_rate = clk_get_rate(rp->clk); 71 unsigned long long max; /* max cycle / nanoseconds */ 72 unsigned int div; 73 74 if (clk_rate == 0) 75 return -EINVAL; 76 77 for (div = 0; div <= RCAR_PWM_MAX_DIVISION; div++) { 78 max = (unsigned long long)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE * 79 (1 << div); 80 do_div(max, clk_rate); 81 if (period_ns <= max) 82 break; 83 } 84 85 return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE; 86 } 87 88 static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp, 89 unsigned int div) 90 { 91 u32 value; 92 93 value = rcar_pwm_read(rp, RCAR_PWMCR); 94 value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK); 95 96 if (div & 1) 97 value |= RCAR_PWMCR_CCMD; 98 99 div >>= 1; 100 101 value |= div << RCAR_PWMCR_CC0_SHIFT; 102 rcar_pwm_write(rp, value, RCAR_PWMCR); 103 } 104 105 static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns, 106 int period_ns) 107 { 108 unsigned long long one_cycle, tmp; /* 0.01 nanoseconds */ 109 unsigned long clk_rate = clk_get_rate(rp->clk); 110 u32 cyc, ph; 111 112 one_cycle = (unsigned long long)NSEC_PER_SEC * 100ULL * (1 << div); 113 do_div(one_cycle, clk_rate); 114 115 tmp = period_ns * 100ULL; 116 do_div(tmp, one_cycle); 117 cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK; 118 119 tmp = duty_ns * 100ULL; 120 do_div(tmp, one_cycle); 121 ph = tmp & RCAR_PWMCNT_PH0_MASK; 122 123 /* Avoid prohibited setting */ 124 if (cyc == 0 || ph == 0) 125 return -EINVAL; 126 127 rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT); 128 129 return 0; 130 } 131 132 static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 133 { 134 return pm_runtime_get_sync(chip->dev); 135 } 136 137 static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 138 { 139 pm_runtime_put(chip->dev); 140 } 141 142 static int rcar_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 143 int duty_ns, int period_ns) 144 { 145 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); 146 int div, ret; 147 148 div = rcar_pwm_get_clock_division(rp, period_ns); 149 if (div < 0) 150 return div; 151 152 /* 153 * Let the core driver set pwm->period if disabled and duty_ns == 0. 154 * But, this driver should prevent to set the new duty_ns if current 155 * duty_cycle is not set 156 */ 157 if (!pwm_is_enabled(pwm) && !duty_ns && !pwm->state.duty_cycle) 158 return 0; 159 160 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR); 161 162 ret = rcar_pwm_set_counter(rp, div, duty_ns, period_ns); 163 if (!ret) 164 rcar_pwm_set_clock_control(rp, div); 165 166 /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */ 167 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR); 168 169 return ret; 170 } 171 172 static int rcar_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 173 { 174 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); 175 u32 value; 176 177 /* Don't enable the PWM device if CYC0 or PH0 is 0 */ 178 value = rcar_pwm_read(rp, RCAR_PWMCNT); 179 if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 || 180 (value & RCAR_PWMCNT_PH0_MASK) == 0) 181 return -EINVAL; 182 183 rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR); 184 185 return 0; 186 } 187 188 static void rcar_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 189 { 190 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); 191 192 rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR); 193 } 194 195 static const struct pwm_ops rcar_pwm_ops = { 196 .request = rcar_pwm_request, 197 .free = rcar_pwm_free, 198 .config = rcar_pwm_config, 199 .enable = rcar_pwm_enable, 200 .disable = rcar_pwm_disable, 201 .owner = THIS_MODULE, 202 }; 203 204 static int rcar_pwm_probe(struct platform_device *pdev) 205 { 206 struct rcar_pwm_chip *rcar_pwm; 207 struct resource *res; 208 int ret; 209 210 rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL); 211 if (rcar_pwm == NULL) 212 return -ENOMEM; 213 214 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 215 rcar_pwm->base = devm_ioremap_resource(&pdev->dev, res); 216 if (IS_ERR(rcar_pwm->base)) 217 return PTR_ERR(rcar_pwm->base); 218 219 rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL); 220 if (IS_ERR(rcar_pwm->clk)) { 221 dev_err(&pdev->dev, "cannot get clock\n"); 222 return PTR_ERR(rcar_pwm->clk); 223 } 224 225 platform_set_drvdata(pdev, rcar_pwm); 226 227 rcar_pwm->chip.dev = &pdev->dev; 228 rcar_pwm->chip.ops = &rcar_pwm_ops; 229 rcar_pwm->chip.base = -1; 230 rcar_pwm->chip.npwm = 1; 231 232 ret = pwmchip_add(&rcar_pwm->chip); 233 if (ret < 0) { 234 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret); 235 return ret; 236 } 237 238 pm_runtime_enable(&pdev->dev); 239 240 return 0; 241 } 242 243 static int rcar_pwm_remove(struct platform_device *pdev) 244 { 245 struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev); 246 247 pm_runtime_disable(&pdev->dev); 248 249 return pwmchip_remove(&rcar_pwm->chip); 250 } 251 252 static const struct of_device_id rcar_pwm_of_table[] = { 253 { .compatible = "renesas,pwm-rcar", }, 254 { }, 255 }; 256 MODULE_DEVICE_TABLE(of, rcar_pwm_of_table); 257 258 #ifdef CONFIG_PM_SLEEP 259 static struct pwm_device *rcar_pwm_dev_to_pwm_dev(struct device *dev) 260 { 261 struct rcar_pwm_chip *rcar_pwm = dev_get_drvdata(dev); 262 struct pwm_chip *chip = &rcar_pwm->chip; 263 264 return &chip->pwms[0]; 265 } 266 267 static int rcar_pwm_suspend(struct device *dev) 268 { 269 struct pwm_device *pwm = rcar_pwm_dev_to_pwm_dev(dev); 270 271 if (!test_bit(PWMF_REQUESTED, &pwm->flags)) 272 return 0; 273 274 pm_runtime_put(dev); 275 276 return 0; 277 } 278 279 static int rcar_pwm_resume(struct device *dev) 280 { 281 struct pwm_device *pwm = rcar_pwm_dev_to_pwm_dev(dev); 282 283 if (!test_bit(PWMF_REQUESTED, &pwm->flags)) 284 return 0; 285 286 pm_runtime_get_sync(dev); 287 288 rcar_pwm_config(pwm->chip, pwm, pwm->state.duty_cycle, 289 pwm->state.period); 290 if (pwm_is_enabled(pwm)) 291 rcar_pwm_enable(pwm->chip, pwm); 292 293 return 0; 294 } 295 #endif /* CONFIG_PM_SLEEP */ 296 static SIMPLE_DEV_PM_OPS(rcar_pwm_pm_ops, rcar_pwm_suspend, rcar_pwm_resume); 297 298 static struct platform_driver rcar_pwm_driver = { 299 .probe = rcar_pwm_probe, 300 .remove = rcar_pwm_remove, 301 .driver = { 302 .name = "pwm-rcar", 303 .pm = &rcar_pwm_pm_ops, 304 .of_match_table = of_match_ptr(rcar_pwm_of_table), 305 } 306 }; 307 module_platform_driver(rcar_pwm_driver); 308 309 MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>"); 310 MODULE_DESCRIPTION("Renesas PWM Timer Driver"); 311 MODULE_LICENSE("GPL v2"); 312 MODULE_ALIAS("platform:pwm-rcar"); 313