1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/pwm/pwm-pxa.c
4 *
5 * simple driver for PWM (Pulse Width Modulator) controller
6 *
7 * 2008-02-13 initial version
8 * eric miao <eric.miao@marvell.com>
9 *
10 * Links to reference manuals for some of the supported PWM chips can be found
11 * in Documentation/arch/arm/marvell.rst.
12 *
13 * Limitations:
14 * - When PWM is stopped, the current PWM period stops abruptly at the next
15 * input clock (PWMCR_SD is set) and the output is driven to inactive.
16 */
17
18 #include <linux/mod_devicetable.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <linux/err.h>
24 #include <linux/clk.h>
25 #include <linux/io.h>
26 #include <linux/pwm.h>
27 #include <linux/of_device.h>
28
29 #include <asm/div64.h>
30
31 #define HAS_SECONDARY_PWM 0x10
32
33 static const struct platform_device_id pwm_id_table[] = {
34 /* PWM has_secondary_pwm? */
35 { "pxa25x-pwm", 0 },
36 { "pxa27x-pwm", HAS_SECONDARY_PWM },
37 { "pxa168-pwm", 0 },
38 { "pxa910-pwm", 0 },
39 { },
40 };
41 MODULE_DEVICE_TABLE(platform, pwm_id_table);
42
43 /* PWM registers and bits definitions */
44 #define PWMCR (0x00)
45 #define PWMDCR (0x04)
46 #define PWMPCR (0x08)
47
48 #define PWMCR_SD (1 << 6)
49 #define PWMDCR_FD (1 << 10)
50
51 struct pxa_pwm_chip {
52 struct pwm_chip chip;
53 struct device *dev;
54
55 struct clk *clk;
56 void __iomem *mmio_base;
57 };
58
to_pxa_pwm_chip(struct pwm_chip * chip)59 static inline struct pxa_pwm_chip *to_pxa_pwm_chip(struct pwm_chip *chip)
60 {
61 return container_of(chip, struct pxa_pwm_chip, chip);
62 }
63
64 /*
65 * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
66 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
67 */
pxa_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,u64 duty_ns,u64 period_ns)68 static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
69 u64 duty_ns, u64 period_ns)
70 {
71 struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
72 unsigned long long c;
73 unsigned long period_cycles, prescale, pv, dc;
74 unsigned long offset;
75
76 offset = pwm->hwpwm ? 0x10 : 0;
77
78 c = clk_get_rate(pc->clk);
79 c = c * period_ns;
80 do_div(c, 1000000000);
81 period_cycles = c;
82
83 if (period_cycles < 1)
84 period_cycles = 1;
85 prescale = (period_cycles - 1) / 1024;
86 pv = period_cycles / (prescale + 1) - 1;
87
88 if (prescale > 63)
89 return -EINVAL;
90
91 if (duty_ns == period_ns)
92 dc = PWMDCR_FD;
93 else
94 dc = mul_u64_u64_div_u64(pv + 1, duty_ns, period_ns);
95
96 writel(prescale | PWMCR_SD, pc->mmio_base + offset + PWMCR);
97 writel(dc, pc->mmio_base + offset + PWMDCR);
98 writel(pv, pc->mmio_base + offset + PWMPCR);
99
100 return 0;
101 }
102
pxa_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)103 static int pxa_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
104 const struct pwm_state *state)
105 {
106 struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
107 u64 duty_cycle;
108 int err;
109
110 if (state->polarity != PWM_POLARITY_NORMAL)
111 return -EINVAL;
112
113 err = clk_prepare_enable(pc->clk);
114 if (err)
115 return err;
116
117 duty_cycle = state->enabled ? state->duty_cycle : 0;
118
119 err = pxa_pwm_config(chip, pwm, duty_cycle, state->period);
120 if (err) {
121 clk_disable_unprepare(pc->clk);
122 return err;
123 }
124
125 if (state->enabled && !pwm->state.enabled)
126 return 0;
127
128 clk_disable_unprepare(pc->clk);
129
130 if (!state->enabled && pwm->state.enabled)
131 clk_disable_unprepare(pc->clk);
132
133 return 0;
134 }
135
136 static const struct pwm_ops pxa_pwm_ops = {
137 .apply = pxa_pwm_apply,
138 .owner = THIS_MODULE,
139 };
140
141 #ifdef CONFIG_OF
142 /*
143 * Device tree users must create one device instance for each PWM channel.
144 * Hence we dispense with the HAS_SECONDARY_PWM and "tell" the original driver
145 * code that this is a single channel pxa25x-pwm. Currently all devices are
146 * supported identically.
147 */
148 static const struct of_device_id pwm_of_match[] = {
149 { .compatible = "marvell,pxa250-pwm", .data = &pwm_id_table[0]},
150 { .compatible = "marvell,pxa270-pwm", .data = &pwm_id_table[0]},
151 { .compatible = "marvell,pxa168-pwm", .data = &pwm_id_table[0]},
152 { .compatible = "marvell,pxa910-pwm", .data = &pwm_id_table[0]},
153 { }
154 };
155 MODULE_DEVICE_TABLE(of, pwm_of_match);
156 #else
157 #define pwm_of_match NULL
158 #endif
159
pwm_probe(struct platform_device * pdev)160 static int pwm_probe(struct platform_device *pdev)
161 {
162 const struct platform_device_id *id = platform_get_device_id(pdev);
163 struct pxa_pwm_chip *pc;
164 int ret = 0;
165
166 if (IS_ENABLED(CONFIG_OF) && id == NULL)
167 id = of_device_get_match_data(&pdev->dev);
168
169 if (id == NULL)
170 return -EINVAL;
171
172 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
173 if (pc == NULL)
174 return -ENOMEM;
175
176 pc->clk = devm_clk_get(&pdev->dev, NULL);
177 if (IS_ERR(pc->clk))
178 return PTR_ERR(pc->clk);
179
180 pc->chip.dev = &pdev->dev;
181 pc->chip.ops = &pxa_pwm_ops;
182 pc->chip.npwm = (id->driver_data & HAS_SECONDARY_PWM) ? 2 : 1;
183
184 if (IS_ENABLED(CONFIG_OF)) {
185 pc->chip.of_xlate = of_pwm_single_xlate;
186 pc->chip.of_pwm_n_cells = 1;
187 }
188
189 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);
190 if (IS_ERR(pc->mmio_base))
191 return PTR_ERR(pc->mmio_base);
192
193 ret = devm_pwmchip_add(&pdev->dev, &pc->chip);
194 if (ret < 0) {
195 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
196 return ret;
197 }
198
199 return 0;
200 }
201
202 static struct platform_driver pwm_driver = {
203 .driver = {
204 .name = "pxa25x-pwm",
205 .of_match_table = pwm_of_match,
206 },
207 .probe = pwm_probe,
208 .id_table = pwm_id_table,
209 };
210
211 module_platform_driver(pwm_driver);
212
213 MODULE_LICENSE("GPL v2");
214