1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2012 Freescale Semiconductor, Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/err.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/platform_device.h> 14 #include <linux/pwm.h> 15 #include <linux/slab.h> 16 #include <linux/stmp_device.h> 17 18 #define SET 0x4 19 #define CLR 0x8 20 #define TOG 0xc 21 22 #define PWM_CTRL 0x0 23 #define PWM_ACTIVE0 0x10 24 #define PWM_PERIOD0 0x20 25 #define PERIOD_PERIOD(p) ((p) & 0xffff) 26 #define PERIOD_PERIOD_MAX 0x10000 27 #define PERIOD_ACTIVE_HIGH (3 << 16) 28 #define PERIOD_ACTIVE_LOW (2 << 16) 29 #define PERIOD_INACTIVE_HIGH (3 << 18) 30 #define PERIOD_INACTIVE_LOW (2 << 18) 31 #define PERIOD_POLARITY_NORMAL (PERIOD_ACTIVE_HIGH | PERIOD_INACTIVE_LOW) 32 #define PERIOD_POLARITY_INVERSE (PERIOD_ACTIVE_LOW | PERIOD_INACTIVE_HIGH) 33 #define PERIOD_CDIV(div) (((div) & 0x7) << 20) 34 #define PERIOD_CDIV_MAX 8 35 36 static const u8 cdiv_shift[PERIOD_CDIV_MAX] = { 37 0, 1, 2, 3, 4, 6, 8, 10 38 }; 39 40 struct mxs_pwm_chip { 41 struct pwm_chip chip; 42 struct clk *clk; 43 void __iomem *base; 44 }; 45 46 #define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip) 47 48 static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 49 const struct pwm_state *state) 50 { 51 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip); 52 int ret, div = 0; 53 unsigned int period_cycles, duty_cycles; 54 unsigned long rate; 55 unsigned long long c; 56 unsigned int pol_bits; 57 58 /* 59 * If the PWM channel is disabled, make sure to turn on the 60 * clock before calling clk_get_rate() and writing to the 61 * registers. Otherwise, just keep it enabled. 62 */ 63 if (!pwm_is_enabled(pwm)) { 64 ret = clk_prepare_enable(mxs->clk); 65 if (ret) 66 return ret; 67 } 68 69 if (!state->enabled && pwm_is_enabled(pwm)) 70 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR); 71 72 rate = clk_get_rate(mxs->clk); 73 while (1) { 74 c = rate >> cdiv_shift[div]; 75 c = c * state->period; 76 do_div(c, 1000000000); 77 if (c < PERIOD_PERIOD_MAX) 78 break; 79 div++; 80 if (div >= PERIOD_CDIV_MAX) 81 return -EINVAL; 82 } 83 84 period_cycles = c; 85 c *= state->duty_cycle; 86 do_div(c, state->period); 87 duty_cycles = c; 88 89 /* 90 * The data sheet the says registers must be written to in 91 * this order (ACTIVEn, then PERIODn). Also, the new settings 92 * only take effect at the beginning of a new period, avoiding 93 * glitches. 94 */ 95 96 pol_bits = state->polarity == PWM_POLARITY_NORMAL ? 97 PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE; 98 writel(duty_cycles << 16, 99 mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20); 100 writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div), 101 mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20); 102 103 if (state->enabled) { 104 if (!pwm_is_enabled(pwm)) { 105 /* 106 * The clock was enabled above. Just enable 107 * the channel in the control register. 108 */ 109 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET); 110 } 111 } else { 112 clk_disable_unprepare(mxs->clk); 113 } 114 return 0; 115 } 116 117 static const struct pwm_ops mxs_pwm_ops = { 118 .apply = mxs_pwm_apply, 119 .owner = THIS_MODULE, 120 }; 121 122 static int mxs_pwm_probe(struct platform_device *pdev) 123 { 124 struct device_node *np = pdev->dev.of_node; 125 struct mxs_pwm_chip *mxs; 126 int ret; 127 128 mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL); 129 if (!mxs) 130 return -ENOMEM; 131 132 mxs->base = devm_platform_ioremap_resource(pdev, 0); 133 if (IS_ERR(mxs->base)) 134 return PTR_ERR(mxs->base); 135 136 mxs->clk = devm_clk_get(&pdev->dev, NULL); 137 if (IS_ERR(mxs->clk)) 138 return PTR_ERR(mxs->clk); 139 140 mxs->chip.dev = &pdev->dev; 141 mxs->chip.ops = &mxs_pwm_ops; 142 mxs->chip.of_xlate = of_pwm_xlate_with_flags; 143 mxs->chip.of_pwm_n_cells = 3; 144 mxs->chip.base = -1; 145 146 ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm); 147 if (ret < 0) { 148 dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret); 149 return ret; 150 } 151 152 ret = pwmchip_add(&mxs->chip); 153 if (ret < 0) { 154 dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret); 155 return ret; 156 } 157 158 platform_set_drvdata(pdev, mxs); 159 160 ret = stmp_reset_block(mxs->base); 161 if (ret) 162 goto pwm_remove; 163 164 return 0; 165 166 pwm_remove: 167 pwmchip_remove(&mxs->chip); 168 return ret; 169 } 170 171 static int mxs_pwm_remove(struct platform_device *pdev) 172 { 173 struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev); 174 175 return pwmchip_remove(&mxs->chip); 176 } 177 178 static const struct of_device_id mxs_pwm_dt_ids[] = { 179 { .compatible = "fsl,imx23-pwm", }, 180 { /* sentinel */ } 181 }; 182 MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids); 183 184 static struct platform_driver mxs_pwm_driver = { 185 .driver = { 186 .name = "mxs-pwm", 187 .of_match_table = mxs_pwm_dt_ids, 188 }, 189 .probe = mxs_pwm_probe, 190 .remove = mxs_pwm_remove, 191 }; 192 module_platform_driver(mxs_pwm_driver); 193 194 MODULE_ALIAS("platform:mxs-pwm"); 195 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 196 MODULE_DESCRIPTION("Freescale MXS PWM Driver"); 197 MODULE_LICENSE("GPL v2"); 198