1 /* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright (c) 2016 BayLibre, SAS. 8 * Author: Neil Armstrong <narmstrong@baylibre.com> 9 * Copyright (C) 2014 Amlogic, Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, see <http://www.gnu.org/licenses/>. 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * BSD LICENSE 26 * 27 * Copyright (c) 2016 BayLibre, SAS. 28 * Author: Neil Armstrong <narmstrong@baylibre.com> 29 * Copyright (C) 2014 Amlogic, Inc. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 35 * * Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * * Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in 39 * the documentation and/or other materials provided with the 40 * distribution. 41 * * Neither the name of Intel Corporation nor the names of its 42 * contributors may be used to endorse or promote products derived 43 * from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 46 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 47 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 48 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 49 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 50 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 51 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 55 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57 58 #include <linux/clk.h> 59 #include <linux/clk-provider.h> 60 #include <linux/err.h> 61 #include <linux/io.h> 62 #include <linux/kernel.h> 63 #include <linux/module.h> 64 #include <linux/of.h> 65 #include <linux/of_device.h> 66 #include <linux/platform_device.h> 67 #include <linux/pwm.h> 68 #include <linux/slab.h> 69 #include <linux/spinlock.h> 70 71 #define REG_PWM_A 0x0 72 #define REG_PWM_B 0x4 73 #define PWM_HIGH_SHIFT 16 74 75 #define REG_MISC_AB 0x8 76 #define MISC_B_CLK_EN BIT(23) 77 #define MISC_A_CLK_EN BIT(15) 78 #define MISC_CLK_DIV_MASK 0x7f 79 #define MISC_B_CLK_DIV_SHIFT 16 80 #define MISC_A_CLK_DIV_SHIFT 8 81 #define MISC_B_CLK_SEL_SHIFT 6 82 #define MISC_A_CLK_SEL_SHIFT 4 83 #define MISC_CLK_SEL_WIDTH 2 84 #define MISC_B_EN BIT(1) 85 #define MISC_A_EN BIT(0) 86 87 static const unsigned int mux_reg_shifts[] = { 88 MISC_A_CLK_SEL_SHIFT, 89 MISC_B_CLK_SEL_SHIFT 90 }; 91 92 struct meson_pwm_channel { 93 unsigned int hi; 94 unsigned int lo; 95 u8 pre_div; 96 97 struct pwm_state state; 98 99 struct clk *clk_parent; 100 struct clk_mux mux; 101 struct clk *clk; 102 }; 103 104 struct meson_pwm_data { 105 const char * const *parent_names; 106 unsigned int num_parents; 107 }; 108 109 struct meson_pwm { 110 struct pwm_chip chip; 111 const struct meson_pwm_data *data; 112 void __iomem *base; 113 u8 inverter_mask; 114 /* 115 * Protects register (write) access to the REG_MISC_AB register 116 * that is shared between the two PWMs. 117 */ 118 spinlock_t lock; 119 }; 120 121 static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip) 122 { 123 return container_of(chip, struct meson_pwm, chip); 124 } 125 126 static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 127 { 128 struct meson_pwm_channel *channel = pwm_get_chip_data(pwm); 129 struct device *dev = chip->dev; 130 int err; 131 132 if (!channel) 133 return -ENODEV; 134 135 if (channel->clk_parent) { 136 err = clk_set_parent(channel->clk, channel->clk_parent); 137 if (err < 0) { 138 dev_err(dev, "failed to set parent %s for %s: %d\n", 139 __clk_get_name(channel->clk_parent), 140 __clk_get_name(channel->clk), err); 141 return err; 142 } 143 } 144 145 err = clk_prepare_enable(channel->clk); 146 if (err < 0) { 147 dev_err(dev, "failed to enable clock %s: %d\n", 148 __clk_get_name(channel->clk), err); 149 return err; 150 } 151 152 chip->ops->get_state(chip, pwm, &channel->state); 153 154 return 0; 155 } 156 157 static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 158 { 159 struct meson_pwm_channel *channel = pwm_get_chip_data(pwm); 160 161 if (channel) 162 clk_disable_unprepare(channel->clk); 163 } 164 165 static int meson_pwm_calc(struct meson_pwm *meson, 166 struct meson_pwm_channel *channel, unsigned int id, 167 unsigned int duty, unsigned int period) 168 { 169 unsigned int pre_div, cnt, duty_cnt; 170 unsigned long fin_freq = -1; 171 u64 fin_ps; 172 173 if (~(meson->inverter_mask >> id) & 0x1) 174 duty = period - duty; 175 176 if (period == channel->state.period && 177 duty == channel->state.duty_cycle) 178 return 0; 179 180 fin_freq = clk_get_rate(channel->clk); 181 if (fin_freq == 0) { 182 dev_err(meson->chip.dev, "invalid source clock frequency\n"); 183 return -EINVAL; 184 } 185 186 dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq); 187 fin_ps = (u64)NSEC_PER_SEC * 1000; 188 do_div(fin_ps, fin_freq); 189 190 /* Calc pre_div with the period */ 191 for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) { 192 cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000, 193 fin_ps * (pre_div + 1)); 194 dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n", 195 fin_ps, pre_div, cnt); 196 if (cnt <= 0xffff) 197 break; 198 } 199 200 if (pre_div > MISC_CLK_DIV_MASK) { 201 dev_err(meson->chip.dev, "unable to get period pre_div\n"); 202 return -EINVAL; 203 } 204 205 dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period, 206 pre_div, cnt); 207 208 if (duty == period) { 209 channel->pre_div = pre_div; 210 channel->hi = cnt; 211 channel->lo = 0; 212 } else if (duty == 0) { 213 channel->pre_div = pre_div; 214 channel->hi = 0; 215 channel->lo = cnt; 216 } else { 217 /* Then check is we can have the duty with the same pre_div */ 218 duty_cnt = DIV_ROUND_CLOSEST_ULL((u64)duty * 1000, 219 fin_ps * (pre_div + 1)); 220 if (duty_cnt > 0xffff) { 221 dev_err(meson->chip.dev, "unable to get duty cycle\n"); 222 return -EINVAL; 223 } 224 225 dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n", 226 duty, pre_div, duty_cnt); 227 228 channel->pre_div = pre_div; 229 channel->hi = duty_cnt; 230 channel->lo = cnt - duty_cnt; 231 } 232 233 return 0; 234 } 235 236 static void meson_pwm_enable(struct meson_pwm *meson, 237 struct meson_pwm_channel *channel, 238 unsigned int id) 239 { 240 u32 value, clk_shift, clk_enable, enable; 241 unsigned int offset; 242 unsigned long flags; 243 244 switch (id) { 245 case 0: 246 clk_shift = MISC_A_CLK_DIV_SHIFT; 247 clk_enable = MISC_A_CLK_EN; 248 enable = MISC_A_EN; 249 offset = REG_PWM_A; 250 break; 251 252 case 1: 253 clk_shift = MISC_B_CLK_DIV_SHIFT; 254 clk_enable = MISC_B_CLK_EN; 255 enable = MISC_B_EN; 256 offset = REG_PWM_B; 257 break; 258 259 default: 260 return; 261 } 262 263 spin_lock_irqsave(&meson->lock, flags); 264 265 value = readl(meson->base + REG_MISC_AB); 266 value &= ~(MISC_CLK_DIV_MASK << clk_shift); 267 value |= channel->pre_div << clk_shift; 268 value |= clk_enable; 269 writel(value, meson->base + REG_MISC_AB); 270 271 value = (channel->hi << PWM_HIGH_SHIFT) | channel->lo; 272 writel(value, meson->base + offset); 273 274 value = readl(meson->base + REG_MISC_AB); 275 value |= enable; 276 writel(value, meson->base + REG_MISC_AB); 277 278 spin_unlock_irqrestore(&meson->lock, flags); 279 } 280 281 static void meson_pwm_disable(struct meson_pwm *meson, unsigned int id) 282 { 283 u32 value, enable; 284 unsigned long flags; 285 286 switch (id) { 287 case 0: 288 enable = MISC_A_EN; 289 break; 290 291 case 1: 292 enable = MISC_B_EN; 293 break; 294 295 default: 296 return; 297 } 298 299 spin_lock_irqsave(&meson->lock, flags); 300 301 value = readl(meson->base + REG_MISC_AB); 302 value &= ~enable; 303 writel(value, meson->base + REG_MISC_AB); 304 305 spin_unlock_irqrestore(&meson->lock, flags); 306 } 307 308 static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 309 struct pwm_state *state) 310 { 311 struct meson_pwm_channel *channel = pwm_get_chip_data(pwm); 312 struct meson_pwm *meson = to_meson_pwm(chip); 313 int err = 0; 314 315 if (!state) 316 return -EINVAL; 317 318 if (!state->enabled) { 319 meson_pwm_disable(meson, pwm->hwpwm); 320 channel->state.enabled = false; 321 322 return 0; 323 } 324 325 if (state->period != channel->state.period || 326 state->duty_cycle != channel->state.duty_cycle || 327 state->polarity != channel->state.polarity) { 328 if (state->polarity != channel->state.polarity) { 329 if (state->polarity == PWM_POLARITY_NORMAL) 330 meson->inverter_mask |= BIT(pwm->hwpwm); 331 else 332 meson->inverter_mask &= ~BIT(pwm->hwpwm); 333 } 334 335 err = meson_pwm_calc(meson, channel, pwm->hwpwm, 336 state->duty_cycle, state->period); 337 if (err < 0) 338 return err; 339 340 channel->state.polarity = state->polarity; 341 channel->state.period = state->period; 342 channel->state.duty_cycle = state->duty_cycle; 343 } 344 345 if (state->enabled && !channel->state.enabled) { 346 meson_pwm_enable(meson, channel, pwm->hwpwm); 347 channel->state.enabled = true; 348 } 349 350 return 0; 351 } 352 353 static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 354 struct pwm_state *state) 355 { 356 struct meson_pwm *meson = to_meson_pwm(chip); 357 u32 value, mask; 358 359 if (!state) 360 return; 361 362 switch (pwm->hwpwm) { 363 case 0: 364 mask = MISC_A_EN; 365 break; 366 367 case 1: 368 mask = MISC_B_EN; 369 break; 370 371 default: 372 return; 373 } 374 375 value = readl(meson->base + REG_MISC_AB); 376 state->enabled = (value & mask) != 0; 377 } 378 379 static const struct pwm_ops meson_pwm_ops = { 380 .request = meson_pwm_request, 381 .free = meson_pwm_free, 382 .apply = meson_pwm_apply, 383 .get_state = meson_pwm_get_state, 384 .owner = THIS_MODULE, 385 }; 386 387 static const char * const pwm_meson8b_parent_names[] = { 388 "xtal", "vid_pll", "fclk_div4", "fclk_div3" 389 }; 390 391 static const struct meson_pwm_data pwm_meson8b_data = { 392 .parent_names = pwm_meson8b_parent_names, 393 .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names), 394 }; 395 396 static const char * const pwm_gxbb_parent_names[] = { 397 "xtal", "hdmi_pll", "fclk_div4", "fclk_div3" 398 }; 399 400 static const struct meson_pwm_data pwm_gxbb_data = { 401 .parent_names = pwm_gxbb_parent_names, 402 .num_parents = ARRAY_SIZE(pwm_gxbb_parent_names), 403 }; 404 405 /* 406 * Only the 2 first inputs of the GXBB AO PWMs are valid 407 * The last 2 are grounded 408 */ 409 static const char * const pwm_gxbb_ao_parent_names[] = { 410 "xtal", "clk81" 411 }; 412 413 static const struct meson_pwm_data pwm_gxbb_ao_data = { 414 .parent_names = pwm_gxbb_ao_parent_names, 415 .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names), 416 }; 417 418 static const char * const pwm_axg_ee_parent_names[] = { 419 "xtal", "fclk_div5", "fclk_div4", "fclk_div3" 420 }; 421 422 static const struct meson_pwm_data pwm_axg_ee_data = { 423 .parent_names = pwm_axg_ee_parent_names, 424 .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names), 425 }; 426 427 static const char * const pwm_axg_ao_parent_names[] = { 428 "aoclk81", "xtal", "fclk_div4", "fclk_div5" 429 }; 430 431 static const struct meson_pwm_data pwm_axg_ao_data = { 432 .parent_names = pwm_axg_ao_parent_names, 433 .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), 434 }; 435 436 static const char * const pwm_g12a_ao_cd_parent_names[] = { 437 "aoclk81", "xtal", 438 }; 439 440 static const struct meson_pwm_data pwm_g12a_ao_cd_data = { 441 .parent_names = pwm_g12a_ao_cd_parent_names, 442 .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names), 443 }; 444 445 static const char * const pwm_g12a_ee_parent_names[] = { 446 "xtal", "hdmi_pll", "fclk_div4", "fclk_div3" 447 }; 448 449 static const struct meson_pwm_data pwm_g12a_ee_data = { 450 .parent_names = pwm_g12a_ee_parent_names, 451 .num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names), 452 }; 453 454 static const struct of_device_id meson_pwm_matches[] = { 455 { 456 .compatible = "amlogic,meson8b-pwm", 457 .data = &pwm_meson8b_data 458 }, 459 { 460 .compatible = "amlogic,meson-gxbb-pwm", 461 .data = &pwm_gxbb_data 462 }, 463 { 464 .compatible = "amlogic,meson-gxbb-ao-pwm", 465 .data = &pwm_gxbb_ao_data 466 }, 467 { 468 .compatible = "amlogic,meson-axg-ee-pwm", 469 .data = &pwm_axg_ee_data 470 }, 471 { 472 .compatible = "amlogic,meson-axg-ao-pwm", 473 .data = &pwm_axg_ao_data 474 }, 475 { 476 .compatible = "amlogic,meson-g12a-ee-pwm", 477 .data = &pwm_g12a_ee_data 478 }, 479 { 480 .compatible = "amlogic,meson-g12a-ao-pwm-ab", 481 .data = &pwm_axg_ao_data 482 }, 483 { 484 .compatible = "amlogic,meson-g12a-ao-pwm-cd", 485 .data = &pwm_g12a_ao_cd_data 486 }, 487 {}, 488 }; 489 MODULE_DEVICE_TABLE(of, meson_pwm_matches); 490 491 static int meson_pwm_init_channels(struct meson_pwm *meson, 492 struct meson_pwm_channel *channels) 493 { 494 struct device *dev = meson->chip.dev; 495 struct clk_init_data init; 496 unsigned int i; 497 char name[255]; 498 int err; 499 500 for (i = 0; i < meson->chip.npwm; i++) { 501 struct meson_pwm_channel *channel = &channels[i]; 502 503 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i); 504 505 init.name = name; 506 init.ops = &clk_mux_ops; 507 init.flags = 0; 508 init.parent_names = meson->data->parent_names; 509 init.num_parents = meson->data->num_parents; 510 511 channel->mux.reg = meson->base + REG_MISC_AB; 512 channel->mux.shift = mux_reg_shifts[i]; 513 channel->mux.mask = BIT(MISC_CLK_SEL_WIDTH) - 1; 514 channel->mux.flags = 0; 515 channel->mux.lock = &meson->lock; 516 channel->mux.table = NULL; 517 channel->mux.hw.init = &init; 518 519 channel->clk = devm_clk_register(dev, &channel->mux.hw); 520 if (IS_ERR(channel->clk)) { 521 err = PTR_ERR(channel->clk); 522 dev_err(dev, "failed to register %s: %d\n", name, err); 523 return err; 524 } 525 526 snprintf(name, sizeof(name), "clkin%u", i); 527 528 channel->clk_parent = devm_clk_get(dev, name); 529 if (IS_ERR(channel->clk_parent)) { 530 err = PTR_ERR(channel->clk_parent); 531 if (err == -EPROBE_DEFER) 532 return err; 533 534 channel->clk_parent = NULL; 535 } 536 } 537 538 return 0; 539 } 540 541 static void meson_pwm_add_channels(struct meson_pwm *meson, 542 struct meson_pwm_channel *channels) 543 { 544 unsigned int i; 545 546 for (i = 0; i < meson->chip.npwm; i++) 547 pwm_set_chip_data(&meson->chip.pwms[i], &channels[i]); 548 } 549 550 static int meson_pwm_probe(struct platform_device *pdev) 551 { 552 struct meson_pwm_channel *channels; 553 struct meson_pwm *meson; 554 struct resource *regs; 555 int err; 556 557 meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL); 558 if (!meson) 559 return -ENOMEM; 560 561 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 562 meson->base = devm_ioremap_resource(&pdev->dev, regs); 563 if (IS_ERR(meson->base)) 564 return PTR_ERR(meson->base); 565 566 spin_lock_init(&meson->lock); 567 meson->chip.dev = &pdev->dev; 568 meson->chip.ops = &meson_pwm_ops; 569 meson->chip.base = -1; 570 meson->chip.npwm = 2; 571 meson->chip.of_xlate = of_pwm_xlate_with_flags; 572 meson->chip.of_pwm_n_cells = 3; 573 574 meson->data = of_device_get_match_data(&pdev->dev); 575 meson->inverter_mask = BIT(meson->chip.npwm) - 1; 576 577 channels = devm_kcalloc(&pdev->dev, meson->chip.npwm, 578 sizeof(*channels), GFP_KERNEL); 579 if (!channels) 580 return -ENOMEM; 581 582 err = meson_pwm_init_channels(meson, channels); 583 if (err < 0) 584 return err; 585 586 err = pwmchip_add(&meson->chip); 587 if (err < 0) { 588 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err); 589 return err; 590 } 591 592 meson_pwm_add_channels(meson, channels); 593 594 platform_set_drvdata(pdev, meson); 595 596 return 0; 597 } 598 599 static int meson_pwm_remove(struct platform_device *pdev) 600 { 601 struct meson_pwm *meson = platform_get_drvdata(pdev); 602 603 return pwmchip_remove(&meson->chip); 604 } 605 606 static struct platform_driver meson_pwm_driver = { 607 .driver = { 608 .name = "meson-pwm", 609 .of_match_table = meson_pwm_matches, 610 }, 611 .probe = meson_pwm_probe, 612 .remove = meson_pwm_remove, 613 }; 614 module_platform_driver(meson_pwm_driver); 615 616 MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver"); 617 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 618 MODULE_LICENSE("Dual BSD/GPL"); 619