1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek Pulse Width Modulator driver 4 * 5 * Copyright (C) 2015 John Crispin <blogic@openwrt.org> 6 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com> 7 * 8 */ 9 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/ioport.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/clk.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/pwm.h> 20 #include <linux/slab.h> 21 #include <linux/types.h> 22 23 /* PWM registers and bits definitions */ 24 #define PWMCON 0x00 25 #define PWMHDUR 0x04 26 #define PWMLDUR 0x08 27 #define PWMGDUR 0x0c 28 #define PWMWAVENUM 0x28 29 #define PWMDWIDTH 0x2c 30 #define PWM45DWIDTH_FIXUP 0x30 31 #define PWMTHRES 0x30 32 #define PWM45THRES_FIXUP 0x34 33 #define PWM_CK_26M_SEL 0x210 34 35 #define PWM_CLK_DIV_MAX 7 36 37 struct pwm_mediatek_of_data { 38 unsigned int num_pwms; 39 bool pwm45_fixup; 40 bool has_ck_26m_sel; 41 const unsigned int *reg_offset; 42 }; 43 44 /** 45 * struct pwm_mediatek_chip - struct representing PWM chip 46 * @chip: linux PWM chip representation 47 * @regs: base address of PWM chip 48 * @clk_top: the top clock generator 49 * @clk_main: the clock used by PWM core 50 * @clk_pwms: the clock used by each PWM channel 51 * @clk_freq: the fix clock frequency of legacy MIPS SoC 52 * @soc: pointer to chip's platform data 53 */ 54 struct pwm_mediatek_chip { 55 struct pwm_chip chip; 56 void __iomem *regs; 57 struct clk *clk_top; 58 struct clk *clk_main; 59 struct clk **clk_pwms; 60 const struct pwm_mediatek_of_data *soc; 61 }; 62 63 static const unsigned int mtk_pwm_reg_offset_v1[] = { 64 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 65 }; 66 67 static const unsigned int mtk_pwm_reg_offset_v2[] = { 68 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 69 }; 70 71 static inline struct pwm_mediatek_chip * 72 to_pwm_mediatek_chip(struct pwm_chip *chip) 73 { 74 return container_of(chip, struct pwm_mediatek_chip, chip); 75 } 76 77 static int pwm_mediatek_clk_enable(struct pwm_chip *chip, 78 struct pwm_device *pwm) 79 { 80 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 81 int ret; 82 83 ret = clk_prepare_enable(pc->clk_top); 84 if (ret < 0) 85 return ret; 86 87 ret = clk_prepare_enable(pc->clk_main); 88 if (ret < 0) 89 goto disable_clk_top; 90 91 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]); 92 if (ret < 0) 93 goto disable_clk_main; 94 95 return 0; 96 97 disable_clk_main: 98 clk_disable_unprepare(pc->clk_main); 99 disable_clk_top: 100 clk_disable_unprepare(pc->clk_top); 101 102 return ret; 103 } 104 105 static void pwm_mediatek_clk_disable(struct pwm_chip *chip, 106 struct pwm_device *pwm) 107 { 108 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 109 110 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); 111 clk_disable_unprepare(pc->clk_main); 112 clk_disable_unprepare(pc->clk_top); 113 } 114 115 static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip, 116 unsigned int num, unsigned int offset, 117 u32 value) 118 { 119 writel(value, chip->regs + chip->soc->reg_offset[num] + offset); 120 } 121 122 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, 123 int duty_ns, int period_ns) 124 { 125 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 126 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, 127 reg_thres = PWMTHRES; 128 u64 resolution; 129 int ret; 130 131 ret = pwm_mediatek_clk_enable(chip, pwm); 132 133 if (ret < 0) 134 return ret; 135 136 /* Make sure we use the bus clock and not the 26MHz clock */ 137 if (pc->soc->has_ck_26m_sel) 138 writel(0, pc->regs + PWM_CK_26M_SEL); 139 140 /* Using resolution in picosecond gets accuracy higher */ 141 resolution = (u64)NSEC_PER_SEC * 1000; 142 do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm])); 143 144 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); 145 while (cnt_period > 8191) { 146 resolution *= 2; 147 clkdiv++; 148 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, 149 resolution); 150 } 151 152 if (clkdiv > PWM_CLK_DIV_MAX) { 153 pwm_mediatek_clk_disable(chip, pwm); 154 dev_err(chip->dev, "period of %d ns not supported\n", period_ns); 155 return -EINVAL; 156 } 157 158 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { 159 /* 160 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES 161 * from the other PWMs on MT7623. 162 */ 163 reg_width = PWM45DWIDTH_FIXUP; 164 reg_thres = PWM45THRES_FIXUP; 165 } 166 167 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); 168 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); 169 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); 170 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); 171 172 pwm_mediatek_clk_disable(chip, pwm); 173 174 return 0; 175 } 176 177 static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm) 178 { 179 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 180 u32 value; 181 int ret; 182 183 ret = pwm_mediatek_clk_enable(chip, pwm); 184 if (ret < 0) 185 return ret; 186 187 value = readl(pc->regs); 188 value |= BIT(pwm->hwpwm); 189 writel(value, pc->regs); 190 191 return 0; 192 } 193 194 static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm) 195 { 196 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 197 u32 value; 198 199 value = readl(pc->regs); 200 value &= ~BIT(pwm->hwpwm); 201 writel(value, pc->regs); 202 203 pwm_mediatek_clk_disable(chip, pwm); 204 } 205 206 static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm, 207 const struct pwm_state *state) 208 { 209 int err; 210 211 if (state->polarity != PWM_POLARITY_NORMAL) 212 return -EINVAL; 213 214 if (!state->enabled) { 215 if (pwm->state.enabled) 216 pwm_mediatek_disable(chip, pwm); 217 218 return 0; 219 } 220 221 err = pwm_mediatek_config(pwm->chip, pwm, state->duty_cycle, state->period); 222 if (err) 223 return err; 224 225 if (!pwm->state.enabled) 226 err = pwm_mediatek_enable(chip, pwm); 227 228 return err; 229 } 230 231 static const struct pwm_ops pwm_mediatek_ops = { 232 .apply = pwm_mediatek_apply, 233 .owner = THIS_MODULE, 234 }; 235 236 static int pwm_mediatek_probe(struct platform_device *pdev) 237 { 238 struct pwm_mediatek_chip *pc; 239 unsigned int i; 240 int ret; 241 242 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 243 if (!pc) 244 return -ENOMEM; 245 246 pc->soc = of_device_get_match_data(&pdev->dev); 247 248 pc->regs = devm_platform_ioremap_resource(pdev, 0); 249 if (IS_ERR(pc->regs)) 250 return PTR_ERR(pc->regs); 251 252 pc->clk_pwms = devm_kmalloc_array(&pdev->dev, pc->soc->num_pwms, 253 sizeof(*pc->clk_pwms), GFP_KERNEL); 254 if (!pc->clk_pwms) 255 return -ENOMEM; 256 257 pc->clk_top = devm_clk_get(&pdev->dev, "top"); 258 if (IS_ERR(pc->clk_top)) 259 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top), 260 "Failed to get top clock\n"); 261 262 pc->clk_main = devm_clk_get(&pdev->dev, "main"); 263 if (IS_ERR(pc->clk_main)) 264 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main), 265 "Failed to get main clock\n"); 266 267 for (i = 0; i < pc->soc->num_pwms; i++) { 268 char name[8]; 269 270 snprintf(name, sizeof(name), "pwm%d", i + 1); 271 272 pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name); 273 if (IS_ERR(pc->clk_pwms[i])) 274 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]), 275 "Failed to get %s clock\n", name); 276 } 277 278 pc->chip.dev = &pdev->dev; 279 pc->chip.ops = &pwm_mediatek_ops; 280 pc->chip.npwm = pc->soc->num_pwms; 281 282 ret = devm_pwmchip_add(&pdev->dev, &pc->chip); 283 if (ret < 0) 284 return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n"); 285 286 return 0; 287 } 288 289 static const struct pwm_mediatek_of_data mt2712_pwm_data = { 290 .num_pwms = 8, 291 .pwm45_fixup = false, 292 .has_ck_26m_sel = false, 293 .reg_offset = mtk_pwm_reg_offset_v1, 294 }; 295 296 static const struct pwm_mediatek_of_data mt6795_pwm_data = { 297 .num_pwms = 7, 298 .pwm45_fixup = false, 299 .has_ck_26m_sel = false, 300 .reg_offset = mtk_pwm_reg_offset_v1, 301 }; 302 303 static const struct pwm_mediatek_of_data mt7622_pwm_data = { 304 .num_pwms = 6, 305 .pwm45_fixup = false, 306 .has_ck_26m_sel = true, 307 .reg_offset = mtk_pwm_reg_offset_v1, 308 }; 309 310 static const struct pwm_mediatek_of_data mt7623_pwm_data = { 311 .num_pwms = 5, 312 .pwm45_fixup = true, 313 .has_ck_26m_sel = false, 314 .reg_offset = mtk_pwm_reg_offset_v1, 315 }; 316 317 static const struct pwm_mediatek_of_data mt7628_pwm_data = { 318 .num_pwms = 4, 319 .pwm45_fixup = true, 320 .has_ck_26m_sel = false, 321 .reg_offset = mtk_pwm_reg_offset_v1, 322 }; 323 324 static const struct pwm_mediatek_of_data mt7629_pwm_data = { 325 .num_pwms = 1, 326 .pwm45_fixup = false, 327 .has_ck_26m_sel = false, 328 .reg_offset = mtk_pwm_reg_offset_v1, 329 }; 330 331 static const struct pwm_mediatek_of_data mt7981_pwm_data = { 332 .num_pwms = 3, 333 .pwm45_fixup = false, 334 .has_ck_26m_sel = true, 335 .reg_offset = mtk_pwm_reg_offset_v2, 336 }; 337 338 static const struct pwm_mediatek_of_data mt7986_pwm_data = { 339 .num_pwms = 2, 340 .pwm45_fixup = false, 341 .has_ck_26m_sel = true, 342 .reg_offset = mtk_pwm_reg_offset_v1, 343 }; 344 345 static const struct pwm_mediatek_of_data mt8183_pwm_data = { 346 .num_pwms = 4, 347 .pwm45_fixup = false, 348 .has_ck_26m_sel = true, 349 .reg_offset = mtk_pwm_reg_offset_v1, 350 }; 351 352 static const struct pwm_mediatek_of_data mt8365_pwm_data = { 353 .num_pwms = 3, 354 .pwm45_fixup = false, 355 .has_ck_26m_sel = true, 356 .reg_offset = mtk_pwm_reg_offset_v1, 357 }; 358 359 static const struct pwm_mediatek_of_data mt8516_pwm_data = { 360 .num_pwms = 5, 361 .pwm45_fixup = false, 362 .has_ck_26m_sel = true, 363 .reg_offset = mtk_pwm_reg_offset_v1, 364 }; 365 366 static const struct of_device_id pwm_mediatek_of_match[] = { 367 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, 368 { .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data }, 369 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, 370 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, 371 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, 372 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, 373 { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, 374 { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, 375 { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, 376 { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, 377 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, 378 { }, 379 }; 380 MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match); 381 382 static struct platform_driver pwm_mediatek_driver = { 383 .driver = { 384 .name = "pwm-mediatek", 385 .of_match_table = pwm_mediatek_of_match, 386 }, 387 .probe = pwm_mediatek_probe, 388 }; 389 module_platform_driver(pwm_mediatek_driver); 390 391 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 392 MODULE_LICENSE("GPL v2"); 393