1 /* 2 * Intel Low Power Subsystem PWM controller driver 3 * 4 * Copyright (C) 2014, Intel Corporation 5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 6 * Author: Chew Kean Ho <kean.ho.chew@intel.com> 7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> 8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com> 9 * Author: Alan Cox <alan@linux.intel.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/time.h> 23 24 #include "pwm-lpss.h" 25 26 #define PWM 0x00000000 27 #define PWM_ENABLE BIT(31) 28 #define PWM_SW_UPDATE BIT(30) 29 #define PWM_BASE_UNIT_SHIFT 8 30 #define PWM_ON_TIME_DIV_MASK 0x000000ff 31 32 /* Size of each PWM register space if multiple */ 33 #define PWM_SIZE 0x400 34 35 #define MAX_PWMS 4 36 37 struct pwm_lpss_chip { 38 struct pwm_chip chip; 39 void __iomem *regs; 40 const struct pwm_lpss_boardinfo *info; 41 u32 saved_ctrl[MAX_PWMS]; 42 }; 43 44 static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip) 45 { 46 return container_of(chip, struct pwm_lpss_chip, chip); 47 } 48 49 static inline u32 pwm_lpss_read(const struct pwm_device *pwm) 50 { 51 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); 52 53 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); 54 } 55 56 static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value) 57 { 58 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); 59 60 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); 61 } 62 63 static int pwm_lpss_wait_for_update(struct pwm_device *pwm) 64 { 65 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); 66 const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM; 67 const unsigned int ms = 500 * USEC_PER_MSEC; 68 u32 val; 69 int err; 70 71 /* 72 * PWM Configuration register has SW_UPDATE bit that is set when a new 73 * configuration is written to the register. The bit is automatically 74 * cleared at the start of the next output cycle by the IP block. 75 * 76 * If one writes a new configuration to the register while it still has 77 * the bit enabled, PWM may freeze. That is, while one can still write 78 * to the register, it won't have an effect. Thus, we try to sleep long 79 * enough that the bit gets cleared and make sure the bit is not 80 * enabled while we update the configuration. 81 */ 82 err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms); 83 if (err) 84 dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n"); 85 86 return err; 87 } 88 89 static inline int pwm_lpss_is_updating(struct pwm_device *pwm) 90 { 91 return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0; 92 } 93 94 static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, 95 int duty_ns, int period_ns) 96 { 97 unsigned long long on_time_div; 98 unsigned long c = lpwm->info->clk_rate, base_unit_range; 99 unsigned long long base_unit, freq = NSEC_PER_SEC; 100 u32 ctrl; 101 102 do_div(freq, period_ns); 103 104 /* 105 * The equation is: 106 * base_unit = round(base_unit_range * freq / c) 107 */ 108 base_unit_range = BIT(lpwm->info->base_unit_bits) - 1; 109 freq *= base_unit_range; 110 111 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c); 112 113 on_time_div = 255ULL * duty_ns; 114 do_div(on_time_div, period_ns); 115 on_time_div = 255ULL - on_time_div; 116 117 ctrl = pwm_lpss_read(pwm); 118 ctrl &= ~PWM_ON_TIME_DIV_MASK; 119 ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT); 120 base_unit &= base_unit_range; 121 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; 122 ctrl |= on_time_div; 123 pwm_lpss_write(pwm, ctrl); 124 } 125 126 static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond) 127 { 128 if (cond) 129 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE); 130 } 131 132 static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm, 133 struct pwm_state *state) 134 { 135 struct pwm_lpss_chip *lpwm = to_lpwm(chip); 136 int ret; 137 138 if (state->enabled) { 139 if (!pwm_is_enabled(pwm)) { 140 pm_runtime_get_sync(chip->dev); 141 ret = pwm_lpss_is_updating(pwm); 142 if (ret) { 143 pm_runtime_put(chip->dev); 144 return ret; 145 } 146 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period); 147 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE); 148 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false); 149 ret = pwm_lpss_wait_for_update(pwm); 150 if (ret) { 151 pm_runtime_put(chip->dev); 152 return ret; 153 } 154 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true); 155 } else { 156 ret = pwm_lpss_is_updating(pwm); 157 if (ret) 158 return ret; 159 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period); 160 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE); 161 return pwm_lpss_wait_for_update(pwm); 162 } 163 } else if (pwm_is_enabled(pwm)) { 164 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE); 165 pm_runtime_put(chip->dev); 166 } 167 168 return 0; 169 } 170 171 static const struct pwm_ops pwm_lpss_ops = { 172 .apply = pwm_lpss_apply, 173 .owner = THIS_MODULE, 174 }; 175 176 struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r, 177 const struct pwm_lpss_boardinfo *info) 178 { 179 struct pwm_lpss_chip *lpwm; 180 unsigned long c; 181 int ret; 182 183 if (WARN_ON(info->npwm > MAX_PWMS)) 184 return ERR_PTR(-ENODEV); 185 186 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL); 187 if (!lpwm) 188 return ERR_PTR(-ENOMEM); 189 190 lpwm->regs = devm_ioremap_resource(dev, r); 191 if (IS_ERR(lpwm->regs)) 192 return ERR_CAST(lpwm->regs); 193 194 lpwm->info = info; 195 196 c = lpwm->info->clk_rate; 197 if (!c) 198 return ERR_PTR(-EINVAL); 199 200 lpwm->chip.dev = dev; 201 lpwm->chip.ops = &pwm_lpss_ops; 202 lpwm->chip.base = -1; 203 lpwm->chip.npwm = info->npwm; 204 205 ret = pwmchip_add(&lpwm->chip); 206 if (ret) { 207 dev_err(dev, "failed to add PWM chip: %d\n", ret); 208 return ERR_PTR(ret); 209 } 210 211 return lpwm; 212 } 213 EXPORT_SYMBOL_GPL(pwm_lpss_probe); 214 215 int pwm_lpss_remove(struct pwm_lpss_chip *lpwm) 216 { 217 return pwmchip_remove(&lpwm->chip); 218 } 219 EXPORT_SYMBOL_GPL(pwm_lpss_remove); 220 221 int pwm_lpss_suspend(struct device *dev) 222 { 223 struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev); 224 int i; 225 226 for (i = 0; i < lpwm->info->npwm; i++) 227 lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM); 228 229 return 0; 230 } 231 EXPORT_SYMBOL_GPL(pwm_lpss_suspend); 232 233 int pwm_lpss_resume(struct device *dev) 234 { 235 struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev); 236 int i; 237 238 for (i = 0; i < lpwm->info->npwm; i++) 239 writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM); 240 241 return 0; 242 } 243 EXPORT_SYMBOL_GPL(pwm_lpss_resume); 244 245 MODULE_DESCRIPTION("PWM driver for Intel LPSS"); 246 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 247 MODULE_LICENSE("GPL v2"); 248