1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver 4 * 5 * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com> 6 * 7 * Notes 8 * ===== 9 * NXP LPC18xx provides a State Configurable Timer (SCT) which can be configured 10 * as a Pulse Width Modulator. 11 * 12 * SCT supports 16 outputs, 16 events and 16 registers. Each event will be 13 * triggered when its related register matches the SCT counter value, and it 14 * will set or clear a selected output. 15 * 16 * One of the events is preselected to generate the period, thus the maximum 17 * number of simultaneous channels is limited to 15. Notice that period is 18 * global to all the channels, thus PWM driver will refuse setting different 19 * values to it, unless there's only one channel requested. 20 */ 21 22 #include <linux/clk.h> 23 #include <linux/err.h> 24 #include <linux/io.h> 25 #include <linux/module.h> 26 #include <linux/platform_device.h> 27 #include <linux/pwm.h> 28 29 /* LPC18xx SCT registers */ 30 #define LPC18XX_PWM_CONFIG 0x000 31 #define LPC18XX_PWM_CONFIG_UNIFY BIT(0) 32 #define LPC18XX_PWM_CONFIG_NORELOAD BIT(7) 33 34 #define LPC18XX_PWM_CTRL 0x004 35 #define LPC18XX_PWM_CTRL_HALT BIT(2) 36 #define LPC18XX_PWM_BIDIR BIT(4) 37 #define LPC18XX_PWM_PRE_SHIFT 5 38 #define LPC18XX_PWM_PRE_MASK (0xff << LPC18XX_PWM_PRE_SHIFT) 39 #define LPC18XX_PWM_PRE(x) (x << LPC18XX_PWM_PRE_SHIFT) 40 41 #define LPC18XX_PWM_LIMIT 0x008 42 43 #define LPC18XX_PWM_RES_BASE 0x058 44 #define LPC18XX_PWM_RES_SHIFT(_ch) (_ch * 2) 45 #define LPC18XX_PWM_RES(_ch, _action) (_action << LPC18XX_PWM_RES_SHIFT(_ch)) 46 #define LPC18XX_PWM_RES_MASK(_ch) (0x3 << LPC18XX_PWM_RES_SHIFT(_ch)) 47 48 #define LPC18XX_PWM_MATCH_BASE 0x100 49 #define LPC18XX_PWM_MATCH(_ch) (LPC18XX_PWM_MATCH_BASE + _ch * 4) 50 51 #define LPC18XX_PWM_MATCHREL_BASE 0x200 52 #define LPC18XX_PWM_MATCHREL(_ch) (LPC18XX_PWM_MATCHREL_BASE + _ch * 4) 53 54 #define LPC18XX_PWM_EVSTATEMSK_BASE 0x300 55 #define LPC18XX_PWM_EVSTATEMSK(_ch) (LPC18XX_PWM_EVSTATEMSK_BASE + _ch * 8) 56 #define LPC18XX_PWM_EVSTATEMSK_ALL 0xffffffff 57 58 #define LPC18XX_PWM_EVCTRL_BASE 0x304 59 #define LPC18XX_PWM_EVCTRL(_ev) (LPC18XX_PWM_EVCTRL_BASE + _ev * 8) 60 61 #define LPC18XX_PWM_EVCTRL_MATCH(_ch) _ch 62 63 #define LPC18XX_PWM_EVCTRL_COMB_SHIFT 12 64 #define LPC18XX_PWM_EVCTRL_COMB_MATCH (0x1 << LPC18XX_PWM_EVCTRL_COMB_SHIFT) 65 66 #define LPC18XX_PWM_OUTPUTSET_BASE 0x500 67 #define LPC18XX_PWM_OUTPUTSET(_ch) (LPC18XX_PWM_OUTPUTSET_BASE + _ch * 8) 68 69 #define LPC18XX_PWM_OUTPUTCL_BASE 0x504 70 #define LPC18XX_PWM_OUTPUTCL(_ch) (LPC18XX_PWM_OUTPUTCL_BASE + _ch * 8) 71 72 /* LPC18xx SCT unified counter */ 73 #define LPC18XX_PWM_TIMER_MAX 0xffffffff 74 75 /* LPC18xx SCT events */ 76 #define LPC18XX_PWM_EVENT_PERIOD 0 77 #define LPC18XX_PWM_EVENT_MAX 16 78 79 #define LPC18XX_NUM_PWMS 16 80 81 /* SCT conflict resolution */ 82 enum lpc18xx_pwm_res_action { 83 LPC18XX_PWM_RES_NONE, 84 LPC18XX_PWM_RES_SET, 85 LPC18XX_PWM_RES_CLEAR, 86 LPC18XX_PWM_RES_TOGGLE, 87 }; 88 89 struct lpc18xx_pwm_data { 90 unsigned int duty_event; 91 }; 92 93 struct lpc18xx_pwm_chip { 94 struct device *dev; 95 struct pwm_chip chip; 96 void __iomem *base; 97 struct clk *pwm_clk; 98 unsigned long clk_rate; 99 unsigned int period_ns; 100 unsigned int min_period_ns; 101 unsigned int max_period_ns; 102 unsigned int period_event; 103 unsigned long event_map; 104 struct mutex res_lock; 105 struct mutex period_lock; 106 struct lpc18xx_pwm_data channeldata[LPC18XX_NUM_PWMS]; 107 }; 108 109 static inline struct lpc18xx_pwm_chip * 110 to_lpc18xx_pwm_chip(struct pwm_chip *chip) 111 { 112 return container_of(chip, struct lpc18xx_pwm_chip, chip); 113 } 114 115 static inline void lpc18xx_pwm_writel(struct lpc18xx_pwm_chip *lpc18xx_pwm, 116 u32 reg, u32 val) 117 { 118 writel(val, lpc18xx_pwm->base + reg); 119 } 120 121 static inline u32 lpc18xx_pwm_readl(struct lpc18xx_pwm_chip *lpc18xx_pwm, 122 u32 reg) 123 { 124 return readl(lpc18xx_pwm->base + reg); 125 } 126 127 static void lpc18xx_pwm_set_conflict_res(struct lpc18xx_pwm_chip *lpc18xx_pwm, 128 struct pwm_device *pwm, 129 enum lpc18xx_pwm_res_action action) 130 { 131 u32 val; 132 133 mutex_lock(&lpc18xx_pwm->res_lock); 134 135 /* 136 * Simultaneous set and clear may happen on an output, that is the case 137 * when duty_ns == period_ns. LPC18xx SCT allows to set a conflict 138 * resolution action to be taken in such a case. 139 */ 140 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_RES_BASE); 141 val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm); 142 val |= LPC18XX_PWM_RES(pwm->hwpwm, action); 143 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_RES_BASE, val); 144 145 mutex_unlock(&lpc18xx_pwm->res_lock); 146 } 147 148 static void lpc18xx_pwm_config_period(struct pwm_chip *chip, int period_ns) 149 { 150 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); 151 u64 val; 152 153 val = (u64)period_ns * lpc18xx_pwm->clk_rate; 154 do_div(val, NSEC_PER_SEC); 155 156 lpc18xx_pwm_writel(lpc18xx_pwm, 157 LPC18XX_PWM_MATCH(lpc18xx_pwm->period_event), 158 (u32)val - 1); 159 160 lpc18xx_pwm_writel(lpc18xx_pwm, 161 LPC18XX_PWM_MATCHREL(lpc18xx_pwm->period_event), 162 (u32)val - 1); 163 } 164 165 static void lpc18xx_pwm_config_duty(struct pwm_chip *chip, 166 struct pwm_device *pwm, int duty_ns) 167 { 168 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); 169 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; 170 u64 val; 171 172 val = (u64)duty_ns * lpc18xx_pwm->clk_rate; 173 do_div(val, NSEC_PER_SEC); 174 175 lpc18xx_pwm_writel(lpc18xx_pwm, 176 LPC18XX_PWM_MATCH(lpc18xx_data->duty_event), 177 (u32)val); 178 179 lpc18xx_pwm_writel(lpc18xx_pwm, 180 LPC18XX_PWM_MATCHREL(lpc18xx_data->duty_event), 181 (u32)val); 182 } 183 184 static int lpc18xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 185 int duty_ns, int period_ns) 186 { 187 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); 188 int requested_events, i; 189 190 if (period_ns < lpc18xx_pwm->min_period_ns || 191 period_ns > lpc18xx_pwm->max_period_ns) { 192 dev_err(chip->dev, "period %d not in range\n", period_ns); 193 return -ERANGE; 194 } 195 196 mutex_lock(&lpc18xx_pwm->period_lock); 197 198 requested_events = bitmap_weight(&lpc18xx_pwm->event_map, 199 LPC18XX_PWM_EVENT_MAX); 200 201 /* 202 * The PWM supports only a single period for all PWM channels. 203 * Once the period is set, it can only be changed if no more than one 204 * channel is requested at that moment. 205 */ 206 if (requested_events > 2 && lpc18xx_pwm->period_ns != period_ns && 207 lpc18xx_pwm->period_ns) { 208 dev_err(chip->dev, "conflicting period requested for PWM %u\n", 209 pwm->hwpwm); 210 mutex_unlock(&lpc18xx_pwm->period_lock); 211 return -EBUSY; 212 } 213 214 if ((requested_events <= 2 && lpc18xx_pwm->period_ns != period_ns) || 215 !lpc18xx_pwm->period_ns) { 216 lpc18xx_pwm->period_ns = period_ns; 217 for (i = 0; i < chip->npwm; i++) 218 pwm_set_period(&chip->pwms[i], period_ns); 219 lpc18xx_pwm_config_period(chip, period_ns); 220 } 221 222 mutex_unlock(&lpc18xx_pwm->period_lock); 223 224 lpc18xx_pwm_config_duty(chip, pwm, duty_ns); 225 226 return 0; 227 } 228 229 static int lpc18xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity) 230 { 231 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); 232 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; 233 enum lpc18xx_pwm_res_action res_action; 234 unsigned int set_event, clear_event; 235 236 lpc18xx_pwm_writel(lpc18xx_pwm, 237 LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event), 238 LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_data->duty_event) | 239 LPC18XX_PWM_EVCTRL_COMB_MATCH); 240 241 lpc18xx_pwm_writel(lpc18xx_pwm, 242 LPC18XX_PWM_EVSTATEMSK(lpc18xx_data->duty_event), 243 LPC18XX_PWM_EVSTATEMSK_ALL); 244 245 if (polarity == PWM_POLARITY_NORMAL) { 246 set_event = lpc18xx_pwm->period_event; 247 clear_event = lpc18xx_data->duty_event; 248 res_action = LPC18XX_PWM_RES_SET; 249 } else { 250 set_event = lpc18xx_data->duty_event; 251 clear_event = lpc18xx_pwm->period_event; 252 res_action = LPC18XX_PWM_RES_CLEAR; 253 } 254 255 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 256 BIT(set_event)); 257 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 258 BIT(clear_event)); 259 lpc18xx_pwm_set_conflict_res(lpc18xx_pwm, pwm, res_action); 260 261 return 0; 262 } 263 264 static void lpc18xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 265 { 266 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); 267 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; 268 269 lpc18xx_pwm_writel(lpc18xx_pwm, 270 LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event), 0); 271 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0); 272 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 0); 273 } 274 275 static int lpc18xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 276 { 277 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); 278 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; 279 unsigned long event; 280 281 event = find_first_zero_bit(&lpc18xx_pwm->event_map, 282 LPC18XX_PWM_EVENT_MAX); 283 284 if (event >= LPC18XX_PWM_EVENT_MAX) { 285 dev_err(lpc18xx_pwm->dev, 286 "maximum number of simultaneous channels reached\n"); 287 return -EBUSY; 288 } 289 290 set_bit(event, &lpc18xx_pwm->event_map); 291 lpc18xx_data->duty_event = event; 292 293 return 0; 294 } 295 296 static void lpc18xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 297 { 298 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); 299 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; 300 301 clear_bit(lpc18xx_data->duty_event, &lpc18xx_pwm->event_map); 302 } 303 304 static int lpc18xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 305 const struct pwm_state *state) 306 { 307 int err; 308 bool enabled = pwm->state.enabled; 309 310 if (state->polarity != pwm->state.polarity && pwm->state.enabled) { 311 lpc18xx_pwm_disable(chip, pwm); 312 enabled = false; 313 } 314 315 if (!state->enabled) { 316 if (enabled) 317 lpc18xx_pwm_disable(chip, pwm); 318 319 return 0; 320 } 321 322 err = lpc18xx_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period); 323 if (err) 324 return err; 325 326 if (!enabled) 327 err = lpc18xx_pwm_enable(chip, pwm, state->polarity); 328 329 return err; 330 } 331 static const struct pwm_ops lpc18xx_pwm_ops = { 332 .apply = lpc18xx_pwm_apply, 333 .request = lpc18xx_pwm_request, 334 .free = lpc18xx_pwm_free, 335 .owner = THIS_MODULE, 336 }; 337 338 static const struct of_device_id lpc18xx_pwm_of_match[] = { 339 { .compatible = "nxp,lpc1850-sct-pwm" }, 340 {} 341 }; 342 MODULE_DEVICE_TABLE(of, lpc18xx_pwm_of_match); 343 344 static int lpc18xx_pwm_probe(struct platform_device *pdev) 345 { 346 struct lpc18xx_pwm_chip *lpc18xx_pwm; 347 int ret; 348 u64 val; 349 350 lpc18xx_pwm = devm_kzalloc(&pdev->dev, sizeof(*lpc18xx_pwm), 351 GFP_KERNEL); 352 if (!lpc18xx_pwm) 353 return -ENOMEM; 354 355 lpc18xx_pwm->dev = &pdev->dev; 356 357 lpc18xx_pwm->base = devm_platform_ioremap_resource(pdev, 0); 358 if (IS_ERR(lpc18xx_pwm->base)) 359 return PTR_ERR(lpc18xx_pwm->base); 360 361 lpc18xx_pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm"); 362 if (IS_ERR(lpc18xx_pwm->pwm_clk)) { 363 dev_err(&pdev->dev, "failed to get pwm clock\n"); 364 return PTR_ERR(lpc18xx_pwm->pwm_clk); 365 } 366 367 ret = clk_prepare_enable(lpc18xx_pwm->pwm_clk); 368 if (ret < 0) { 369 dev_err(&pdev->dev, "could not prepare or enable pwm clock\n"); 370 return ret; 371 } 372 373 lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk); 374 if (!lpc18xx_pwm->clk_rate) { 375 dev_err(&pdev->dev, "pwm clock has no frequency\n"); 376 ret = -EINVAL; 377 goto disable_pwmclk; 378 } 379 380 mutex_init(&lpc18xx_pwm->res_lock); 381 mutex_init(&lpc18xx_pwm->period_lock); 382 383 val = (u64)NSEC_PER_SEC * LPC18XX_PWM_TIMER_MAX; 384 do_div(val, lpc18xx_pwm->clk_rate); 385 lpc18xx_pwm->max_period_ns = val; 386 387 lpc18xx_pwm->min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, 388 lpc18xx_pwm->clk_rate); 389 390 lpc18xx_pwm->chip.dev = &pdev->dev; 391 lpc18xx_pwm->chip.ops = &lpc18xx_pwm_ops; 392 lpc18xx_pwm->chip.npwm = LPC18XX_NUM_PWMS; 393 394 /* SCT counter must be in unify (32 bit) mode */ 395 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CONFIG, 396 LPC18XX_PWM_CONFIG_UNIFY); 397 398 /* 399 * Everytime the timer counter reaches the period value, the related 400 * event will be triggered and the counter reset to 0. 401 */ 402 set_bit(LPC18XX_PWM_EVENT_PERIOD, &lpc18xx_pwm->event_map); 403 lpc18xx_pwm->period_event = LPC18XX_PWM_EVENT_PERIOD; 404 405 lpc18xx_pwm_writel(lpc18xx_pwm, 406 LPC18XX_PWM_EVSTATEMSK(lpc18xx_pwm->period_event), 407 LPC18XX_PWM_EVSTATEMSK_ALL); 408 409 val = LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_pwm->period_event) | 410 LPC18XX_PWM_EVCTRL_COMB_MATCH; 411 lpc18xx_pwm_writel(lpc18xx_pwm, 412 LPC18XX_PWM_EVCTRL(lpc18xx_pwm->period_event), val); 413 414 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_LIMIT, 415 BIT(lpc18xx_pwm->period_event)); 416 417 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL); 418 val &= ~LPC18XX_PWM_BIDIR; 419 val &= ~LPC18XX_PWM_CTRL_HALT; 420 val &= ~LPC18XX_PWM_PRE_MASK; 421 val |= LPC18XX_PWM_PRE(0); 422 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL, val); 423 424 ret = pwmchip_add(&lpc18xx_pwm->chip); 425 if (ret < 0) { 426 dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret); 427 goto disable_pwmclk; 428 } 429 430 platform_set_drvdata(pdev, lpc18xx_pwm); 431 432 return 0; 433 434 disable_pwmclk: 435 clk_disable_unprepare(lpc18xx_pwm->pwm_clk); 436 return ret; 437 } 438 439 static int lpc18xx_pwm_remove(struct platform_device *pdev) 440 { 441 struct lpc18xx_pwm_chip *lpc18xx_pwm = platform_get_drvdata(pdev); 442 u32 val; 443 444 pwmchip_remove(&lpc18xx_pwm->chip); 445 446 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL); 447 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL, 448 val | LPC18XX_PWM_CTRL_HALT); 449 450 clk_disable_unprepare(lpc18xx_pwm->pwm_clk); 451 452 return 0; 453 } 454 455 static struct platform_driver lpc18xx_pwm_driver = { 456 .driver = { 457 .name = "lpc18xx-sct-pwm", 458 .of_match_table = lpc18xx_pwm_of_match, 459 }, 460 .probe = lpc18xx_pwm_probe, 461 .remove = lpc18xx_pwm_remove, 462 }; 463 module_platform_driver(lpc18xx_pwm_driver); 464 465 MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>"); 466 MODULE_DESCRIPTION("NXP LPC18xx PWM driver"); 467 MODULE_LICENSE("GPL v2"); 468