1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * simple driver for PWM (Pulse Width Modulator) controller 4 * 5 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com> 6 * 7 * Limitations: 8 * - When disabled the output is driven to 0 independent of the configured 9 * polarity. 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bitops.h> 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 #include <linux/pwm.h> 23 #include <linux/slab.h> 24 25 #define MX3_PWMCR 0x00 /* PWM Control Register */ 26 #define MX3_PWMSR 0x04 /* PWM Status Register */ 27 #define MX3_PWMSAR 0x0C /* PWM Sample Register */ 28 #define MX3_PWMPR 0x10 /* PWM Period Register */ 29 #define MX3_PWMCNR 0x14 /* PWM Counter Register */ 30 31 #define MX3_PWMCR_FWM GENMASK(27, 26) 32 #define MX3_PWMCR_STOPEN BIT(25) 33 #define MX3_PWMCR_DOZEN BIT(24) 34 #define MX3_PWMCR_WAITEN BIT(23) 35 #define MX3_PWMCR_DBGEN BIT(22) 36 #define MX3_PWMCR_BCTR BIT(21) 37 #define MX3_PWMCR_HCTR BIT(20) 38 39 #define MX3_PWMCR_POUTC GENMASK(19, 18) 40 #define MX3_PWMCR_POUTC_NORMAL 0 41 #define MX3_PWMCR_POUTC_INVERTED 1 42 #define MX3_PWMCR_POUTC_OFF 2 43 44 #define MX3_PWMCR_CLKSRC GENMASK(17, 16) 45 #define MX3_PWMCR_CLKSRC_OFF 0 46 #define MX3_PWMCR_CLKSRC_IPG 1 47 #define MX3_PWMCR_CLKSRC_IPG_HIGH 2 48 #define MX3_PWMCR_CLKSRC_IPG_32K 3 49 50 #define MX3_PWMCR_PRESCALER GENMASK(15, 4) 51 52 #define MX3_PWMCR_SWR BIT(3) 53 54 #define MX3_PWMCR_REPEAT GENMASK(2, 1) 55 #define MX3_PWMCR_REPEAT_1X 0 56 #define MX3_PWMCR_REPEAT_2X 1 57 #define MX3_PWMCR_REPEAT_4X 2 58 #define MX3_PWMCR_REPEAT_8X 3 59 60 #define MX3_PWMCR_EN BIT(0) 61 62 #define MX3_PWMSR_FWE BIT(6) 63 #define MX3_PWMSR_CMP BIT(5) 64 #define MX3_PWMSR_ROV BIT(4) 65 #define MX3_PWMSR_FE BIT(3) 66 67 #define MX3_PWMSR_FIFOAV GENMASK(2, 0) 68 #define MX3_PWMSR_FIFOAV_EMPTY 0 69 #define MX3_PWMSR_FIFOAV_1WORD 1 70 #define MX3_PWMSR_FIFOAV_2WORDS 2 71 #define MX3_PWMSR_FIFOAV_3WORDS 3 72 #define MX3_PWMSR_FIFOAV_4WORDS 4 73 74 #define MX3_PWMCR_PRESCALER_SET(x) FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1) 75 #define MX3_PWMCR_PRESCALER_GET(x) (FIELD_GET(MX3_PWMCR_PRESCALER, \ 76 (x)) + 1) 77 78 #define MX3_PWM_SWR_LOOP 5 79 80 /* PWMPR register value of 0xffff has the same effect as 0xfffe */ 81 #define MX3_PWMPR_MAX 0xfffe 82 83 struct pwm_imx27_chip { 84 struct clk *clk_ipg; 85 struct clk *clk_per; 86 void __iomem *mmio_base; 87 struct pwm_chip chip; 88 89 /* 90 * The driver cannot read the current duty cycle from the hardware if 91 * the hardware is disabled. Cache the last programmed duty cycle 92 * value to return in that case. 93 */ 94 unsigned int duty_cycle; 95 }; 96 97 #define to_pwm_imx27_chip(chip) container_of(chip, struct pwm_imx27_chip, chip) 98 99 static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx) 100 { 101 int ret; 102 103 ret = clk_prepare_enable(imx->clk_ipg); 104 if (ret) 105 return ret; 106 107 ret = clk_prepare_enable(imx->clk_per); 108 if (ret) { 109 clk_disable_unprepare(imx->clk_ipg); 110 return ret; 111 } 112 113 return 0; 114 } 115 116 static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx) 117 { 118 clk_disable_unprepare(imx->clk_per); 119 clk_disable_unprepare(imx->clk_ipg); 120 } 121 122 static int pwm_imx27_get_state(struct pwm_chip *chip, 123 struct pwm_device *pwm, struct pwm_state *state) 124 { 125 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); 126 u32 period, prescaler, pwm_clk, val; 127 u64 tmp; 128 int ret; 129 130 ret = pwm_imx27_clk_prepare_enable(imx); 131 if (ret < 0) 132 return ret; 133 134 val = readl(imx->mmio_base + MX3_PWMCR); 135 136 if (val & MX3_PWMCR_EN) 137 state->enabled = true; 138 else 139 state->enabled = false; 140 141 switch (FIELD_GET(MX3_PWMCR_POUTC, val)) { 142 case MX3_PWMCR_POUTC_NORMAL: 143 state->polarity = PWM_POLARITY_NORMAL; 144 break; 145 case MX3_PWMCR_POUTC_INVERTED: 146 state->polarity = PWM_POLARITY_INVERSED; 147 break; 148 default: 149 dev_warn(chip->dev, "can't set polarity, output disconnected"); 150 } 151 152 prescaler = MX3_PWMCR_PRESCALER_GET(val); 153 pwm_clk = clk_get_rate(imx->clk_per); 154 val = readl(imx->mmio_base + MX3_PWMPR); 155 period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val; 156 157 /* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */ 158 tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler; 159 state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk); 160 161 /* 162 * PWMSAR can be read only if PWM is enabled. If the PWM is disabled, 163 * use the cached value. 164 */ 165 if (state->enabled) 166 val = readl(imx->mmio_base + MX3_PWMSAR); 167 else 168 val = imx->duty_cycle; 169 170 tmp = NSEC_PER_SEC * (u64)(val) * prescaler; 171 state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk); 172 173 pwm_imx27_clk_disable_unprepare(imx); 174 175 return 0; 176 } 177 178 static void pwm_imx27_sw_reset(struct pwm_chip *chip) 179 { 180 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); 181 struct device *dev = chip->dev; 182 int wait_count = 0; 183 u32 cr; 184 185 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR); 186 do { 187 usleep_range(200, 1000); 188 cr = readl(imx->mmio_base + MX3_PWMCR); 189 } while ((cr & MX3_PWMCR_SWR) && 190 (wait_count++ < MX3_PWM_SWR_LOOP)); 191 192 if (cr & MX3_PWMCR_SWR) 193 dev_warn(dev, "software reset timeout\n"); 194 } 195 196 static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip, 197 struct pwm_device *pwm) 198 { 199 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); 200 struct device *dev = chip->dev; 201 unsigned int period_ms; 202 int fifoav; 203 u32 sr; 204 205 sr = readl(imx->mmio_base + MX3_PWMSR); 206 fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr); 207 if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) { 208 period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm), 209 NSEC_PER_MSEC); 210 msleep(period_ms); 211 212 sr = readl(imx->mmio_base + MX3_PWMSR); 213 if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr)) 214 dev_warn(dev, "there is no free FIFO slot\n"); 215 } 216 } 217 218 static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm, 219 const struct pwm_state *state) 220 { 221 unsigned long period_cycles, duty_cycles, prescale, period_us, tmp; 222 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); 223 struct pwm_state cstate; 224 unsigned long long c; 225 unsigned long long clkrate; 226 unsigned long flags; 227 int val; 228 int ret; 229 u32 cr; 230 231 pwm_get_state(pwm, &cstate); 232 233 clkrate = clk_get_rate(imx->clk_per); 234 c = clkrate * state->period; 235 236 do_div(c, NSEC_PER_SEC); 237 period_cycles = c; 238 239 prescale = period_cycles / 0x10000 + 1; 240 241 period_cycles /= prescale; 242 c = clkrate * state->duty_cycle; 243 do_div(c, NSEC_PER_SEC); 244 duty_cycles = c; 245 duty_cycles /= prescale; 246 247 /* 248 * according to imx pwm RM, the real period value should be PERIOD 249 * value in PWMPR plus 2. 250 */ 251 if (period_cycles > 2) 252 period_cycles -= 2; 253 else 254 period_cycles = 0; 255 256 /* 257 * Wait for a free FIFO slot if the PWM is already enabled, and flush 258 * the FIFO if the PWM was disabled and is about to be enabled. 259 */ 260 if (cstate.enabled) { 261 pwm_imx27_wait_fifo_slot(chip, pwm); 262 } else { 263 ret = pwm_imx27_clk_prepare_enable(imx); 264 if (ret) 265 return ret; 266 267 pwm_imx27_sw_reset(chip); 268 } 269 270 val = readl(imx->mmio_base + MX3_PWMPR); 271 val = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val; 272 cr = readl(imx->mmio_base + MX3_PWMCR); 273 tmp = NSEC_PER_SEC * (u64)(val + 2) * MX3_PWMCR_PRESCALER_GET(cr); 274 tmp = DIV_ROUND_UP_ULL(tmp, clkrate); 275 period_us = DIV_ROUND_UP_ULL(tmp, 1000); 276 277 /* 278 * ERR051198: 279 * PWM: PWM output may not function correctly if the FIFO is empty when 280 * a new SAR value is programmed 281 * 282 * Description: 283 * When the PWM FIFO is empty, a new value programmed to the PWM Sample 284 * register (PWM_PWMSAR) will be directly applied even if the current 285 * timer period has not expired. 286 * 287 * If the new SAMPLE value programmed in the PWM_PWMSAR register is 288 * less than the previous value, and the PWM counter register 289 * (PWM_PWMCNR) that contains the current COUNT value is greater than 290 * the new programmed SAMPLE value, the current period will not flip 291 * the level. This may result in an output pulse with a duty cycle of 292 * 100%. 293 * 294 * Consider a change from 295 * ________ 296 * / \______/ 297 * ^ * ^ 298 * to 299 * ____ 300 * / \__________/ 301 * ^ ^ 302 * At the time marked by *, the new write value will be directly applied 303 * to SAR even the current period is not over if FIFO is empty. 304 * 305 * ________ ____________________ 306 * / \______/ \__________/ 307 * ^ ^ * ^ ^ 308 * |<-- old SAR -->| |<-- new SAR -->| 309 * 310 * That is the output is active for a whole period. 311 * 312 * Workaround: 313 * Check new SAR less than old SAR and current counter is in errata 314 * windows, write extra old SAR into FIFO and new SAR will effect at 315 * next period. 316 * 317 * Sometime period is quite long, such as over 1 second. If add old SAR 318 * into FIFO unconditional, new SAR have to wait for next period. It 319 * may be too long. 320 * 321 * Turn off the interrupt to ensure that not IRQ and schedule happen 322 * during above operations. If any irq and schedule happen, counter 323 * in PWM will be out of data and take wrong action. 324 * 325 * Add a safety margin 1.5us because it needs some time to complete 326 * IO write. 327 * 328 * Use writel_relaxed() to minimize the interval between two writes to 329 * the SAR register to increase the fastest PWM frequency supported. 330 * 331 * When the PWM period is longer than 2us(or <500kHz), this workaround 332 * can solve this problem. No software workaround is available if PWM 333 * period is shorter than IO write. Just try best to fill old data 334 * into FIFO. 335 */ 336 c = clkrate * 1500; 337 do_div(c, NSEC_PER_SEC); 338 339 local_irq_save(flags); 340 val = FIELD_GET(MX3_PWMSR_FIFOAV, readl_relaxed(imx->mmio_base + MX3_PWMSR)); 341 342 if (duty_cycles < imx->duty_cycle && (cr & MX3_PWMCR_EN)) { 343 if (period_us < 2) { /* 2us = 500 kHz */ 344 /* Best effort attempt to fix up >500 kHz case */ 345 udelay(3 * period_us); 346 writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR); 347 writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR); 348 } else if (val < MX3_PWMSR_FIFOAV_2WORDS) { 349 val = readl_relaxed(imx->mmio_base + MX3_PWMCNR); 350 /* 351 * If counter is close to period, controller may roll over when 352 * next IO write. 353 */ 354 if ((val + c >= duty_cycles && val < imx->duty_cycle) || 355 val + c >= period_cycles) 356 writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR); 357 } 358 } 359 writel_relaxed(duty_cycles, imx->mmio_base + MX3_PWMSAR); 360 local_irq_restore(flags); 361 362 writel(period_cycles, imx->mmio_base + MX3_PWMPR); 363 364 /* 365 * Store the duty cycle for future reference in cases where the 366 * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled). 367 */ 368 imx->duty_cycle = duty_cycles; 369 370 cr = MX3_PWMCR_PRESCALER_SET(prescale) | 371 MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | 372 FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) | 373 MX3_PWMCR_DBGEN; 374 375 if (state->polarity == PWM_POLARITY_INVERSED) 376 cr |= FIELD_PREP(MX3_PWMCR_POUTC, 377 MX3_PWMCR_POUTC_INVERTED); 378 379 if (state->enabled) 380 cr |= MX3_PWMCR_EN; 381 382 writel(cr, imx->mmio_base + MX3_PWMCR); 383 384 if (!state->enabled) 385 pwm_imx27_clk_disable_unprepare(imx); 386 387 return 0; 388 } 389 390 static const struct pwm_ops pwm_imx27_ops = { 391 .apply = pwm_imx27_apply, 392 .get_state = pwm_imx27_get_state, 393 .owner = THIS_MODULE, 394 }; 395 396 static const struct of_device_id pwm_imx27_dt_ids[] = { 397 { .compatible = "fsl,imx27-pwm", }, 398 { /* sentinel */ } 399 }; 400 MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids); 401 402 static int pwm_imx27_probe(struct platform_device *pdev) 403 { 404 struct pwm_imx27_chip *imx; 405 int ret; 406 u32 pwmcr; 407 408 imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL); 409 if (imx == NULL) 410 return -ENOMEM; 411 412 imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 413 if (IS_ERR(imx->clk_ipg)) 414 return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_ipg), 415 "getting ipg clock failed\n"); 416 417 imx->clk_per = devm_clk_get(&pdev->dev, "per"); 418 if (IS_ERR(imx->clk_per)) 419 return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_per), 420 "failed to get peripheral clock\n"); 421 422 imx->chip.ops = &pwm_imx27_ops; 423 imx->chip.dev = &pdev->dev; 424 imx->chip.npwm = 1; 425 426 imx->mmio_base = devm_platform_ioremap_resource(pdev, 0); 427 if (IS_ERR(imx->mmio_base)) 428 return PTR_ERR(imx->mmio_base); 429 430 ret = pwm_imx27_clk_prepare_enable(imx); 431 if (ret) 432 return ret; 433 434 /* keep clks on if pwm is running */ 435 pwmcr = readl(imx->mmio_base + MX3_PWMCR); 436 if (!(pwmcr & MX3_PWMCR_EN)) 437 pwm_imx27_clk_disable_unprepare(imx); 438 439 return devm_pwmchip_add(&pdev->dev, &imx->chip); 440 } 441 442 static struct platform_driver imx_pwm_driver = { 443 .driver = { 444 .name = "pwm-imx27", 445 .of_match_table = pwm_imx27_dt_ids, 446 }, 447 .probe = pwm_imx27_probe, 448 }; 449 module_platform_driver(imx_pwm_driver); 450 451 MODULE_LICENSE("GPL v2"); 452 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 453