1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Imagination Technologies Pulse Width Modulator driver 4 * 5 * Copyright (c) 2014-2015, Imagination Technologies 6 * 7 * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/pwm.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 23 /* PWM registers */ 24 #define PWM_CTRL_CFG 0x0000 25 #define PWM_CTRL_CFG_NO_SUB_DIV 0 26 #define PWM_CTRL_CFG_SUB_DIV0 1 27 #define PWM_CTRL_CFG_SUB_DIV1 2 28 #define PWM_CTRL_CFG_SUB_DIV0_DIV1 3 29 #define PWM_CTRL_CFG_DIV_SHIFT(ch) ((ch) * 2 + 4) 30 #define PWM_CTRL_CFG_DIV_MASK 0x3 31 32 #define PWM_CH_CFG(ch) (0x4 + (ch) * 4) 33 #define PWM_CH_CFG_TMBASE_SHIFT 0 34 #define PWM_CH_CFG_DUTY_SHIFT 16 35 36 #define PERIP_PWM_PDM_CONTROL 0x0140 37 #define PERIP_PWM_PDM_CONTROL_CH_MASK 0x1 38 #define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch) ((ch) * 4) 39 40 #define IMG_PWM_PM_TIMEOUT 1000 /* ms */ 41 42 /* 43 * PWM period is specified with a timebase register, 44 * in number of step periods. The PWM duty cycle is also 45 * specified in step periods, in the [0, $timebase] range. 46 * In other words, the timebase imposes the duty cycle 47 * resolution. Therefore, let's constraint the timebase to 48 * a minimum value to allow a sane range of duty cycle values. 49 * Imposing a minimum timebase, will impose a maximum PWM frequency. 50 * 51 * The value chosen is completely arbitrary. 52 */ 53 #define MIN_TMBASE_STEPS 16 54 55 #define IMG_PWM_NPWM 4 56 57 struct img_pwm_soc_data { 58 u32 max_timebase; 59 }; 60 61 struct img_pwm_chip { 62 struct device *dev; 63 struct pwm_chip chip; 64 struct clk *pwm_clk; 65 struct clk *sys_clk; 66 void __iomem *base; 67 struct regmap *periph_regs; 68 int max_period_ns; 69 int min_period_ns; 70 const struct img_pwm_soc_data *data; 71 u32 suspend_ctrl_cfg; 72 u32 suspend_ch_cfg[IMG_PWM_NPWM]; 73 }; 74 75 static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip) 76 { 77 return container_of(chip, struct img_pwm_chip, chip); 78 } 79 80 static inline void img_pwm_writel(struct img_pwm_chip *chip, 81 u32 reg, u32 val) 82 { 83 writel(val, chip->base + reg); 84 } 85 86 static inline u32 img_pwm_readl(struct img_pwm_chip *chip, 87 u32 reg) 88 { 89 return readl(chip->base + reg); 90 } 91 92 static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 93 int duty_ns, int period_ns) 94 { 95 u32 val, div, duty, timebase; 96 unsigned long mul, output_clk_hz, input_clk_hz; 97 struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip); 98 unsigned int max_timebase = pwm_chip->data->max_timebase; 99 int ret; 100 101 if (period_ns < pwm_chip->min_period_ns || 102 period_ns > pwm_chip->max_period_ns) { 103 dev_err(chip->dev, "configured period not in range\n"); 104 return -ERANGE; 105 } 106 107 input_clk_hz = clk_get_rate(pwm_chip->pwm_clk); 108 output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns); 109 110 mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz); 111 if (mul <= max_timebase) { 112 div = PWM_CTRL_CFG_NO_SUB_DIV; 113 timebase = DIV_ROUND_UP(mul, 1); 114 } else if (mul <= max_timebase * 8) { 115 div = PWM_CTRL_CFG_SUB_DIV0; 116 timebase = DIV_ROUND_UP(mul, 8); 117 } else if (mul <= max_timebase * 64) { 118 div = PWM_CTRL_CFG_SUB_DIV1; 119 timebase = DIV_ROUND_UP(mul, 64); 120 } else if (mul <= max_timebase * 512) { 121 div = PWM_CTRL_CFG_SUB_DIV0_DIV1; 122 timebase = DIV_ROUND_UP(mul, 512); 123 } else { 124 dev_err(chip->dev, 125 "failed to configure timebase steps/divider value\n"); 126 return -EINVAL; 127 } 128 129 duty = DIV_ROUND_UP(timebase * duty_ns, period_ns); 130 131 ret = pm_runtime_resume_and_get(chip->dev); 132 if (ret < 0) 133 return ret; 134 135 val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG); 136 val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm)); 137 val |= (div & PWM_CTRL_CFG_DIV_MASK) << 138 PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm); 139 img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val); 140 141 val = (duty << PWM_CH_CFG_DUTY_SHIFT) | 142 (timebase << PWM_CH_CFG_TMBASE_SHIFT); 143 img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val); 144 145 pm_runtime_mark_last_busy(chip->dev); 146 pm_runtime_put_autosuspend(chip->dev); 147 148 return 0; 149 } 150 151 static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 152 { 153 u32 val; 154 struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip); 155 int ret; 156 157 ret = pm_runtime_resume_and_get(chip->dev); 158 if (ret < 0) 159 return ret; 160 161 val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG); 162 val |= BIT(pwm->hwpwm); 163 img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val); 164 165 regmap_update_bits(pwm_chip->periph_regs, PERIP_PWM_PDM_CONTROL, 166 PERIP_PWM_PDM_CONTROL_CH_MASK << 167 PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0); 168 169 return 0; 170 } 171 172 static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 173 { 174 u32 val; 175 struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip); 176 177 val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG); 178 val &= ~BIT(pwm->hwpwm); 179 img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val); 180 181 pm_runtime_mark_last_busy(chip->dev); 182 pm_runtime_put_autosuspend(chip->dev); 183 } 184 185 static int img_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 186 const struct pwm_state *state) 187 { 188 int err; 189 190 if (state->polarity != PWM_POLARITY_NORMAL) 191 return -EINVAL; 192 193 if (!state->enabled) { 194 if (pwm->state.enabled) 195 img_pwm_disable(chip, pwm); 196 197 return 0; 198 } 199 200 err = img_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period); 201 if (err) 202 return err; 203 204 if (!pwm->state.enabled) 205 err = img_pwm_enable(chip, pwm); 206 207 return err; 208 } 209 210 static const struct pwm_ops img_pwm_ops = { 211 .apply = img_pwm_apply, 212 .owner = THIS_MODULE, 213 }; 214 215 static const struct img_pwm_soc_data pistachio_pwm = { 216 .max_timebase = 255, 217 }; 218 219 static const struct of_device_id img_pwm_of_match[] = { 220 { 221 .compatible = "img,pistachio-pwm", 222 .data = &pistachio_pwm, 223 }, 224 { } 225 }; 226 MODULE_DEVICE_TABLE(of, img_pwm_of_match); 227 228 static int img_pwm_runtime_suspend(struct device *dev) 229 { 230 struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev); 231 232 clk_disable_unprepare(pwm_chip->pwm_clk); 233 clk_disable_unprepare(pwm_chip->sys_clk); 234 235 return 0; 236 } 237 238 static int img_pwm_runtime_resume(struct device *dev) 239 { 240 struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev); 241 int ret; 242 243 ret = clk_prepare_enable(pwm_chip->sys_clk); 244 if (ret < 0) { 245 dev_err(dev, "could not prepare or enable sys clock\n"); 246 return ret; 247 } 248 249 ret = clk_prepare_enable(pwm_chip->pwm_clk); 250 if (ret < 0) { 251 dev_err(dev, "could not prepare or enable pwm clock\n"); 252 clk_disable_unprepare(pwm_chip->sys_clk); 253 return ret; 254 } 255 256 return 0; 257 } 258 259 static int img_pwm_probe(struct platform_device *pdev) 260 { 261 int ret; 262 u64 val; 263 unsigned long clk_rate; 264 struct img_pwm_chip *pwm; 265 const struct of_device_id *of_dev_id; 266 267 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); 268 if (!pwm) 269 return -ENOMEM; 270 271 pwm->dev = &pdev->dev; 272 273 pwm->base = devm_platform_ioremap_resource(pdev, 0); 274 if (IS_ERR(pwm->base)) 275 return PTR_ERR(pwm->base); 276 277 of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev); 278 if (!of_dev_id) 279 return -ENODEV; 280 pwm->data = of_dev_id->data; 281 282 pwm->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 283 "img,cr-periph"); 284 if (IS_ERR(pwm->periph_regs)) 285 return PTR_ERR(pwm->periph_regs); 286 287 pwm->sys_clk = devm_clk_get(&pdev->dev, "sys"); 288 if (IS_ERR(pwm->sys_clk)) { 289 dev_err(&pdev->dev, "failed to get system clock\n"); 290 return PTR_ERR(pwm->sys_clk); 291 } 292 293 pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm"); 294 if (IS_ERR(pwm->pwm_clk)) { 295 dev_err(&pdev->dev, "failed to get pwm clock\n"); 296 return PTR_ERR(pwm->pwm_clk); 297 } 298 299 platform_set_drvdata(pdev, pwm); 300 301 pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT); 302 pm_runtime_use_autosuspend(&pdev->dev); 303 pm_runtime_enable(&pdev->dev); 304 if (!pm_runtime_enabled(&pdev->dev)) { 305 ret = img_pwm_runtime_resume(&pdev->dev); 306 if (ret) 307 goto err_pm_disable; 308 } 309 310 clk_rate = clk_get_rate(pwm->pwm_clk); 311 if (!clk_rate) { 312 dev_err(&pdev->dev, "pwm clock has no frequency\n"); 313 ret = -EINVAL; 314 goto err_suspend; 315 } 316 317 /* The maximum input clock divider is 512 */ 318 val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase; 319 do_div(val, clk_rate); 320 pwm->max_period_ns = val; 321 322 val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS; 323 do_div(val, clk_rate); 324 pwm->min_period_ns = val; 325 326 pwm->chip.dev = &pdev->dev; 327 pwm->chip.ops = &img_pwm_ops; 328 pwm->chip.npwm = IMG_PWM_NPWM; 329 330 ret = pwmchip_add(&pwm->chip); 331 if (ret < 0) { 332 dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret); 333 goto err_suspend; 334 } 335 336 return 0; 337 338 err_suspend: 339 if (!pm_runtime_enabled(&pdev->dev)) 340 img_pwm_runtime_suspend(&pdev->dev); 341 err_pm_disable: 342 pm_runtime_disable(&pdev->dev); 343 pm_runtime_dont_use_autosuspend(&pdev->dev); 344 return ret; 345 } 346 347 static int img_pwm_remove(struct platform_device *pdev) 348 { 349 struct img_pwm_chip *pwm_chip = platform_get_drvdata(pdev); 350 351 pm_runtime_disable(&pdev->dev); 352 if (!pm_runtime_status_suspended(&pdev->dev)) 353 img_pwm_runtime_suspend(&pdev->dev); 354 355 pwmchip_remove(&pwm_chip->chip); 356 357 return 0; 358 } 359 360 #ifdef CONFIG_PM_SLEEP 361 static int img_pwm_suspend(struct device *dev) 362 { 363 struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev); 364 int i, ret; 365 366 if (pm_runtime_status_suspended(dev)) { 367 ret = img_pwm_runtime_resume(dev); 368 if (ret) 369 return ret; 370 } 371 372 for (i = 0; i < pwm_chip->chip.npwm; i++) 373 pwm_chip->suspend_ch_cfg[i] = img_pwm_readl(pwm_chip, 374 PWM_CH_CFG(i)); 375 376 pwm_chip->suspend_ctrl_cfg = img_pwm_readl(pwm_chip, PWM_CTRL_CFG); 377 378 img_pwm_runtime_suspend(dev); 379 380 return 0; 381 } 382 383 static int img_pwm_resume(struct device *dev) 384 { 385 struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev); 386 int ret; 387 int i; 388 389 ret = img_pwm_runtime_resume(dev); 390 if (ret) 391 return ret; 392 393 for (i = 0; i < pwm_chip->chip.npwm; i++) 394 img_pwm_writel(pwm_chip, PWM_CH_CFG(i), 395 pwm_chip->suspend_ch_cfg[i]); 396 397 img_pwm_writel(pwm_chip, PWM_CTRL_CFG, pwm_chip->suspend_ctrl_cfg); 398 399 for (i = 0; i < pwm_chip->chip.npwm; i++) 400 if (pwm_chip->suspend_ctrl_cfg & BIT(i)) 401 regmap_update_bits(pwm_chip->periph_regs, 402 PERIP_PWM_PDM_CONTROL, 403 PERIP_PWM_PDM_CONTROL_CH_MASK << 404 PERIP_PWM_PDM_CONTROL_CH_SHIFT(i), 405 0); 406 407 if (pm_runtime_status_suspended(dev)) 408 img_pwm_runtime_suspend(dev); 409 410 return 0; 411 } 412 #endif /* CONFIG_PM */ 413 414 static const struct dev_pm_ops img_pwm_pm_ops = { 415 SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend, 416 img_pwm_runtime_resume, 417 NULL) 418 SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume) 419 }; 420 421 static struct platform_driver img_pwm_driver = { 422 .driver = { 423 .name = "img-pwm", 424 .pm = &img_pwm_pm_ops, 425 .of_match_table = img_pwm_of_match, 426 }, 427 .probe = img_pwm_probe, 428 .remove = img_pwm_remove, 429 }; 430 module_platform_driver(img_pwm_driver); 431 432 MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>"); 433 MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver"); 434 MODULE_LICENSE("GPL v2"); 435