1d09f0081Syuanjian /* 2d09f0081Syuanjian * PWM Controller Driver for HiSilicon BVT SoCs 3d09f0081Syuanjian * 4d09f0081Syuanjian * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 5d09f0081Syuanjian * 6d09f0081Syuanjian * This program is free software; you can redistribute it and/or modify 7d09f0081Syuanjian * it under the terms of the GNU General Public License as published by 8d09f0081Syuanjian * the Free Software Foundation; either version 2 of the License, or 9d09f0081Syuanjian * (at your option) any later version. 10d09f0081Syuanjian * 11d09f0081Syuanjian * This program is distributed in the hope that it will be useful, 12d09f0081Syuanjian * but WITHOUT ANY WARRANTY; without even the implied warranty of 13d09f0081Syuanjian * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14d09f0081Syuanjian * GNU General Public License for more details. 15d09f0081Syuanjian * 16d09f0081Syuanjian * You should have received a copy of the GNU General Public License 17d09f0081Syuanjian * along with this program. If not, see <http://www.gnu.org/licenses/>. 18d09f0081Syuanjian */ 19d09f0081Syuanjian 20d09f0081Syuanjian #include <linux/bitops.h> 21d09f0081Syuanjian #include <linux/clk.h> 22d09f0081Syuanjian #include <linux/delay.h> 23d09f0081Syuanjian #include <linux/io.h> 24d09f0081Syuanjian #include <linux/module.h> 25d09f0081Syuanjian #include <linux/of_device.h> 26d09f0081Syuanjian #include <linux/platform_device.h> 27d09f0081Syuanjian #include <linux/pwm.h> 28d09f0081Syuanjian #include <linux/reset.h> 29d09f0081Syuanjian 30d09f0081Syuanjian #define PWM_CFG0_ADDR(x) (((x) * 0x20) + 0x0) 31d09f0081Syuanjian #define PWM_CFG1_ADDR(x) (((x) * 0x20) + 0x4) 32d09f0081Syuanjian #define PWM_CFG2_ADDR(x) (((x) * 0x20) + 0x8) 33d09f0081Syuanjian #define PWM_CTRL_ADDR(x) (((x) * 0x20) + 0xC) 34d09f0081Syuanjian 35d09f0081Syuanjian #define PWM_ENABLE_SHIFT 0 36d09f0081Syuanjian #define PWM_ENABLE_MASK BIT(0) 37d09f0081Syuanjian 38d09f0081Syuanjian #define PWM_POLARITY_SHIFT 1 39d09f0081Syuanjian #define PWM_POLARITY_MASK BIT(1) 40d09f0081Syuanjian 41d09f0081Syuanjian #define PWM_KEEP_SHIFT 2 42d09f0081Syuanjian #define PWM_KEEP_MASK BIT(2) 43d09f0081Syuanjian 44d09f0081Syuanjian #define PWM_PERIOD_MASK GENMASK(31, 0) 45d09f0081Syuanjian #define PWM_DUTY_MASK GENMASK(31, 0) 46d09f0081Syuanjian 47d09f0081Syuanjian struct hibvt_pwm_chip { 48d09f0081Syuanjian struct pwm_chip chip; 49d09f0081Syuanjian struct clk *clk; 50d09f0081Syuanjian void __iomem *base; 51d09f0081Syuanjian struct reset_control *rstc; 5277c3eddeSMathieu Othacehe const struct hibvt_pwm_soc *soc; 53d09f0081Syuanjian }; 54d09f0081Syuanjian 55d09f0081Syuanjian struct hibvt_pwm_soc { 56d09f0081Syuanjian u32 num_pwms; 57d09f0081Syuanjian }; 58d09f0081Syuanjian 5977c3eddeSMathieu Othacehe static const struct hibvt_pwm_soc hi3516cv300_soc_info = { 6077c3eddeSMathieu Othacehe .num_pwms = 4, 6177c3eddeSMathieu Othacehe }; 6277c3eddeSMathieu Othacehe 6377c3eddeSMathieu Othacehe static const struct hibvt_pwm_soc hi3519v100_soc_info = { 6477c3eddeSMathieu Othacehe .num_pwms = 8, 65d09f0081Syuanjian }; 66d09f0081Syuanjian 67d09f0081Syuanjian static inline struct hibvt_pwm_chip *to_hibvt_pwm_chip(struct pwm_chip *chip) 68d09f0081Syuanjian { 69d09f0081Syuanjian return container_of(chip, struct hibvt_pwm_chip, chip); 70d09f0081Syuanjian } 71d09f0081Syuanjian 72d09f0081Syuanjian static void hibvt_pwm_set_bits(void __iomem *base, u32 offset, 73d09f0081Syuanjian u32 mask, u32 data) 74d09f0081Syuanjian { 75d09f0081Syuanjian void __iomem *address = base + offset; 76d09f0081Syuanjian u32 value; 77d09f0081Syuanjian 78d09f0081Syuanjian value = readl(address); 79d09f0081Syuanjian value &= ~mask; 80d09f0081Syuanjian value |= (data & mask); 81d09f0081Syuanjian writel(value, address); 82d09f0081Syuanjian } 83d09f0081Syuanjian 84d09f0081Syuanjian static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 85d09f0081Syuanjian { 86d09f0081Syuanjian struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); 87d09f0081Syuanjian 88d09f0081Syuanjian hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), 89d09f0081Syuanjian PWM_ENABLE_MASK, 0x1); 90d09f0081Syuanjian } 91d09f0081Syuanjian 92d09f0081Syuanjian static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 93d09f0081Syuanjian { 94d09f0081Syuanjian struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); 95d09f0081Syuanjian 96d09f0081Syuanjian hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), 97d09f0081Syuanjian PWM_ENABLE_MASK, 0x0); 98d09f0081Syuanjian } 99d09f0081Syuanjian 100d09f0081Syuanjian static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 101d09f0081Syuanjian int duty_cycle_ns, int period_ns) 102d09f0081Syuanjian { 103d09f0081Syuanjian struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); 104d09f0081Syuanjian u32 freq, period, duty; 105d09f0081Syuanjian 106d09f0081Syuanjian freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000); 107d09f0081Syuanjian 108d09f0081Syuanjian period = div_u64(freq * period_ns, 1000); 109d09f0081Syuanjian duty = div_u64(period * duty_cycle_ns, period_ns); 110d09f0081Syuanjian 111d09f0081Syuanjian hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), 112d09f0081Syuanjian PWM_PERIOD_MASK, period); 113d09f0081Syuanjian 114d09f0081Syuanjian hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), 115d09f0081Syuanjian PWM_DUTY_MASK, duty); 116d09f0081Syuanjian } 117d09f0081Syuanjian 118d09f0081Syuanjian static void hibvt_pwm_set_polarity(struct pwm_chip *chip, 119d09f0081Syuanjian struct pwm_device *pwm, 120d09f0081Syuanjian enum pwm_polarity polarity) 121d09f0081Syuanjian { 122d09f0081Syuanjian struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); 123d09f0081Syuanjian 124d09f0081Syuanjian if (polarity == PWM_POLARITY_INVERSED) 125d09f0081Syuanjian hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), 126d09f0081Syuanjian PWM_POLARITY_MASK, (0x1 << PWM_POLARITY_SHIFT)); 127d09f0081Syuanjian else 128d09f0081Syuanjian hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), 129d09f0081Syuanjian PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT)); 130d09f0081Syuanjian } 131d09f0081Syuanjian 132d09f0081Syuanjian static void hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 133d09f0081Syuanjian struct pwm_state *state) 134d09f0081Syuanjian { 135d09f0081Syuanjian struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); 136d09f0081Syuanjian void __iomem *base; 137d09f0081Syuanjian u32 freq, value; 138d09f0081Syuanjian 139d09f0081Syuanjian freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000); 140d09f0081Syuanjian base = hi_pwm_chip->base; 141d09f0081Syuanjian 142d09f0081Syuanjian value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm)); 143d09f0081Syuanjian state->period = div_u64(value * 1000, freq); 144d09f0081Syuanjian 145d09f0081Syuanjian value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm)); 146d09f0081Syuanjian state->duty_cycle = div_u64(value * 1000, freq); 147d09f0081Syuanjian 148d09f0081Syuanjian value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm)); 149d09f0081Syuanjian state->enabled = (PWM_ENABLE_MASK & value); 150d09f0081Syuanjian } 151d09f0081Syuanjian 152d09f0081Syuanjian static int hibvt_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 153d09f0081Syuanjian struct pwm_state *state) 154d09f0081Syuanjian { 155d09f0081Syuanjian if (state->polarity != pwm->state.polarity) 156d09f0081Syuanjian hibvt_pwm_set_polarity(chip, pwm, state->polarity); 157d09f0081Syuanjian 158d09f0081Syuanjian if (state->period != pwm->state.period || 159d09f0081Syuanjian state->duty_cycle != pwm->state.duty_cycle) 160d09f0081Syuanjian hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period); 161d09f0081Syuanjian 162d09f0081Syuanjian if (state->enabled != pwm->state.enabled) { 163d09f0081Syuanjian if (state->enabled) 164d09f0081Syuanjian hibvt_pwm_enable(chip, pwm); 165d09f0081Syuanjian else 166d09f0081Syuanjian hibvt_pwm_disable(chip, pwm); 167d09f0081Syuanjian } 168d09f0081Syuanjian 169d09f0081Syuanjian return 0; 170d09f0081Syuanjian } 171d09f0081Syuanjian 172c034a6fdSArvind Yadav static const struct pwm_ops hibvt_pwm_ops = { 173d09f0081Syuanjian .get_state = hibvt_pwm_get_state, 174d09f0081Syuanjian .apply = hibvt_pwm_apply, 175d09f0081Syuanjian 176d09f0081Syuanjian .owner = THIS_MODULE, 177d09f0081Syuanjian }; 178d09f0081Syuanjian 179d09f0081Syuanjian static int hibvt_pwm_probe(struct platform_device *pdev) 180d09f0081Syuanjian { 181d09f0081Syuanjian const struct hibvt_pwm_soc *soc = 182d09f0081Syuanjian of_device_get_match_data(&pdev->dev); 183d09f0081Syuanjian struct hibvt_pwm_chip *pwm_chip; 184d09f0081Syuanjian struct resource *res; 185d09f0081Syuanjian int ret; 186d09f0081Syuanjian int i; 187d09f0081Syuanjian 188d09f0081Syuanjian pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL); 189d09f0081Syuanjian if (pwm_chip == NULL) 190d09f0081Syuanjian return -ENOMEM; 191d09f0081Syuanjian 192d09f0081Syuanjian pwm_chip->clk = devm_clk_get(&pdev->dev, NULL); 193d09f0081Syuanjian if (IS_ERR(pwm_chip->clk)) { 194d09f0081Syuanjian dev_err(&pdev->dev, "getting clock failed with %ld\n", 195d09f0081Syuanjian PTR_ERR(pwm_chip->clk)); 196d09f0081Syuanjian return PTR_ERR(pwm_chip->clk); 197d09f0081Syuanjian } 198d09f0081Syuanjian 199d09f0081Syuanjian pwm_chip->chip.ops = &hibvt_pwm_ops; 200d09f0081Syuanjian pwm_chip->chip.dev = &pdev->dev; 201d09f0081Syuanjian pwm_chip->chip.base = -1; 202d09f0081Syuanjian pwm_chip->chip.npwm = soc->num_pwms; 203d09f0081Syuanjian pwm_chip->chip.of_xlate = of_pwm_xlate_with_flags; 204d09f0081Syuanjian pwm_chip->chip.of_pwm_n_cells = 3; 20577c3eddeSMathieu Othacehe pwm_chip->soc = soc; 206d09f0081Syuanjian 207d09f0081Syuanjian res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 208d09f0081Syuanjian pwm_chip->base = devm_ioremap_resource(&pdev->dev, res); 209d09f0081Syuanjian if (IS_ERR(pwm_chip->base)) 210d09f0081Syuanjian return PTR_ERR(pwm_chip->base); 211d09f0081Syuanjian 212d09f0081Syuanjian ret = clk_prepare_enable(pwm_chip->clk); 213d09f0081Syuanjian if (ret < 0) 214d09f0081Syuanjian return ret; 215d09f0081Syuanjian 2160fd3b93fSPhilipp Zabel pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 217d09f0081Syuanjian if (IS_ERR(pwm_chip->rstc)) { 218d09f0081Syuanjian clk_disable_unprepare(pwm_chip->clk); 219d09f0081Syuanjian return PTR_ERR(pwm_chip->rstc); 220d09f0081Syuanjian } 221d09f0081Syuanjian 222d09f0081Syuanjian reset_control_assert(pwm_chip->rstc); 223d09f0081Syuanjian msleep(30); 224d09f0081Syuanjian reset_control_deassert(pwm_chip->rstc); 225d09f0081Syuanjian 226d09f0081Syuanjian ret = pwmchip_add(&pwm_chip->chip); 227d09f0081Syuanjian if (ret < 0) { 228d09f0081Syuanjian clk_disable_unprepare(pwm_chip->clk); 229d09f0081Syuanjian return ret; 230d09f0081Syuanjian } 231d09f0081Syuanjian 232d09f0081Syuanjian for (i = 0; i < pwm_chip->chip.npwm; i++) { 233d09f0081Syuanjian hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i), 234d09f0081Syuanjian PWM_KEEP_MASK, (0x1 << PWM_KEEP_SHIFT)); 235d09f0081Syuanjian } 236d09f0081Syuanjian 237d09f0081Syuanjian platform_set_drvdata(pdev, pwm_chip); 238d09f0081Syuanjian 239d09f0081Syuanjian return 0; 240d09f0081Syuanjian } 241d09f0081Syuanjian 242d09f0081Syuanjian static int hibvt_pwm_remove(struct platform_device *pdev) 243d09f0081Syuanjian { 244d09f0081Syuanjian struct hibvt_pwm_chip *pwm_chip; 245d09f0081Syuanjian 246d09f0081Syuanjian pwm_chip = platform_get_drvdata(pdev); 247d09f0081Syuanjian 248d09f0081Syuanjian reset_control_assert(pwm_chip->rstc); 249d09f0081Syuanjian msleep(30); 250d09f0081Syuanjian reset_control_deassert(pwm_chip->rstc); 251d09f0081Syuanjian 252d09f0081Syuanjian clk_disable_unprepare(pwm_chip->clk); 253d09f0081Syuanjian 254d09f0081Syuanjian return pwmchip_remove(&pwm_chip->chip); 255d09f0081Syuanjian } 256d09f0081Syuanjian 257d09f0081Syuanjian static const struct of_device_id hibvt_pwm_of_match[] = { 25877c3eddeSMathieu Othacehe { .compatible = "hisilicon,hi3516cv300-pwm", 25977c3eddeSMathieu Othacehe .data = &hi3516cv300_soc_info }, 26077c3eddeSMathieu Othacehe { .compatible = "hisilicon,hi3519v100-pwm", 26177c3eddeSMathieu Othacehe .data = &hi3519v100_soc_info }, 262d09f0081Syuanjian { } 263d09f0081Syuanjian }; 264d09f0081Syuanjian MODULE_DEVICE_TABLE(of, hibvt_pwm_of_match); 265d09f0081Syuanjian 266d09f0081Syuanjian static struct platform_driver hibvt_pwm_driver = { 267d09f0081Syuanjian .driver = { 268d09f0081Syuanjian .name = "hibvt-pwm", 269d09f0081Syuanjian .of_match_table = hibvt_pwm_of_match, 270d09f0081Syuanjian }, 271d09f0081Syuanjian .probe = hibvt_pwm_probe, 272d09f0081Syuanjian .remove = hibvt_pwm_remove, 273d09f0081Syuanjian }; 274d09f0081Syuanjian module_platform_driver(hibvt_pwm_driver); 275d09f0081Syuanjian 276d09f0081Syuanjian MODULE_AUTHOR("Jian Yuan"); 277d09f0081Syuanjian MODULE_DESCRIPTION("HiSilicon BVT SoCs PWM driver"); 278d09f0081Syuanjian MODULE_LICENSE("GPL"); 279