11ccea77eSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2d09f0081Syuanjian /* 3d09f0081Syuanjian * PWM Controller Driver for HiSilicon BVT SoCs 4d09f0081Syuanjian * 5d09f0081Syuanjian * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 6d09f0081Syuanjian */ 7d09f0081Syuanjian 8d09f0081Syuanjian #include <linux/bitops.h> 9d09f0081Syuanjian #include <linux/clk.h> 10d09f0081Syuanjian #include <linux/delay.h> 11d09f0081Syuanjian #include <linux/io.h> 12d09f0081Syuanjian #include <linux/module.h> 13d09f0081Syuanjian #include <linux/of_device.h> 14d09f0081Syuanjian #include <linux/platform_device.h> 15d09f0081Syuanjian #include <linux/pwm.h> 16d09f0081Syuanjian #include <linux/reset.h> 17d09f0081Syuanjian 18d09f0081Syuanjian #define PWM_CFG0_ADDR(x) (((x) * 0x20) + 0x0) 19d09f0081Syuanjian #define PWM_CFG1_ADDR(x) (((x) * 0x20) + 0x4) 20d09f0081Syuanjian #define PWM_CFG2_ADDR(x) (((x) * 0x20) + 0x8) 21d09f0081Syuanjian #define PWM_CTRL_ADDR(x) (((x) * 0x20) + 0xC) 22d09f0081Syuanjian 23d09f0081Syuanjian #define PWM_ENABLE_SHIFT 0 24d09f0081Syuanjian #define PWM_ENABLE_MASK BIT(0) 25d09f0081Syuanjian 26d09f0081Syuanjian #define PWM_POLARITY_SHIFT 1 27d09f0081Syuanjian #define PWM_POLARITY_MASK BIT(1) 28d09f0081Syuanjian 29d09f0081Syuanjian #define PWM_KEEP_SHIFT 2 30d09f0081Syuanjian #define PWM_KEEP_MASK BIT(2) 31d09f0081Syuanjian 32d09f0081Syuanjian #define PWM_PERIOD_MASK GENMASK(31, 0) 33d09f0081Syuanjian #define PWM_DUTY_MASK GENMASK(31, 0) 34d09f0081Syuanjian 35d09f0081Syuanjian struct hibvt_pwm_chip { 36d09f0081Syuanjian struct pwm_chip chip; 37d09f0081Syuanjian struct clk *clk; 38d09f0081Syuanjian void __iomem *base; 39d09f0081Syuanjian struct reset_control *rstc; 4077c3eddeSMathieu Othacehe const struct hibvt_pwm_soc *soc; 41d09f0081Syuanjian }; 42d09f0081Syuanjian 43d09f0081Syuanjian struct hibvt_pwm_soc { 44d09f0081Syuanjian u32 num_pwms; 457a58fc54SMathieu Othacehe bool quirk_force_enable; 46d09f0081Syuanjian }; 47d09f0081Syuanjian 4877c3eddeSMathieu Othacehe static const struct hibvt_pwm_soc hi3516cv300_soc_info = { 4977c3eddeSMathieu Othacehe .num_pwms = 4, 5077c3eddeSMathieu Othacehe }; 5177c3eddeSMathieu Othacehe 5277c3eddeSMathieu Othacehe static const struct hibvt_pwm_soc hi3519v100_soc_info = { 5377c3eddeSMathieu Othacehe .num_pwms = 8, 54d09f0081Syuanjian }; 55d09f0081Syuanjian 567a58fc54SMathieu Othacehe static const struct hibvt_pwm_soc hi3559v100_shub_soc_info = { 577a58fc54SMathieu Othacehe .num_pwms = 8, 587a58fc54SMathieu Othacehe .quirk_force_enable = true, 597a58fc54SMathieu Othacehe }; 607a58fc54SMathieu Othacehe 617a58fc54SMathieu Othacehe static const struct hibvt_pwm_soc hi3559v100_soc_info = { 627a58fc54SMathieu Othacehe .num_pwms = 2, 637a58fc54SMathieu Othacehe .quirk_force_enable = true, 647a58fc54SMathieu Othacehe }; 657a58fc54SMathieu Othacehe 66d09f0081Syuanjian static inline struct hibvt_pwm_chip *to_hibvt_pwm_chip(struct pwm_chip *chip) 67d09f0081Syuanjian { 68d09f0081Syuanjian return container_of(chip, struct hibvt_pwm_chip, chip); 69d09f0081Syuanjian } 70d09f0081Syuanjian 71d09f0081Syuanjian static void hibvt_pwm_set_bits(void __iomem *base, u32 offset, 72d09f0081Syuanjian u32 mask, u32 data) 73d09f0081Syuanjian { 74d09f0081Syuanjian void __iomem *address = base + offset; 75d09f0081Syuanjian u32 value; 76d09f0081Syuanjian 77d09f0081Syuanjian value = readl(address); 78d09f0081Syuanjian value &= ~mask; 79d09f0081Syuanjian value |= (data & mask); 80d09f0081Syuanjian writel(value, address); 81d09f0081Syuanjian } 82d09f0081Syuanjian 83d09f0081Syuanjian static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 84d09f0081Syuanjian { 85d09f0081Syuanjian struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); 86d09f0081Syuanjian 87d09f0081Syuanjian hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), 88d09f0081Syuanjian PWM_ENABLE_MASK, 0x1); 89d09f0081Syuanjian } 90d09f0081Syuanjian 91d09f0081Syuanjian static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 92d09f0081Syuanjian { 93d09f0081Syuanjian struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); 94d09f0081Syuanjian 95d09f0081Syuanjian hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), 96d09f0081Syuanjian PWM_ENABLE_MASK, 0x0); 97d09f0081Syuanjian } 98d09f0081Syuanjian 99d09f0081Syuanjian static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 100d09f0081Syuanjian int duty_cycle_ns, int period_ns) 101d09f0081Syuanjian { 102d09f0081Syuanjian struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); 103d09f0081Syuanjian u32 freq, period, duty; 104d09f0081Syuanjian 105d09f0081Syuanjian freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000); 106d09f0081Syuanjian 107d09f0081Syuanjian period = div_u64(freq * period_ns, 1000); 108d09f0081Syuanjian duty = div_u64(period * duty_cycle_ns, period_ns); 109d09f0081Syuanjian 110d09f0081Syuanjian hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), 111d09f0081Syuanjian PWM_PERIOD_MASK, period); 112d09f0081Syuanjian 113d09f0081Syuanjian hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), 114d09f0081Syuanjian PWM_DUTY_MASK, duty); 115d09f0081Syuanjian } 116d09f0081Syuanjian 117d09f0081Syuanjian static void hibvt_pwm_set_polarity(struct pwm_chip *chip, 118d09f0081Syuanjian struct pwm_device *pwm, 119d09f0081Syuanjian enum pwm_polarity polarity) 120d09f0081Syuanjian { 121d09f0081Syuanjian struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); 122d09f0081Syuanjian 123d09f0081Syuanjian if (polarity == PWM_POLARITY_INVERSED) 124d09f0081Syuanjian hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), 125d09f0081Syuanjian PWM_POLARITY_MASK, (0x1 << PWM_POLARITY_SHIFT)); 126d09f0081Syuanjian else 127d09f0081Syuanjian hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), 128d09f0081Syuanjian PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT)); 129d09f0081Syuanjian } 130d09f0081Syuanjian 131d09f0081Syuanjian static void hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 132d09f0081Syuanjian struct pwm_state *state) 133d09f0081Syuanjian { 134d09f0081Syuanjian struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); 135d09f0081Syuanjian void __iomem *base; 136d09f0081Syuanjian u32 freq, value; 137d09f0081Syuanjian 138d09f0081Syuanjian freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000); 139d09f0081Syuanjian base = hi_pwm_chip->base; 140d09f0081Syuanjian 141d09f0081Syuanjian value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm)); 142d09f0081Syuanjian state->period = div_u64(value * 1000, freq); 143d09f0081Syuanjian 144d09f0081Syuanjian value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm)); 145d09f0081Syuanjian state->duty_cycle = div_u64(value * 1000, freq); 146d09f0081Syuanjian 147d09f0081Syuanjian value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm)); 148d09f0081Syuanjian state->enabled = (PWM_ENABLE_MASK & value); 149d09f0081Syuanjian } 150d09f0081Syuanjian 151d09f0081Syuanjian static int hibvt_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 15271523d18SUwe Kleine-König const struct pwm_state *state) 153d09f0081Syuanjian { 1547a58fc54SMathieu Othacehe struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip); 1557a58fc54SMathieu Othacehe 156d09f0081Syuanjian if (state->polarity != pwm->state.polarity) 157d09f0081Syuanjian hibvt_pwm_set_polarity(chip, pwm, state->polarity); 158d09f0081Syuanjian 159d09f0081Syuanjian if (state->period != pwm->state.period || 1607a58fc54SMathieu Othacehe state->duty_cycle != pwm->state.duty_cycle) { 161d09f0081Syuanjian hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period); 162d09f0081Syuanjian 1637a58fc54SMathieu Othacehe /* 1647a58fc54SMathieu Othacehe * Some implementations require the PWM to be enabled twice 1657a58fc54SMathieu Othacehe * each time the duty cycle is refreshed. 1667a58fc54SMathieu Othacehe */ 1677a58fc54SMathieu Othacehe if (hi_pwm_chip->soc->quirk_force_enable && state->enabled) 1687a58fc54SMathieu Othacehe hibvt_pwm_enable(chip, pwm); 1697a58fc54SMathieu Othacehe } 1707a58fc54SMathieu Othacehe 171d09f0081Syuanjian if (state->enabled != pwm->state.enabled) { 172d09f0081Syuanjian if (state->enabled) 173d09f0081Syuanjian hibvt_pwm_enable(chip, pwm); 174d09f0081Syuanjian else 175d09f0081Syuanjian hibvt_pwm_disable(chip, pwm); 176d09f0081Syuanjian } 177d09f0081Syuanjian 178d09f0081Syuanjian return 0; 179d09f0081Syuanjian } 180d09f0081Syuanjian 181c034a6fdSArvind Yadav static const struct pwm_ops hibvt_pwm_ops = { 182d09f0081Syuanjian .get_state = hibvt_pwm_get_state, 183d09f0081Syuanjian .apply = hibvt_pwm_apply, 184d09f0081Syuanjian 185d09f0081Syuanjian .owner = THIS_MODULE, 186d09f0081Syuanjian }; 187d09f0081Syuanjian 188d09f0081Syuanjian static int hibvt_pwm_probe(struct platform_device *pdev) 189d09f0081Syuanjian { 190d09f0081Syuanjian const struct hibvt_pwm_soc *soc = 191d09f0081Syuanjian of_device_get_match_data(&pdev->dev); 192d09f0081Syuanjian struct hibvt_pwm_chip *pwm_chip; 193cecccd8dSYangtao Li int ret, i; 194d09f0081Syuanjian 195d09f0081Syuanjian pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL); 196d09f0081Syuanjian if (pwm_chip == NULL) 197d09f0081Syuanjian return -ENOMEM; 198d09f0081Syuanjian 199d09f0081Syuanjian pwm_chip->clk = devm_clk_get(&pdev->dev, NULL); 200d09f0081Syuanjian if (IS_ERR(pwm_chip->clk)) { 201d09f0081Syuanjian dev_err(&pdev->dev, "getting clock failed with %ld\n", 202d09f0081Syuanjian PTR_ERR(pwm_chip->clk)); 203d09f0081Syuanjian return PTR_ERR(pwm_chip->clk); 204d09f0081Syuanjian } 205d09f0081Syuanjian 206d09f0081Syuanjian pwm_chip->chip.ops = &hibvt_pwm_ops; 207d09f0081Syuanjian pwm_chip->chip.dev = &pdev->dev; 208d09f0081Syuanjian pwm_chip->chip.npwm = soc->num_pwms; 20977c3eddeSMathieu Othacehe pwm_chip->soc = soc; 210d09f0081Syuanjian 211cecccd8dSYangtao Li pwm_chip->base = devm_platform_ioremap_resource(pdev, 0); 212d09f0081Syuanjian if (IS_ERR(pwm_chip->base)) 213d09f0081Syuanjian return PTR_ERR(pwm_chip->base); 214d09f0081Syuanjian 215d09f0081Syuanjian ret = clk_prepare_enable(pwm_chip->clk); 216d09f0081Syuanjian if (ret < 0) 217d09f0081Syuanjian return ret; 218d09f0081Syuanjian 2190fd3b93fSPhilipp Zabel pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 220d09f0081Syuanjian if (IS_ERR(pwm_chip->rstc)) { 221d09f0081Syuanjian clk_disable_unprepare(pwm_chip->clk); 222d09f0081Syuanjian return PTR_ERR(pwm_chip->rstc); 223d09f0081Syuanjian } 224d09f0081Syuanjian 225d09f0081Syuanjian reset_control_assert(pwm_chip->rstc); 226d09f0081Syuanjian msleep(30); 227d09f0081Syuanjian reset_control_deassert(pwm_chip->rstc); 228d09f0081Syuanjian 229d09f0081Syuanjian ret = pwmchip_add(&pwm_chip->chip); 230d09f0081Syuanjian if (ret < 0) { 231d09f0081Syuanjian clk_disable_unprepare(pwm_chip->clk); 232d09f0081Syuanjian return ret; 233d09f0081Syuanjian } 234d09f0081Syuanjian 235d09f0081Syuanjian for (i = 0; i < pwm_chip->chip.npwm; i++) { 236d09f0081Syuanjian hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i), 237d09f0081Syuanjian PWM_KEEP_MASK, (0x1 << PWM_KEEP_SHIFT)); 238d09f0081Syuanjian } 239d09f0081Syuanjian 240d09f0081Syuanjian platform_set_drvdata(pdev, pwm_chip); 241d09f0081Syuanjian 242d09f0081Syuanjian return 0; 243d09f0081Syuanjian } 244d09f0081Syuanjian 245d09f0081Syuanjian static int hibvt_pwm_remove(struct platform_device *pdev) 246d09f0081Syuanjian { 247d09f0081Syuanjian struct hibvt_pwm_chip *pwm_chip; 248d09f0081Syuanjian 249d09f0081Syuanjian pwm_chip = platform_get_drvdata(pdev); 250d09f0081Syuanjian 251*04d77521SUwe Kleine-König pwmchip_remove(&pwm_chip->chip); 252*04d77521SUwe Kleine-König 253d09f0081Syuanjian reset_control_assert(pwm_chip->rstc); 254d09f0081Syuanjian msleep(30); 255d09f0081Syuanjian reset_control_deassert(pwm_chip->rstc); 256d09f0081Syuanjian 257d09f0081Syuanjian clk_disable_unprepare(pwm_chip->clk); 258d09f0081Syuanjian 259*04d77521SUwe Kleine-König return 0; 260d09f0081Syuanjian } 261d09f0081Syuanjian 262d09f0081Syuanjian static const struct of_device_id hibvt_pwm_of_match[] = { 26377c3eddeSMathieu Othacehe { .compatible = "hisilicon,hi3516cv300-pwm", 26477c3eddeSMathieu Othacehe .data = &hi3516cv300_soc_info }, 26577c3eddeSMathieu Othacehe { .compatible = "hisilicon,hi3519v100-pwm", 26677c3eddeSMathieu Othacehe .data = &hi3519v100_soc_info }, 2677a58fc54SMathieu Othacehe { .compatible = "hisilicon,hi3559v100-shub-pwm", 2687a58fc54SMathieu Othacehe .data = &hi3559v100_shub_soc_info }, 2697a58fc54SMathieu Othacehe { .compatible = "hisilicon,hi3559v100-pwm", 2707a58fc54SMathieu Othacehe .data = &hi3559v100_soc_info }, 271d09f0081Syuanjian { } 272d09f0081Syuanjian }; 273d09f0081Syuanjian MODULE_DEVICE_TABLE(of, hibvt_pwm_of_match); 274d09f0081Syuanjian 275d09f0081Syuanjian static struct platform_driver hibvt_pwm_driver = { 276d09f0081Syuanjian .driver = { 277d09f0081Syuanjian .name = "hibvt-pwm", 278d09f0081Syuanjian .of_match_table = hibvt_pwm_of_match, 279d09f0081Syuanjian }, 280d09f0081Syuanjian .probe = hibvt_pwm_probe, 281d09f0081Syuanjian .remove = hibvt_pwm_remove, 282d09f0081Syuanjian }; 283d09f0081Syuanjian module_platform_driver(hibvt_pwm_driver); 284d09f0081Syuanjian 285d09f0081Syuanjian MODULE_AUTHOR("Jian Yuan"); 286d09f0081Syuanjian MODULE_DESCRIPTION("HiSilicon BVT SoCs PWM driver"); 287d09f0081Syuanjian MODULE_LICENSE("GPL"); 288