1 /* 2 * Freescale FlexTimer Module (FTM) PWM Driver 3 * 4 * Copyright 2012-2013 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/of_address.h> 19 #include <linux/of_device.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm.h> 22 #include <linux/pwm.h> 23 #include <linux/regmap.h> 24 #include <linux/slab.h> 25 #include <linux/fsl/ftm.h> 26 27 #define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT) 28 29 enum fsl_pwm_clk { 30 FSL_PWM_CLK_SYS, 31 FSL_PWM_CLK_FIX, 32 FSL_PWM_CLK_EXT, 33 FSL_PWM_CLK_CNTEN, 34 FSL_PWM_CLK_MAX 35 }; 36 37 struct fsl_ftm_soc { 38 bool has_enable_bits; 39 }; 40 41 struct fsl_pwm_chip { 42 struct pwm_chip chip; 43 44 struct mutex lock; 45 46 unsigned int cnt_select; 47 unsigned int clk_ps; 48 49 struct regmap *regmap; 50 51 int period_ns; 52 53 struct clk *ipg_clk; 54 struct clk *clk[FSL_PWM_CLK_MAX]; 55 56 const struct fsl_ftm_soc *soc; 57 }; 58 59 static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip) 60 { 61 return container_of(chip, struct fsl_pwm_chip, chip); 62 } 63 64 static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 65 { 66 int ret; 67 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 68 69 ret = clk_prepare_enable(fpc->ipg_clk); 70 if (!ret && fpc->soc->has_enable_bits) { 71 mutex_lock(&fpc->lock); 72 regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), 73 BIT(pwm->hwpwm + 16)); 74 mutex_unlock(&fpc->lock); 75 } 76 77 return ret; 78 } 79 80 static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 81 { 82 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 83 84 if (fpc->soc->has_enable_bits) { 85 mutex_lock(&fpc->lock); 86 regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), 87 0); 88 mutex_unlock(&fpc->lock); 89 } 90 91 clk_disable_unprepare(fpc->ipg_clk); 92 } 93 94 static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc, 95 enum fsl_pwm_clk index) 96 { 97 unsigned long sys_rate, cnt_rate; 98 unsigned long long ratio; 99 100 sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]); 101 if (!sys_rate) 102 return -EINVAL; 103 104 cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]); 105 if (!cnt_rate) 106 return -EINVAL; 107 108 switch (index) { 109 case FSL_PWM_CLK_SYS: 110 fpc->clk_ps = 1; 111 break; 112 case FSL_PWM_CLK_FIX: 113 ratio = 2 * cnt_rate - 1; 114 do_div(ratio, sys_rate); 115 fpc->clk_ps = ratio; 116 break; 117 case FSL_PWM_CLK_EXT: 118 ratio = 4 * cnt_rate - 1; 119 do_div(ratio, sys_rate); 120 fpc->clk_ps = ratio; 121 break; 122 default: 123 return -EINVAL; 124 } 125 126 return 0; 127 } 128 129 static unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc, 130 unsigned long period_ns) 131 { 132 unsigned long long c, c0; 133 134 c = clk_get_rate(fpc->clk[fpc->cnt_select]); 135 c = c * period_ns; 136 do_div(c, 1000000000UL); 137 138 do { 139 c0 = c; 140 do_div(c0, (1 << fpc->clk_ps)); 141 if (c0 <= 0xFFFF) 142 return (unsigned long)c0; 143 } while (++fpc->clk_ps < 8); 144 145 return 0; 146 } 147 148 static unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc, 149 unsigned long period_ns, 150 enum fsl_pwm_clk index) 151 { 152 int ret; 153 154 ret = fsl_pwm_calculate_default_ps(fpc, index); 155 if (ret) { 156 dev_err(fpc->chip.dev, 157 "failed to calculate default prescaler: %d\n", 158 ret); 159 return 0; 160 } 161 162 return fsl_pwm_calculate_cycles(fpc, period_ns); 163 } 164 165 static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc, 166 unsigned long period_ns) 167 { 168 enum fsl_pwm_clk m0, m1; 169 unsigned long fix_rate, ext_rate, cycles; 170 171 cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, 172 FSL_PWM_CLK_SYS); 173 if (cycles) { 174 fpc->cnt_select = FSL_PWM_CLK_SYS; 175 return cycles; 176 } 177 178 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]); 179 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]); 180 181 if (fix_rate > ext_rate) { 182 m0 = FSL_PWM_CLK_FIX; 183 m1 = FSL_PWM_CLK_EXT; 184 } else { 185 m0 = FSL_PWM_CLK_EXT; 186 m1 = FSL_PWM_CLK_FIX; 187 } 188 189 cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0); 190 if (cycles) { 191 fpc->cnt_select = m0; 192 return cycles; 193 } 194 195 fpc->cnt_select = m1; 196 197 return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1); 198 } 199 200 static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc, 201 unsigned long period_ns, 202 unsigned long duty_ns) 203 { 204 unsigned long long duty; 205 u32 val; 206 207 regmap_read(fpc->regmap, FTM_MOD, &val); 208 duty = (unsigned long long)duty_ns * (val + 1); 209 do_div(duty, period_ns); 210 211 return (unsigned long)duty; 212 } 213 214 static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 215 int duty_ns, int period_ns) 216 { 217 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 218 u32 period, duty; 219 220 mutex_lock(&fpc->lock); 221 222 /* 223 * The Freescale FTM controller supports only a single period for 224 * all PWM channels, therefore incompatible changes need to be 225 * refused. 226 */ 227 if (fpc->period_ns && fpc->period_ns != period_ns) { 228 dev_err(fpc->chip.dev, 229 "conflicting period requested for PWM %u\n", 230 pwm->hwpwm); 231 mutex_unlock(&fpc->lock); 232 return -EBUSY; 233 } 234 235 if (!fpc->period_ns && duty_ns) { 236 period = fsl_pwm_calculate_period(fpc, period_ns); 237 if (!period) { 238 dev_err(fpc->chip.dev, "failed to calculate period\n"); 239 mutex_unlock(&fpc->lock); 240 return -EINVAL; 241 } 242 243 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK, 244 fpc->clk_ps); 245 regmap_write(fpc->regmap, FTM_MOD, period - 1); 246 247 fpc->period_ns = period_ns; 248 } 249 250 mutex_unlock(&fpc->lock); 251 252 duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns); 253 254 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm), 255 FTM_CSC_MSB | FTM_CSC_ELSB); 256 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty); 257 258 return 0; 259 } 260 261 static int fsl_pwm_set_polarity(struct pwm_chip *chip, 262 struct pwm_device *pwm, 263 enum pwm_polarity polarity) 264 { 265 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 266 u32 val; 267 268 regmap_read(fpc->regmap, FTM_POL, &val); 269 270 if (polarity == PWM_POLARITY_INVERSED) 271 val |= BIT(pwm->hwpwm); 272 else 273 val &= ~BIT(pwm->hwpwm); 274 275 regmap_write(fpc->regmap, FTM_POL, val); 276 277 return 0; 278 } 279 280 static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc) 281 { 282 int ret; 283 284 /* select counter clock source */ 285 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, 286 FTM_SC_CLK(fpc->cnt_select)); 287 288 ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]); 289 if (ret) 290 return ret; 291 292 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); 293 if (ret) { 294 clk_disable_unprepare(fpc->clk[fpc->cnt_select]); 295 return ret; 296 } 297 298 return 0; 299 } 300 301 static int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 302 { 303 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 304 int ret; 305 306 mutex_lock(&fpc->lock); 307 regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 0); 308 309 ret = fsl_counter_clock_enable(fpc); 310 mutex_unlock(&fpc->lock); 311 312 return ret; 313 } 314 315 static void fsl_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 316 { 317 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 318 u32 val; 319 320 mutex_lock(&fpc->lock); 321 regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 322 BIT(pwm->hwpwm)); 323 324 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); 325 clk_disable_unprepare(fpc->clk[fpc->cnt_select]); 326 327 regmap_read(fpc->regmap, FTM_OUTMASK, &val); 328 if ((val & 0xFF) == 0xFF) 329 fpc->period_ns = 0; 330 331 mutex_unlock(&fpc->lock); 332 } 333 334 static const struct pwm_ops fsl_pwm_ops = { 335 .request = fsl_pwm_request, 336 .free = fsl_pwm_free, 337 .config = fsl_pwm_config, 338 .set_polarity = fsl_pwm_set_polarity, 339 .enable = fsl_pwm_enable, 340 .disable = fsl_pwm_disable, 341 .owner = THIS_MODULE, 342 }; 343 344 static int fsl_pwm_init(struct fsl_pwm_chip *fpc) 345 { 346 int ret; 347 348 ret = clk_prepare_enable(fpc->ipg_clk); 349 if (ret) 350 return ret; 351 352 regmap_write(fpc->regmap, FTM_CNTIN, 0x00); 353 regmap_write(fpc->regmap, FTM_OUTINIT, 0x00); 354 regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF); 355 356 clk_disable_unprepare(fpc->ipg_clk); 357 358 return 0; 359 } 360 361 static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg) 362 { 363 switch (reg) { 364 case FTM_CNT: 365 return true; 366 } 367 return false; 368 } 369 370 static const struct regmap_config fsl_pwm_regmap_config = { 371 .reg_bits = 32, 372 .reg_stride = 4, 373 .val_bits = 32, 374 375 .max_register = FTM_PWMLOAD, 376 .volatile_reg = fsl_pwm_volatile_reg, 377 .cache_type = REGCACHE_FLAT, 378 }; 379 380 static int fsl_pwm_probe(struct platform_device *pdev) 381 { 382 struct fsl_pwm_chip *fpc; 383 struct resource *res; 384 void __iomem *base; 385 int ret; 386 387 fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL); 388 if (!fpc) 389 return -ENOMEM; 390 391 mutex_init(&fpc->lock); 392 393 fpc->soc = of_device_get_match_data(&pdev->dev); 394 fpc->chip.dev = &pdev->dev; 395 396 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 397 base = devm_ioremap_resource(&pdev->dev, res); 398 if (IS_ERR(base)) 399 return PTR_ERR(base); 400 401 fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base, 402 &fsl_pwm_regmap_config); 403 if (IS_ERR(fpc->regmap)) { 404 dev_err(&pdev->dev, "regmap init failed\n"); 405 return PTR_ERR(fpc->regmap); 406 } 407 408 fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys"); 409 if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) { 410 dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n"); 411 return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]); 412 } 413 414 fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix"); 415 if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX])) 416 return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]); 417 418 fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext"); 419 if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT])) 420 return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]); 421 422 fpc->clk[FSL_PWM_CLK_CNTEN] = 423 devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en"); 424 if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN])) 425 return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]); 426 427 /* 428 * ipg_clk is the interface clock for the IP. If not provided, use the 429 * ftm_sys clock as the default. 430 */ 431 fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 432 if (IS_ERR(fpc->ipg_clk)) 433 fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS]; 434 435 436 fpc->chip.ops = &fsl_pwm_ops; 437 fpc->chip.of_xlate = of_pwm_xlate_with_flags; 438 fpc->chip.of_pwm_n_cells = 3; 439 fpc->chip.base = -1; 440 fpc->chip.npwm = 8; 441 442 ret = pwmchip_add(&fpc->chip); 443 if (ret < 0) { 444 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); 445 return ret; 446 } 447 448 platform_set_drvdata(pdev, fpc); 449 450 return fsl_pwm_init(fpc); 451 } 452 453 static int fsl_pwm_remove(struct platform_device *pdev) 454 { 455 struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev); 456 457 return pwmchip_remove(&fpc->chip); 458 } 459 460 #ifdef CONFIG_PM_SLEEP 461 static int fsl_pwm_suspend(struct device *dev) 462 { 463 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev); 464 int i; 465 466 regcache_cache_only(fpc->regmap, true); 467 regcache_mark_dirty(fpc->regmap); 468 469 for (i = 0; i < fpc->chip.npwm; i++) { 470 struct pwm_device *pwm = &fpc->chip.pwms[i]; 471 472 if (!test_bit(PWMF_REQUESTED, &pwm->flags)) 473 continue; 474 475 clk_disable_unprepare(fpc->ipg_clk); 476 477 if (!pwm_is_enabled(pwm)) 478 continue; 479 480 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); 481 clk_disable_unprepare(fpc->clk[fpc->cnt_select]); 482 } 483 484 return 0; 485 } 486 487 static int fsl_pwm_resume(struct device *dev) 488 { 489 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev); 490 int i; 491 492 for (i = 0; i < fpc->chip.npwm; i++) { 493 struct pwm_device *pwm = &fpc->chip.pwms[i]; 494 495 if (!test_bit(PWMF_REQUESTED, &pwm->flags)) 496 continue; 497 498 clk_prepare_enable(fpc->ipg_clk); 499 500 if (!pwm_is_enabled(pwm)) 501 continue; 502 503 clk_prepare_enable(fpc->clk[fpc->cnt_select]); 504 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); 505 } 506 507 /* restore all registers from cache */ 508 regcache_cache_only(fpc->regmap, false); 509 regcache_sync(fpc->regmap); 510 511 return 0; 512 } 513 #endif 514 515 static const struct dev_pm_ops fsl_pwm_pm_ops = { 516 SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume) 517 }; 518 519 static const struct fsl_ftm_soc vf610_ftm_pwm = { 520 .has_enable_bits = false, 521 }; 522 523 static const struct fsl_ftm_soc imx8qm_ftm_pwm = { 524 .has_enable_bits = true, 525 }; 526 527 static const struct of_device_id fsl_pwm_dt_ids[] = { 528 { .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm }, 529 { .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm }, 530 { /* sentinel */ } 531 }; 532 MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids); 533 534 static struct platform_driver fsl_pwm_driver = { 535 .driver = { 536 .name = "fsl-ftm-pwm", 537 .of_match_table = fsl_pwm_dt_ids, 538 .pm = &fsl_pwm_pm_ops, 539 }, 540 .probe = fsl_pwm_probe, 541 .remove = fsl_pwm_remove, 542 }; 543 module_platform_driver(fsl_pwm_driver); 544 545 MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver"); 546 MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>"); 547 MODULE_ALIAS("platform:fsl-ftm-pwm"); 548 MODULE_LICENSE("GPL"); 549