1 /* 2 * Freescale FlexTimer Module (FTM) PWM Driver 3 * 4 * Copyright 2012-2013 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/of_address.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm.h> 21 #include <linux/pwm.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 25 #define FTM_SC 0x00 26 #define FTM_SC_CLK_MASK_SHIFT 3 27 #define FTM_SC_CLK_MASK (3 << FTM_SC_CLK_MASK_SHIFT) 28 #define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT) 29 #define FTM_SC_PS_MASK 0x7 30 31 #define FTM_CNT 0x04 32 #define FTM_MOD 0x08 33 34 #define FTM_CSC_BASE 0x0C 35 #define FTM_CSC_MSB BIT(5) 36 #define FTM_CSC_MSA BIT(4) 37 #define FTM_CSC_ELSB BIT(3) 38 #define FTM_CSC_ELSA BIT(2) 39 #define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8)) 40 41 #define FTM_CV_BASE 0x10 42 #define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8)) 43 44 #define FTM_CNTIN 0x4C 45 #define FTM_STATUS 0x50 46 47 #define FTM_MODE 0x54 48 #define FTM_MODE_FTMEN BIT(0) 49 #define FTM_MODE_INIT BIT(2) 50 #define FTM_MODE_PWMSYNC BIT(3) 51 52 #define FTM_SYNC 0x58 53 #define FTM_OUTINIT 0x5C 54 #define FTM_OUTMASK 0x60 55 #define FTM_COMBINE 0x64 56 #define FTM_DEADTIME 0x68 57 #define FTM_EXTTRIG 0x6C 58 #define FTM_POL 0x70 59 #define FTM_FMS 0x74 60 #define FTM_FILTER 0x78 61 #define FTM_FLTCTRL 0x7C 62 #define FTM_QDCTRL 0x80 63 #define FTM_CONF 0x84 64 #define FTM_FLTPOL 0x88 65 #define FTM_SYNCONF 0x8C 66 #define FTM_INVCTRL 0x90 67 #define FTM_SWOCTRL 0x94 68 #define FTM_PWMLOAD 0x98 69 70 enum fsl_pwm_clk { 71 FSL_PWM_CLK_SYS, 72 FSL_PWM_CLK_FIX, 73 FSL_PWM_CLK_EXT, 74 FSL_PWM_CLK_CNTEN, 75 FSL_PWM_CLK_MAX 76 }; 77 78 struct fsl_pwm_chip { 79 struct pwm_chip chip; 80 81 struct mutex lock; 82 83 unsigned int use_count; 84 unsigned int cnt_select; 85 unsigned int clk_ps; 86 87 struct regmap *regmap; 88 89 int period_ns; 90 91 struct clk *clk[FSL_PWM_CLK_MAX]; 92 }; 93 94 static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip) 95 { 96 return container_of(chip, struct fsl_pwm_chip, chip); 97 } 98 99 static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 100 { 101 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 102 103 return clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); 104 } 105 106 static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 107 { 108 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 109 110 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); 111 } 112 113 static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc, 114 enum fsl_pwm_clk index) 115 { 116 unsigned long sys_rate, cnt_rate; 117 unsigned long long ratio; 118 119 sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]); 120 if (!sys_rate) 121 return -EINVAL; 122 123 cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]); 124 if (!cnt_rate) 125 return -EINVAL; 126 127 switch (index) { 128 case FSL_PWM_CLK_SYS: 129 fpc->clk_ps = 1; 130 break; 131 case FSL_PWM_CLK_FIX: 132 ratio = 2 * cnt_rate - 1; 133 do_div(ratio, sys_rate); 134 fpc->clk_ps = ratio; 135 break; 136 case FSL_PWM_CLK_EXT: 137 ratio = 4 * cnt_rate - 1; 138 do_div(ratio, sys_rate); 139 fpc->clk_ps = ratio; 140 break; 141 default: 142 return -EINVAL; 143 } 144 145 return 0; 146 } 147 148 static unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc, 149 unsigned long period_ns) 150 { 151 unsigned long long c, c0; 152 153 c = clk_get_rate(fpc->clk[fpc->cnt_select]); 154 c = c * period_ns; 155 do_div(c, 1000000000UL); 156 157 do { 158 c0 = c; 159 do_div(c0, (1 << fpc->clk_ps)); 160 if (c0 <= 0xFFFF) 161 return (unsigned long)c0; 162 } while (++fpc->clk_ps < 8); 163 164 return 0; 165 } 166 167 static unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc, 168 unsigned long period_ns, 169 enum fsl_pwm_clk index) 170 { 171 int ret; 172 173 ret = fsl_pwm_calculate_default_ps(fpc, index); 174 if (ret) { 175 dev_err(fpc->chip.dev, 176 "failed to calculate default prescaler: %d\n", 177 ret); 178 return 0; 179 } 180 181 return fsl_pwm_calculate_cycles(fpc, period_ns); 182 } 183 184 static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc, 185 unsigned long period_ns) 186 { 187 enum fsl_pwm_clk m0, m1; 188 unsigned long fix_rate, ext_rate, cycles; 189 190 cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, 191 FSL_PWM_CLK_SYS); 192 if (cycles) { 193 fpc->cnt_select = FSL_PWM_CLK_SYS; 194 return cycles; 195 } 196 197 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]); 198 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]); 199 200 if (fix_rate > ext_rate) { 201 m0 = FSL_PWM_CLK_FIX; 202 m1 = FSL_PWM_CLK_EXT; 203 } else { 204 m0 = FSL_PWM_CLK_EXT; 205 m1 = FSL_PWM_CLK_FIX; 206 } 207 208 cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0); 209 if (cycles) { 210 fpc->cnt_select = m0; 211 return cycles; 212 } 213 214 fpc->cnt_select = m1; 215 216 return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1); 217 } 218 219 static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc, 220 unsigned long period_ns, 221 unsigned long duty_ns) 222 { 223 unsigned long long duty; 224 u32 val; 225 226 regmap_read(fpc->regmap, FTM_MOD, &val); 227 duty = (unsigned long long)duty_ns * (val + 1); 228 do_div(duty, period_ns); 229 230 return (unsigned long)duty; 231 } 232 233 static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 234 int duty_ns, int period_ns) 235 { 236 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 237 u32 period, duty; 238 239 mutex_lock(&fpc->lock); 240 241 /* 242 * The Freescale FTM controller supports only a single period for 243 * all PWM channels, therefore incompatible changes need to be 244 * refused. 245 */ 246 if (fpc->period_ns && fpc->period_ns != period_ns) { 247 dev_err(fpc->chip.dev, 248 "conflicting period requested for PWM %u\n", 249 pwm->hwpwm); 250 mutex_unlock(&fpc->lock); 251 return -EBUSY; 252 } 253 254 if (!fpc->period_ns && duty_ns) { 255 period = fsl_pwm_calculate_period(fpc, period_ns); 256 if (!period) { 257 dev_err(fpc->chip.dev, "failed to calculate period\n"); 258 mutex_unlock(&fpc->lock); 259 return -EINVAL; 260 } 261 262 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK, 263 fpc->clk_ps); 264 regmap_write(fpc->regmap, FTM_MOD, period - 1); 265 266 fpc->period_ns = period_ns; 267 } 268 269 mutex_unlock(&fpc->lock); 270 271 duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns); 272 273 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm), 274 FTM_CSC_MSB | FTM_CSC_ELSB); 275 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty); 276 277 return 0; 278 } 279 280 static int fsl_pwm_set_polarity(struct pwm_chip *chip, 281 struct pwm_device *pwm, 282 enum pwm_polarity polarity) 283 { 284 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 285 u32 val; 286 287 regmap_read(fpc->regmap, FTM_POL, &val); 288 289 if (polarity == PWM_POLARITY_INVERSED) 290 val |= BIT(pwm->hwpwm); 291 else 292 val &= ~BIT(pwm->hwpwm); 293 294 regmap_write(fpc->regmap, FTM_POL, val); 295 296 return 0; 297 } 298 299 static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc) 300 { 301 int ret; 302 303 if (fpc->use_count++ != 0) 304 return 0; 305 306 /* select counter clock source */ 307 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, 308 FTM_SC_CLK(fpc->cnt_select)); 309 310 ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]); 311 if (ret) 312 return ret; 313 314 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); 315 if (ret) { 316 clk_disable_unprepare(fpc->clk[fpc->cnt_select]); 317 return ret; 318 } 319 320 return 0; 321 } 322 323 static int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 324 { 325 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 326 int ret; 327 328 mutex_lock(&fpc->lock); 329 regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 0); 330 331 ret = fsl_counter_clock_enable(fpc); 332 mutex_unlock(&fpc->lock); 333 334 return ret; 335 } 336 337 static void fsl_counter_clock_disable(struct fsl_pwm_chip *fpc) 338 { 339 /* 340 * already disabled, do nothing 341 */ 342 if (fpc->use_count == 0) 343 return; 344 345 /* there are still users, so can't disable yet */ 346 if (--fpc->use_count > 0) 347 return; 348 349 /* no users left, disable PWM counter clock */ 350 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, 0); 351 352 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); 353 clk_disable_unprepare(fpc->clk[fpc->cnt_select]); 354 } 355 356 static void fsl_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 357 { 358 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 359 u32 val; 360 361 mutex_lock(&fpc->lock); 362 regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 363 BIT(pwm->hwpwm)); 364 365 fsl_counter_clock_disable(fpc); 366 367 regmap_read(fpc->regmap, FTM_OUTMASK, &val); 368 if ((val & 0xFF) == 0xFF) 369 fpc->period_ns = 0; 370 371 mutex_unlock(&fpc->lock); 372 } 373 374 static const struct pwm_ops fsl_pwm_ops = { 375 .request = fsl_pwm_request, 376 .free = fsl_pwm_free, 377 .config = fsl_pwm_config, 378 .set_polarity = fsl_pwm_set_polarity, 379 .enable = fsl_pwm_enable, 380 .disable = fsl_pwm_disable, 381 .owner = THIS_MODULE, 382 }; 383 384 static int fsl_pwm_init(struct fsl_pwm_chip *fpc) 385 { 386 int ret; 387 388 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); 389 if (ret) 390 return ret; 391 392 regmap_write(fpc->regmap, FTM_CNTIN, 0x00); 393 regmap_write(fpc->regmap, FTM_OUTINIT, 0x00); 394 regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF); 395 396 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); 397 398 return 0; 399 } 400 401 static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg) 402 { 403 switch (reg) { 404 case FTM_CNT: 405 return true; 406 } 407 return false; 408 } 409 410 static const struct regmap_config fsl_pwm_regmap_config = { 411 .reg_bits = 32, 412 .reg_stride = 4, 413 .val_bits = 32, 414 415 .max_register = FTM_PWMLOAD, 416 .volatile_reg = fsl_pwm_volatile_reg, 417 .cache_type = REGCACHE_RBTREE, 418 }; 419 420 static int fsl_pwm_probe(struct platform_device *pdev) 421 { 422 struct fsl_pwm_chip *fpc; 423 struct resource *res; 424 void __iomem *base; 425 int ret; 426 427 fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL); 428 if (!fpc) 429 return -ENOMEM; 430 431 mutex_init(&fpc->lock); 432 433 fpc->chip.dev = &pdev->dev; 434 435 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 436 base = devm_ioremap_resource(&pdev->dev, res); 437 if (IS_ERR(base)) 438 return PTR_ERR(base); 439 440 fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base, 441 &fsl_pwm_regmap_config); 442 if (IS_ERR(fpc->regmap)) { 443 dev_err(&pdev->dev, "regmap init failed\n"); 444 return PTR_ERR(fpc->regmap); 445 } 446 447 fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys"); 448 if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) { 449 dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n"); 450 return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]); 451 } 452 453 fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix"); 454 if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX])) 455 return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]); 456 457 fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext"); 458 if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT])) 459 return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]); 460 461 fpc->clk[FSL_PWM_CLK_CNTEN] = 462 devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en"); 463 if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN])) 464 return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]); 465 466 fpc->chip.ops = &fsl_pwm_ops; 467 fpc->chip.of_xlate = of_pwm_xlate_with_flags; 468 fpc->chip.of_pwm_n_cells = 3; 469 fpc->chip.base = -1; 470 fpc->chip.npwm = 8; 471 fpc->chip.can_sleep = true; 472 473 ret = pwmchip_add(&fpc->chip); 474 if (ret < 0) { 475 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); 476 return ret; 477 } 478 479 platform_set_drvdata(pdev, fpc); 480 481 return fsl_pwm_init(fpc); 482 } 483 484 static int fsl_pwm_remove(struct platform_device *pdev) 485 { 486 struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev); 487 488 return pwmchip_remove(&fpc->chip); 489 } 490 491 #ifdef CONFIG_PM_SLEEP 492 static int fsl_pwm_suspend(struct device *dev) 493 { 494 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev); 495 u32 val; 496 497 regcache_cache_only(fpc->regmap, true); 498 regcache_mark_dirty(fpc->regmap); 499 500 /* read from cache */ 501 regmap_read(fpc->regmap, FTM_OUTMASK, &val); 502 if ((val & 0xFF) != 0xFF) { 503 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); 504 clk_disable_unprepare(fpc->clk[fpc->cnt_select]); 505 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); 506 } 507 508 return 0; 509 } 510 511 static int fsl_pwm_resume(struct device *dev) 512 { 513 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev); 514 u32 val; 515 516 /* read from cache */ 517 regmap_read(fpc->regmap, FTM_OUTMASK, &val); 518 if ((val & 0xFF) != 0xFF) { 519 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); 520 clk_prepare_enable(fpc->clk[fpc->cnt_select]); 521 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); 522 } 523 524 /* restore all registers from cache */ 525 regcache_cache_only(fpc->regmap, false); 526 regcache_sync(fpc->regmap); 527 528 return 0; 529 } 530 #endif 531 532 static const struct dev_pm_ops fsl_pwm_pm_ops = { 533 SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume) 534 }; 535 536 static const struct of_device_id fsl_pwm_dt_ids[] = { 537 { .compatible = "fsl,vf610-ftm-pwm", }, 538 { /* sentinel */ } 539 }; 540 MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids); 541 542 static struct platform_driver fsl_pwm_driver = { 543 .driver = { 544 .name = "fsl-ftm-pwm", 545 .of_match_table = fsl_pwm_dt_ids, 546 .pm = &fsl_pwm_pm_ops, 547 }, 548 .probe = fsl_pwm_probe, 549 .remove = fsl_pwm_remove, 550 }; 551 module_platform_driver(fsl_pwm_driver); 552 553 MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver"); 554 MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>"); 555 MODULE_ALIAS("platform:fsl-ftm-pwm"); 556 MODULE_LICENSE("GPL"); 557