1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Broadcom BCM7038 PWM driver
4 * Author: Florian Fainelli
5 *
6 * Copyright (C) 2015 Broadcom Corporation
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/clk.h>
12 #include <linux/export.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/pwm.h>
20 #include <linux/spinlock.h>
21
22 #define PWM_CTRL 0x00
23 #define CTRL_START BIT(0)
24 #define CTRL_OEB BIT(1)
25 #define CTRL_FORCE_HIGH BIT(2)
26 #define CTRL_OPENDRAIN BIT(3)
27 #define CTRL_CHAN_OFFS 4
28
29 #define PWM_CTRL2 0x04
30 #define CTRL2_OUT_SELECT BIT(0)
31
32 #define PWM_CH_SIZE 0x8
33
34 #define PWM_CWORD_MSB(ch) (0x08 + ((ch) * PWM_CH_SIZE))
35 #define PWM_CWORD_LSB(ch) (0x0c + ((ch) * PWM_CH_SIZE))
36
37 /* Number of bits for the CWORD value */
38 #define CWORD_BIT_SIZE 16
39
40 /*
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
43 */
44 #define CONST_VAR_F_MAX 32768
45 #define CONST_VAR_F_MIN 1
46
47 #define PWM_ON(ch) (0x18 + ((ch) * PWM_CH_SIZE))
48 #define PWM_ON_MIN 1
49 #define PWM_PERIOD(ch) (0x1c + ((ch) * PWM_CH_SIZE))
50 #define PWM_PERIOD_MIN 0
51
52 #define PWM_ON_PERIOD_MAX 0xff
53
54 struct brcmstb_pwm {
55 void __iomem *base;
56 struct clk *clk;
57 struct pwm_chip chip;
58 };
59
brcmstb_pwm_readl(struct brcmstb_pwm * p,unsigned int offset)60 static inline u32 brcmstb_pwm_readl(struct brcmstb_pwm *p,
61 unsigned int offset)
62 {
63 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
64 return __raw_readl(p->base + offset);
65 else
66 return readl_relaxed(p->base + offset);
67 }
68
brcmstb_pwm_writel(struct brcmstb_pwm * p,u32 value,unsigned int offset)69 static inline void brcmstb_pwm_writel(struct brcmstb_pwm *p, u32 value,
70 unsigned int offset)
71 {
72 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
73 __raw_writel(value, p->base + offset);
74 else
75 writel_relaxed(value, p->base + offset);
76 }
77
to_brcmstb_pwm(struct pwm_chip * chip)78 static inline struct brcmstb_pwm *to_brcmstb_pwm(struct pwm_chip *chip)
79 {
80 return container_of(chip, struct brcmstb_pwm, chip);
81 }
82
83 /*
84 * Fv is derived from the variable frequency output. The variable frequency
85 * output is configured using this formula:
86 *
87 * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
88 *
89 * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
90 *
91 * The period is: (period + 1) / Fv and "on" time is on / (period + 1)
92 *
93 * The PWM core framework specifies that the "duty_ns" parameter is in fact the
94 * "on" time, so this translates directly into our HW programming here.
95 */
brcmstb_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,u64 duty_ns,u64 period_ns)96 static int brcmstb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
97 u64 duty_ns, u64 period_ns)
98 {
99 struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
100 unsigned long pc, dc, cword = CONST_VAR_F_MAX;
101 unsigned int channel = pwm->hwpwm;
102 u32 value;
103
104 /*
105 * If asking for a duty_ns equal to period_ns, we need to substract
106 * the period value by 1 to make it shorter than the "on" time and
107 * produce a flat 100% duty cycle signal, and max out the "on" time
108 */
109 if (duty_ns == period_ns) {
110 dc = PWM_ON_PERIOD_MAX;
111 pc = PWM_ON_PERIOD_MAX - 1;
112 goto done;
113 }
114
115 while (1) {
116 u64 rate;
117
118 /*
119 * Calculate the base rate from base frequency and current
120 * cword
121 */
122 rate = (u64)clk_get_rate(p->clk) * (u64)cword;
123 rate >>= CWORD_BIT_SIZE;
124
125 pc = mul_u64_u64_div_u64(period_ns, rate, NSEC_PER_SEC);
126 dc = mul_u64_u64_div_u64(duty_ns + 1, rate, NSEC_PER_SEC);
127
128 /*
129 * We can be called with separate duty and period updates,
130 * so do not reject dc == 0 right away
131 */
132 if (pc == PWM_PERIOD_MIN || (dc < PWM_ON_MIN && duty_ns))
133 return -EINVAL;
134
135 /* We converged on a calculation */
136 if (pc <= PWM_ON_PERIOD_MAX && dc <= PWM_ON_PERIOD_MAX)
137 break;
138
139 /*
140 * The cword needs to be a power of 2 for the variable
141 * frequency generator to output a 50% duty cycle variable
142 * frequency which is used as input clock to the fixed
143 * frequency generator.
144 */
145 cword >>= 1;
146
147 /*
148 * Desired periods are too large, we do not have a divider
149 * for them
150 */
151 if (cword < CONST_VAR_F_MIN)
152 return -EINVAL;
153 }
154
155 done:
156 /*
157 * Configure the defined "cword" value to have the variable frequency
158 * generator output a base frequency for the constant frequency
159 * generator to derive from.
160 */
161 brcmstb_pwm_writel(p, cword >> 8, PWM_CWORD_MSB(channel));
162 brcmstb_pwm_writel(p, cword & 0xff, PWM_CWORD_LSB(channel));
163
164 /* Select constant frequency signal output */
165 value = brcmstb_pwm_readl(p, PWM_CTRL2);
166 value |= CTRL2_OUT_SELECT << (channel * CTRL_CHAN_OFFS);
167 brcmstb_pwm_writel(p, value, PWM_CTRL2);
168
169 /* Configure on and period value */
170 brcmstb_pwm_writel(p, pc, PWM_PERIOD(channel));
171 brcmstb_pwm_writel(p, dc, PWM_ON(channel));
172
173 return 0;
174 }
175
brcmstb_pwm_enable_set(struct brcmstb_pwm * p,unsigned int channel,bool enable)176 static inline void brcmstb_pwm_enable_set(struct brcmstb_pwm *p,
177 unsigned int channel, bool enable)
178 {
179 unsigned int shift = channel * CTRL_CHAN_OFFS;
180 u32 value;
181
182 value = brcmstb_pwm_readl(p, PWM_CTRL);
183
184 if (enable) {
185 value &= ~(CTRL_OEB << shift);
186 value |= (CTRL_START | CTRL_OPENDRAIN) << shift;
187 } else {
188 value &= ~((CTRL_START | CTRL_OPENDRAIN) << shift);
189 value |= CTRL_OEB << shift;
190 }
191
192 brcmstb_pwm_writel(p, value, PWM_CTRL);
193 }
194
brcmstb_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)195 static int brcmstb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
196 const struct pwm_state *state)
197 {
198 struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
199 int err;
200
201 if (state->polarity != PWM_POLARITY_NORMAL)
202 return -EINVAL;
203
204 if (!state->enabled) {
205 if (pwm->state.enabled)
206 brcmstb_pwm_enable_set(p, pwm->hwpwm, false);
207
208 return 0;
209 }
210
211 err = brcmstb_pwm_config(chip, pwm, state->duty_cycle, state->period);
212 if (err)
213 return err;
214
215 if (!pwm->state.enabled)
216 brcmstb_pwm_enable_set(p, pwm->hwpwm, true);
217
218 return 0;
219 }
220
221 static const struct pwm_ops brcmstb_pwm_ops = {
222 .apply = brcmstb_pwm_apply,
223 .owner = THIS_MODULE,
224 };
225
226 static const struct of_device_id brcmstb_pwm_of_match[] = {
227 { .compatible = "brcm,bcm7038-pwm", },
228 { /* sentinel */ }
229 };
230 MODULE_DEVICE_TABLE(of, brcmstb_pwm_of_match);
231
brcmstb_pwm_probe(struct platform_device * pdev)232 static int brcmstb_pwm_probe(struct platform_device *pdev)
233 {
234 struct brcmstb_pwm *p;
235 int ret;
236
237 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
238 if (!p)
239 return -ENOMEM;
240
241 p->clk = devm_clk_get(&pdev->dev, NULL);
242 if (IS_ERR(p->clk)) {
243 dev_err(&pdev->dev, "failed to obtain clock\n");
244 return PTR_ERR(p->clk);
245 }
246
247 ret = clk_prepare_enable(p->clk);
248 if (ret < 0) {
249 dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
250 return ret;
251 }
252
253 platform_set_drvdata(pdev, p);
254
255 p->chip.dev = &pdev->dev;
256 p->chip.ops = &brcmstb_pwm_ops;
257 p->chip.npwm = 2;
258
259 p->base = devm_platform_ioremap_resource(pdev, 0);
260 if (IS_ERR(p->base)) {
261 ret = PTR_ERR(p->base);
262 goto out_clk;
263 }
264
265 ret = pwmchip_add(&p->chip);
266 if (ret) {
267 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
268 goto out_clk;
269 }
270
271 return 0;
272
273 out_clk:
274 clk_disable_unprepare(p->clk);
275 return ret;
276 }
277
brcmstb_pwm_remove(struct platform_device * pdev)278 static void brcmstb_pwm_remove(struct platform_device *pdev)
279 {
280 struct brcmstb_pwm *p = platform_get_drvdata(pdev);
281
282 pwmchip_remove(&p->chip);
283 clk_disable_unprepare(p->clk);
284 }
285
286 #ifdef CONFIG_PM_SLEEP
brcmstb_pwm_suspend(struct device * dev)287 static int brcmstb_pwm_suspend(struct device *dev)
288 {
289 struct brcmstb_pwm *p = dev_get_drvdata(dev);
290
291 clk_disable_unprepare(p->clk);
292
293 return 0;
294 }
295
brcmstb_pwm_resume(struct device * dev)296 static int brcmstb_pwm_resume(struct device *dev)
297 {
298 struct brcmstb_pwm *p = dev_get_drvdata(dev);
299
300 clk_prepare_enable(p->clk);
301
302 return 0;
303 }
304 #endif
305
306 static SIMPLE_DEV_PM_OPS(brcmstb_pwm_pm_ops, brcmstb_pwm_suspend,
307 brcmstb_pwm_resume);
308
309 static struct platform_driver brcmstb_pwm_driver = {
310 .probe = brcmstb_pwm_probe,
311 .remove_new = brcmstb_pwm_remove,
312 .driver = {
313 .name = "pwm-brcmstb",
314 .of_match_table = brcmstb_pwm_of_match,
315 .pm = &brcmstb_pwm_pm_ops,
316 },
317 };
318 module_platform_driver(brcmstb_pwm_driver);
319
320 MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
321 MODULE_DESCRIPTION("Broadcom STB PWM driver");
322 MODULE_ALIAS("platform:pwm-brcmstb");
323 MODULE_LICENSE("GPL");
324