xref: /openbmc/linux/drivers/pwm/pwm-bcm-iproc.c (revision 7cffcade)
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2016 Broadcom
3 
4 #include <linux/clk.h>
5 #include <linux/delay.h>
6 #include <linux/err.h>
7 #include <linux/io.h>
8 #include <linux/math64.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 #include <linux/pwm.h>
13 
14 #define IPROC_PWM_CTRL_OFFSET			0x00
15 #define IPROC_PWM_CTRL_TYPE_SHIFT(ch)		(15 + (ch))
16 #define IPROC_PWM_CTRL_POLARITY_SHIFT(ch)	(8 + (ch))
17 #define IPROC_PWM_CTRL_EN_SHIFT(ch)		(ch)
18 
19 #define IPROC_PWM_PERIOD_OFFSET(ch)		(0x04 + ((ch) << 3))
20 #define IPROC_PWM_PERIOD_MIN			0x02
21 #define IPROC_PWM_PERIOD_MAX			0xffff
22 
23 #define IPROC_PWM_DUTY_CYCLE_OFFSET(ch)		(0x08 + ((ch) << 3))
24 #define IPROC_PWM_DUTY_CYCLE_MIN		0x00
25 #define IPROC_PWM_DUTY_CYCLE_MAX		0xffff
26 
27 #define IPROC_PWM_PRESCALE_OFFSET		0x24
28 #define IPROC_PWM_PRESCALE_BITS			0x06
29 #define IPROC_PWM_PRESCALE_SHIFT(ch)		((3 - (ch)) * \
30 						 IPROC_PWM_PRESCALE_BITS)
31 #define IPROC_PWM_PRESCALE_MASK(ch)		(IPROC_PWM_PRESCALE_MAX << \
32 						 IPROC_PWM_PRESCALE_SHIFT(ch))
33 #define IPROC_PWM_PRESCALE_MIN			0x00
34 #define IPROC_PWM_PRESCALE_MAX			0x3f
35 
36 struct iproc_pwmc {
37 	struct pwm_chip chip;
38 	void __iomem *base;
39 	struct clk *clk;
40 };
41 
42 static inline struct iproc_pwmc *to_iproc_pwmc(struct pwm_chip *chip)
43 {
44 	return container_of(chip, struct iproc_pwmc, chip);
45 }
46 
47 static void iproc_pwmc_enable(struct iproc_pwmc *ip, unsigned int channel)
48 {
49 	u32 value;
50 
51 	value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
52 	value |= 1 << IPROC_PWM_CTRL_EN_SHIFT(channel);
53 	writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
54 
55 	/* must be a 400 ns delay between clearing and setting enable bit */
56 	ndelay(400);
57 }
58 
59 static void iproc_pwmc_disable(struct iproc_pwmc *ip, unsigned int channel)
60 {
61 	u32 value;
62 
63 	value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
64 	value &= ~(1 << IPROC_PWM_CTRL_EN_SHIFT(channel));
65 	writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
66 
67 	/* must be a 400 ns delay between clearing and setting enable bit */
68 	ndelay(400);
69 }
70 
71 static void iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
72 				 struct pwm_state *state)
73 {
74 	struct iproc_pwmc *ip = to_iproc_pwmc(chip);
75 	u64 tmp, multi, rate;
76 	u32 value, prescale;
77 
78 	value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
79 
80 	if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm)))
81 		state->enabled = true;
82 	else
83 		state->enabled = false;
84 
85 	if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm)))
86 		state->polarity = PWM_POLARITY_NORMAL;
87 	else
88 		state->polarity = PWM_POLARITY_INVERSED;
89 
90 	rate = clk_get_rate(ip->clk);
91 	if (rate == 0) {
92 		state->period = 0;
93 		state->duty_cycle = 0;
94 		return;
95 	}
96 
97 	value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET);
98 	prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);
99 	prescale &= IPROC_PWM_PRESCALE_MAX;
100 
101 	multi = NSEC_PER_SEC * (prescale + 1);
102 
103 	value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm));
104 	tmp = (value & IPROC_PWM_PERIOD_MAX) * multi;
105 	state->period = div64_u64(tmp, rate);
106 
107 	value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));
108 	tmp = (value & IPROC_PWM_PERIOD_MAX) * multi;
109 	state->duty_cycle = div64_u64(tmp, rate);
110 }
111 
112 static int iproc_pwmc_apply(struct pwm_chip *chip, struct pwm_device *pwm,
113 			    const struct pwm_state *state)
114 {
115 	unsigned long prescale = IPROC_PWM_PRESCALE_MIN;
116 	struct iproc_pwmc *ip = to_iproc_pwmc(chip);
117 	u32 value, period, duty;
118 	u64 rate;
119 
120 	rate = clk_get_rate(ip->clk);
121 
122 	/*
123 	 * Find period count, duty count and prescale to suit duty_cycle and
124 	 * period. This is done according to formulas described below:
125 	 *
126 	 * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
127 	 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
128 	 *
129 	 * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
130 	 * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
131 	 */
132 	while (1) {
133 		u64 value, div;
134 
135 		div = NSEC_PER_SEC * (prescale + 1);
136 		value = rate * state->period;
137 		period = div64_u64(value, div);
138 		value = rate * state->duty_cycle;
139 		duty = div64_u64(value, div);
140 
141 		if (period < IPROC_PWM_PERIOD_MIN)
142 			return -EINVAL;
143 
144 		if (period <= IPROC_PWM_PERIOD_MAX &&
145 		     duty <= IPROC_PWM_DUTY_CYCLE_MAX)
146 			break;
147 
148 		/* Otherwise, increase prescale and recalculate counts */
149 		if (++prescale > IPROC_PWM_PRESCALE_MAX)
150 			return -EINVAL;
151 	}
152 
153 	iproc_pwmc_disable(ip, pwm->hwpwm);
154 
155 	/* Set prescale */
156 	value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET);
157 	value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm);
158 	value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);
159 	writel(value, ip->base + IPROC_PWM_PRESCALE_OFFSET);
160 
161 	/* set period and duty cycle */
162 	writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm));
163 	writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));
164 
165 	/* set polarity */
166 	value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
167 
168 	if (state->polarity == PWM_POLARITY_NORMAL)
169 		value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm);
170 	else
171 		value &= ~(1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm));
172 
173 	writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
174 
175 	if (state->enabled)
176 		iproc_pwmc_enable(ip, pwm->hwpwm);
177 
178 	return 0;
179 }
180 
181 static const struct pwm_ops iproc_pwm_ops = {
182 	.apply = iproc_pwmc_apply,
183 	.get_state = iproc_pwmc_get_state,
184 	.owner = THIS_MODULE,
185 };
186 
187 static int iproc_pwmc_probe(struct platform_device *pdev)
188 {
189 	struct iproc_pwmc *ip;
190 	unsigned int i;
191 	u32 value;
192 	int ret;
193 
194 	ip = devm_kzalloc(&pdev->dev, sizeof(*ip), GFP_KERNEL);
195 	if (!ip)
196 		return -ENOMEM;
197 
198 	platform_set_drvdata(pdev, ip);
199 
200 	ip->chip.dev = &pdev->dev;
201 	ip->chip.ops = &iproc_pwm_ops;
202 	ip->chip.npwm = 4;
203 
204 	ip->base = devm_platform_ioremap_resource(pdev, 0);
205 	if (IS_ERR(ip->base))
206 		return PTR_ERR(ip->base);
207 
208 	ip->clk = devm_clk_get(&pdev->dev, NULL);
209 	if (IS_ERR(ip->clk)) {
210 		dev_err(&pdev->dev, "failed to get clock: %ld\n",
211 			PTR_ERR(ip->clk));
212 		return PTR_ERR(ip->clk);
213 	}
214 
215 	ret = clk_prepare_enable(ip->clk);
216 	if (ret < 0) {
217 		dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
218 		return ret;
219 	}
220 
221 	/* Set full drive and normal polarity for all channels */
222 	value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
223 
224 	for (i = 0; i < ip->chip.npwm; i++) {
225 		value &= ~(1 << IPROC_PWM_CTRL_TYPE_SHIFT(i));
226 		value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(i);
227 	}
228 
229 	writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
230 
231 	ret = pwmchip_add(&ip->chip);
232 	if (ret < 0) {
233 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
234 		clk_disable_unprepare(ip->clk);
235 	}
236 
237 	return ret;
238 }
239 
240 static int iproc_pwmc_remove(struct platform_device *pdev)
241 {
242 	struct iproc_pwmc *ip = platform_get_drvdata(pdev);
243 
244 	pwmchip_remove(&ip->chip);
245 
246 	clk_disable_unprepare(ip->clk);
247 
248 	return 0;
249 }
250 
251 static const struct of_device_id bcm_iproc_pwmc_dt[] = {
252 	{ .compatible = "brcm,iproc-pwm" },
253 	{ },
254 };
255 MODULE_DEVICE_TABLE(of, bcm_iproc_pwmc_dt);
256 
257 static struct platform_driver iproc_pwmc_driver = {
258 	.driver = {
259 		.name = "bcm-iproc-pwm",
260 		.of_match_table = bcm_iproc_pwmc_dt,
261 	},
262 	.probe = iproc_pwmc_probe,
263 	.remove = iproc_pwmc_remove,
264 };
265 module_platform_driver(iproc_pwmc_driver);
266 
267 MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>");
268 MODULE_DESCRIPTION("Broadcom iProc PWM driver");
269 MODULE_LICENSE("GPL v2");
270