1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for Atmel Pulse Width Modulation Controller 4 * 5 * Copyright (C) 2013 Atmel Corporation 6 * Bo Shen <voice.shen@atmel.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/platform_device.h> 18 #include <linux/pwm.h> 19 #include <linux/slab.h> 20 21 /* The following is global registers for PWM controller */ 22 #define PWM_ENA 0x04 23 #define PWM_DIS 0x08 24 #define PWM_SR 0x0C 25 #define PWM_ISR 0x1C 26 /* Bit field in SR */ 27 #define PWM_SR_ALL_CH_ON 0x0F 28 29 /* The following register is PWM channel related registers */ 30 #define PWM_CH_REG_OFFSET 0x200 31 #define PWM_CH_REG_SIZE 0x20 32 33 #define PWM_CMR 0x0 34 /* Bit field in CMR */ 35 #define PWM_CMR_CPOL (1 << 9) 36 #define PWM_CMR_UPD_CDTY (1 << 10) 37 #define PWM_CMR_CPRE_MSK 0xF 38 39 /* The following registers for PWM v1 */ 40 #define PWMV1_CDTY 0x04 41 #define PWMV1_CPRD 0x08 42 #define PWMV1_CUPD 0x10 43 44 /* The following registers for PWM v2 */ 45 #define PWMV2_CDTY 0x04 46 #define PWMV2_CDTYUPD 0x08 47 #define PWMV2_CPRD 0x0C 48 #define PWMV2_CPRDUPD 0x10 49 50 struct atmel_pwm_registers { 51 u8 period; 52 u8 period_upd; 53 u8 duty; 54 u8 duty_upd; 55 }; 56 57 struct atmel_pwm_config { 58 u32 max_period; 59 u32 max_pres; 60 }; 61 62 struct atmel_pwm_data { 63 struct atmel_pwm_registers regs; 64 struct atmel_pwm_config cfg; 65 }; 66 67 struct atmel_pwm_chip { 68 struct pwm_chip chip; 69 struct clk *clk; 70 void __iomem *base; 71 const struct atmel_pwm_data *data; 72 73 unsigned int updated_pwms; 74 /* ISR is cleared when read, ensure only one thread does that */ 75 struct mutex isr_lock; 76 }; 77 78 static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip) 79 { 80 return container_of(chip, struct atmel_pwm_chip, chip); 81 } 82 83 static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip, 84 unsigned long offset) 85 { 86 return readl_relaxed(chip->base + offset); 87 } 88 89 static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip, 90 unsigned long offset, unsigned long val) 91 { 92 writel_relaxed(val, chip->base + offset); 93 } 94 95 static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip, 96 unsigned int ch, unsigned long offset) 97 { 98 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE; 99 100 return readl_relaxed(chip->base + base + offset); 101 } 102 103 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip, 104 unsigned int ch, unsigned long offset, 105 unsigned long val) 106 { 107 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE; 108 109 writel_relaxed(val, chip->base + base + offset); 110 } 111 112 static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip, 113 const struct pwm_state *state, 114 unsigned long *cprd, u32 *pres) 115 { 116 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); 117 unsigned long long cycles = state->period; 118 119 /* Calculate the period cycles and prescale value */ 120 cycles *= clk_get_rate(atmel_pwm->clk); 121 do_div(cycles, NSEC_PER_SEC); 122 123 for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1) 124 (*pres)++; 125 126 if (*pres > atmel_pwm->data->cfg.max_pres) { 127 dev_err(chip->dev, "pres exceeds the maximum value\n"); 128 return -EINVAL; 129 } 130 131 *cprd = cycles; 132 133 return 0; 134 } 135 136 static void atmel_pwm_calculate_cdty(const struct pwm_state *state, 137 unsigned long cprd, unsigned long *cdty) 138 { 139 unsigned long long cycles = state->duty_cycle; 140 141 cycles *= cprd; 142 do_div(cycles, state->period); 143 *cdty = cprd - cycles; 144 } 145 146 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm, 147 unsigned long cdty) 148 { 149 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); 150 u32 val; 151 152 if (atmel_pwm->data->regs.duty_upd == 153 atmel_pwm->data->regs.period_upd) { 154 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); 155 val &= ~PWM_CMR_UPD_CDTY; 156 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); 157 } 158 159 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, 160 atmel_pwm->data->regs.duty_upd, cdty); 161 } 162 163 static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip, 164 struct pwm_device *pwm, 165 unsigned long cprd, unsigned long cdty) 166 { 167 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); 168 169 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, 170 atmel_pwm->data->regs.duty, cdty); 171 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, 172 atmel_pwm->data->regs.period, cprd); 173 } 174 175 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm, 176 bool disable_clk) 177 { 178 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); 179 unsigned long timeout = jiffies + 2 * HZ; 180 181 /* 182 * Wait for at least a complete period to have passed before disabling a 183 * channel to be sure that CDTY has been updated 184 */ 185 mutex_lock(&atmel_pwm->isr_lock); 186 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR); 187 188 while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) && 189 time_before(jiffies, timeout)) { 190 usleep_range(10, 100); 191 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR); 192 } 193 194 mutex_unlock(&atmel_pwm->isr_lock); 195 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); 196 197 /* 198 * Wait for the PWM channel disable operation to be effective before 199 * stopping the clock. 200 */ 201 timeout = jiffies + 2 * HZ; 202 203 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) && 204 time_before(jiffies, timeout)) 205 usleep_range(10, 100); 206 207 if (disable_clk) 208 clk_disable(atmel_pwm->clk); 209 } 210 211 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 212 struct pwm_state *state) 213 { 214 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); 215 struct pwm_state cstate; 216 unsigned long cprd, cdty; 217 u32 pres, val; 218 int ret; 219 220 pwm_get_state(pwm, &cstate); 221 222 if (state->enabled) { 223 if (cstate.enabled && 224 cstate.polarity == state->polarity && 225 cstate.period == state->period) { 226 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, 227 atmel_pwm->data->regs.period); 228 atmel_pwm_calculate_cdty(state, cprd, &cdty); 229 atmel_pwm_update_cdty(chip, pwm, cdty); 230 return 0; 231 } 232 233 ret = atmel_pwm_calculate_cprd_and_pres(chip, state, &cprd, 234 &pres); 235 if (ret) { 236 dev_err(chip->dev, 237 "failed to calculate cprd and prescaler\n"); 238 return ret; 239 } 240 241 atmel_pwm_calculate_cdty(state, cprd, &cdty); 242 243 if (cstate.enabled) { 244 atmel_pwm_disable(chip, pwm, false); 245 } else { 246 ret = clk_enable(atmel_pwm->clk); 247 if (ret) { 248 dev_err(chip->dev, "failed to enable clock\n"); 249 return ret; 250 } 251 } 252 253 /* It is necessary to preserve CPOL, inside CMR */ 254 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); 255 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK); 256 if (state->polarity == PWM_POLARITY_NORMAL) 257 val &= ~PWM_CMR_CPOL; 258 else 259 val |= PWM_CMR_CPOL; 260 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); 261 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty); 262 mutex_lock(&atmel_pwm->isr_lock); 263 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR); 264 atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm); 265 mutex_unlock(&atmel_pwm->isr_lock); 266 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm); 267 } else if (cstate.enabled) { 268 atmel_pwm_disable(chip, pwm, true); 269 } 270 271 return 0; 272 } 273 274 static const struct pwm_ops atmel_pwm_ops = { 275 .apply = atmel_pwm_apply, 276 .owner = THIS_MODULE, 277 }; 278 279 static const struct atmel_pwm_data atmel_sam9rl_pwm_data = { 280 .regs = { 281 .period = PWMV1_CPRD, 282 .period_upd = PWMV1_CUPD, 283 .duty = PWMV1_CDTY, 284 .duty_upd = PWMV1_CUPD, 285 }, 286 .cfg = { 287 /* 16 bits to keep period and duty. */ 288 .max_period = 0xffff, 289 .max_pres = 10, 290 }, 291 }; 292 293 static const struct atmel_pwm_data atmel_sama5_pwm_data = { 294 .regs = { 295 .period = PWMV2_CPRD, 296 .period_upd = PWMV2_CPRDUPD, 297 .duty = PWMV2_CDTY, 298 .duty_upd = PWMV2_CDTYUPD, 299 }, 300 .cfg = { 301 /* 16 bits to keep period and duty. */ 302 .max_period = 0xffff, 303 .max_pres = 10, 304 }, 305 }; 306 307 static const struct atmel_pwm_data mchp_sam9x60_pwm_data = { 308 .regs = { 309 .period = PWMV1_CPRD, 310 .period_upd = PWMV1_CUPD, 311 .duty = PWMV1_CDTY, 312 .duty_upd = PWMV1_CUPD, 313 }, 314 .cfg = { 315 /* 32 bits to keep period and duty. */ 316 .max_period = 0xffffffff, 317 .max_pres = 10, 318 }, 319 }; 320 321 static const struct platform_device_id atmel_pwm_devtypes[] = { 322 { 323 .name = "at91sam9rl-pwm", 324 .driver_data = (kernel_ulong_t)&atmel_sam9rl_pwm_data, 325 }, { 326 .name = "sama5d3-pwm", 327 .driver_data = (kernel_ulong_t)&atmel_sama5_pwm_data, 328 }, { 329 /* sentinel */ 330 }, 331 }; 332 MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes); 333 334 static const struct of_device_id atmel_pwm_dt_ids[] = { 335 { 336 .compatible = "atmel,at91sam9rl-pwm", 337 .data = &atmel_sam9rl_pwm_data, 338 }, { 339 .compatible = "atmel,sama5d3-pwm", 340 .data = &atmel_sama5_pwm_data, 341 }, { 342 .compatible = "atmel,sama5d2-pwm", 343 .data = &atmel_sama5_pwm_data, 344 }, { 345 .compatible = "microchip,sam9x60-pwm", 346 .data = &mchp_sam9x60_pwm_data, 347 }, { 348 /* sentinel */ 349 }, 350 }; 351 MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids); 352 353 static inline const struct atmel_pwm_data * 354 atmel_pwm_get_driver_data(struct platform_device *pdev) 355 { 356 const struct platform_device_id *id; 357 358 if (pdev->dev.of_node) 359 return of_device_get_match_data(&pdev->dev); 360 361 id = platform_get_device_id(pdev); 362 363 return (struct atmel_pwm_data *)id->driver_data; 364 } 365 366 static int atmel_pwm_probe(struct platform_device *pdev) 367 { 368 const struct atmel_pwm_data *data; 369 struct atmel_pwm_chip *atmel_pwm; 370 struct resource *res; 371 int ret; 372 373 data = atmel_pwm_get_driver_data(pdev); 374 if (!data) 375 return -ENODEV; 376 377 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL); 378 if (!atmel_pwm) 379 return -ENOMEM; 380 381 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 382 atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res); 383 if (IS_ERR(atmel_pwm->base)) 384 return PTR_ERR(atmel_pwm->base); 385 386 atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL); 387 if (IS_ERR(atmel_pwm->clk)) 388 return PTR_ERR(atmel_pwm->clk); 389 390 ret = clk_prepare(atmel_pwm->clk); 391 if (ret) { 392 dev_err(&pdev->dev, "failed to prepare PWM clock\n"); 393 return ret; 394 } 395 396 atmel_pwm->chip.dev = &pdev->dev; 397 atmel_pwm->chip.ops = &atmel_pwm_ops; 398 399 if (pdev->dev.of_node) { 400 atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags; 401 atmel_pwm->chip.of_pwm_n_cells = 3; 402 } 403 404 atmel_pwm->chip.base = -1; 405 atmel_pwm->chip.npwm = 4; 406 atmel_pwm->data = data; 407 atmel_pwm->updated_pwms = 0; 408 mutex_init(&atmel_pwm->isr_lock); 409 410 ret = pwmchip_add(&atmel_pwm->chip); 411 if (ret < 0) { 412 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret); 413 goto unprepare_clk; 414 } 415 416 platform_set_drvdata(pdev, atmel_pwm); 417 418 return ret; 419 420 unprepare_clk: 421 clk_unprepare(atmel_pwm->clk); 422 return ret; 423 } 424 425 static int atmel_pwm_remove(struct platform_device *pdev) 426 { 427 struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev); 428 429 clk_unprepare(atmel_pwm->clk); 430 mutex_destroy(&atmel_pwm->isr_lock); 431 432 return pwmchip_remove(&atmel_pwm->chip); 433 } 434 435 static struct platform_driver atmel_pwm_driver = { 436 .driver = { 437 .name = "atmel-pwm", 438 .of_match_table = of_match_ptr(atmel_pwm_dt_ids), 439 }, 440 .id_table = atmel_pwm_devtypes, 441 .probe = atmel_pwm_probe, 442 .remove = atmel_pwm_remove, 443 }; 444 module_platform_driver(atmel_pwm_driver); 445 446 MODULE_ALIAS("platform:atmel-pwm"); 447 MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>"); 448 MODULE_DESCRIPTION("Atmel PWM driver"); 449 MODULE_LICENSE("GPL v2"); 450