xref: /openbmc/linux/drivers/pwm/pwm-atmel.c (revision 62e7ca52) 
1 /*
2  * Driver for Atmel Pulse Width Modulation Controller
3  *
4  * Copyright (C) 2013 Atmel Corporation
5  *		 Bo Shen <voice.shen@atmel.com>
6  *
7  * Licensed under GPLv2.
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/pwm.h>
18 #include <linux/slab.h>
19 
20 /* The following is global registers for PWM controller */
21 #define PWM_ENA			0x04
22 #define PWM_DIS			0x08
23 #define PWM_SR			0x0C
24 /* Bit field in SR */
25 #define PWM_SR_ALL_CH_ON	0x0F
26 
27 /* The following register is PWM channel related registers */
28 #define PWM_CH_REG_OFFSET	0x200
29 #define PWM_CH_REG_SIZE		0x20
30 
31 #define PWM_CMR			0x0
32 /* Bit field in CMR */
33 #define PWM_CMR_CPOL		(1 << 9)
34 #define PWM_CMR_UPD_CDTY	(1 << 10)
35 #define PWM_CMR_CPRE_MSK	0xF
36 
37 /* The following registers for PWM v1 */
38 #define PWMV1_CDTY		0x04
39 #define PWMV1_CPRD		0x08
40 #define PWMV1_CUPD		0x10
41 
42 /* The following registers for PWM v2 */
43 #define PWMV2_CDTY		0x04
44 #define PWMV2_CDTYUPD		0x08
45 #define PWMV2_CPRD		0x0C
46 #define PWMV2_CPRDUPD		0x10
47 
48 /*
49  * Max value for duty and period
50  *
51  * Although the duty and period register is 32 bit,
52  * however only the LSB 16 bits are significant.
53  */
54 #define PWM_MAX_DTY		0xFFFF
55 #define PWM_MAX_PRD		0xFFFF
56 #define PRD_MAX_PRES		10
57 
58 struct atmel_pwm_chip {
59 	struct pwm_chip chip;
60 	struct clk *clk;
61 	void __iomem *base;
62 
63 	void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
64 		       unsigned long dty, unsigned long prd);
65 };
66 
67 static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
68 {
69 	return container_of(chip, struct atmel_pwm_chip, chip);
70 }
71 
72 static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
73 				  unsigned long offset)
74 {
75 	return readl_relaxed(chip->base + offset);
76 }
77 
78 static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
79 				    unsigned long offset, unsigned long val)
80 {
81 	writel_relaxed(val, chip->base + offset);
82 }
83 
84 static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
85 				     unsigned int ch, unsigned long offset)
86 {
87 	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
88 
89 	return readl_relaxed(chip->base + base + offset);
90 }
91 
92 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
93 				       unsigned int ch, unsigned long offset,
94 				       unsigned long val)
95 {
96 	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
97 
98 	writel_relaxed(val, chip->base + base + offset);
99 }
100 
101 static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
102 			    int duty_ns, int period_ns)
103 {
104 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
105 	unsigned long clk_rate, prd, dty;
106 	unsigned long long div;
107 	unsigned int pres = 0;
108 	u32 val;
109 	int ret;
110 
111 	if (test_bit(PWMF_ENABLED, &pwm->flags) && (period_ns != pwm->period)) {
112 		dev_err(chip->dev, "cannot change PWM period while enabled\n");
113 		return -EBUSY;
114 	}
115 
116 	clk_rate = clk_get_rate(atmel_pwm->clk);
117 	div = clk_rate;
118 
119 	/* Calculate the period cycles */
120 	while (div > PWM_MAX_PRD) {
121 		div = clk_rate / (1 << pres);
122 		div = div * period_ns;
123 		/* 1/Hz = 100000000 ns */
124 		do_div(div, 1000000000);
125 
126 		if (pres++ > PRD_MAX_PRES) {
127 			dev_err(chip->dev, "pres exceeds the maximum value\n");
128 			return -EINVAL;
129 		}
130 	}
131 
132 	/* Calculate the duty cycles */
133 	prd = div;
134 	div *= duty_ns;
135 	do_div(div, period_ns);
136 	dty = prd - div;
137 
138 	ret = clk_enable(atmel_pwm->clk);
139 	if (ret) {
140 		dev_err(chip->dev, "failed to enable PWM clock\n");
141 		return ret;
142 	}
143 
144 	/* It is necessary to preserve CPOL, inside CMR */
145 	val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
146 	val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
147 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
148 	atmel_pwm->config(chip, pwm, dty, prd);
149 
150 	clk_disable(atmel_pwm->clk);
151 	return ret;
152 }
153 
154 static void atmel_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm,
155 				unsigned long dty, unsigned long prd)
156 {
157 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
158 	unsigned int val;
159 
160 	if (test_bit(PWMF_ENABLED, &pwm->flags)) {
161 		/*
162 		 * If the PWM channel is enabled, using the update register,
163 		 * it needs to set bit 10 of CMR to 0
164 		 */
165 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty);
166 
167 		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
168 		val &= ~PWM_CMR_UPD_CDTY;
169 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
170 	} else {
171 		/*
172 		 * If the PWM channel is disabled, write value to duty and
173 		 * period registers directly.
174 		 */
175 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty);
176 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd);
177 	}
178 }
179 
180 static void atmel_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
181 				unsigned long dty, unsigned long prd)
182 {
183 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
184 
185 	if (test_bit(PWMF_ENABLED, &pwm->flags)) {
186 		/*
187 		 * If the PWM channel is enabled, using the duty update register
188 		 * to update the value.
189 		 */
190 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTYUPD, dty);
191 	} else {
192 		/*
193 		 * If the PWM channel is disabled, write value to duty and
194 		 * period registers directly.
195 		 */
196 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTY, dty);
197 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CPRD, prd);
198 	}
199 }
200 
201 static int atmel_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
202 				  enum pwm_polarity polarity)
203 {
204 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
205 	u32 val;
206 	int ret;
207 
208 	val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
209 
210 	if (polarity == PWM_POLARITY_NORMAL)
211 		val &= ~PWM_CMR_CPOL;
212 	else
213 		val |= PWM_CMR_CPOL;
214 
215 	ret = clk_enable(atmel_pwm->clk);
216 	if (ret) {
217 		dev_err(chip->dev, "failed to enable PWM clock\n");
218 		return ret;
219 	}
220 
221 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
222 
223 	clk_disable(atmel_pwm->clk);
224 
225 	return 0;
226 }
227 
228 static int atmel_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
229 {
230 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
231 	int ret;
232 
233 	ret = clk_enable(atmel_pwm->clk);
234 	if (ret) {
235 		dev_err(chip->dev, "failed to enable PWM clock\n");
236 		return ret;
237 	}
238 
239 	atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
240 
241 	return 0;
242 }
243 
244 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
245 {
246 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
247 
248 	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
249 
250 	clk_disable(atmel_pwm->clk);
251 }
252 
253 static const struct pwm_ops atmel_pwm_ops = {
254 	.config = atmel_pwm_config,
255 	.set_polarity = atmel_pwm_set_polarity,
256 	.enable = atmel_pwm_enable,
257 	.disable = atmel_pwm_disable,
258 	.owner = THIS_MODULE,
259 };
260 
261 struct atmel_pwm_data {
262 	void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
263 		       unsigned long dty, unsigned long prd);
264 };
265 
266 static const struct atmel_pwm_data atmel_pwm_data_v1 = {
267 	.config = atmel_pwm_config_v1,
268 };
269 
270 static const struct atmel_pwm_data atmel_pwm_data_v2 = {
271 	.config = atmel_pwm_config_v2,
272 };
273 
274 static const struct platform_device_id atmel_pwm_devtypes[] = {
275 	{
276 		.name = "at91sam9rl-pwm",
277 		.driver_data = (kernel_ulong_t)&atmel_pwm_data_v1,
278 	}, {
279 		.name = "sama5d3-pwm",
280 		.driver_data = (kernel_ulong_t)&atmel_pwm_data_v2,
281 	}, {
282 		/* sentinel */
283 	},
284 };
285 MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
286 
287 static const struct of_device_id atmel_pwm_dt_ids[] = {
288 	{
289 		.compatible = "atmel,at91sam9rl-pwm",
290 		.data = &atmel_pwm_data_v1,
291 	}, {
292 		.compatible = "atmel,sama5d3-pwm",
293 		.data = &atmel_pwm_data_v2,
294 	}, {
295 		/* sentinel */
296 	},
297 };
298 MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
299 
300 static inline const struct atmel_pwm_data *
301 atmel_pwm_get_driver_data(struct platform_device *pdev)
302 {
303 	if (pdev->dev.of_node) {
304 		const struct of_device_id *match;
305 
306 		match = of_match_device(atmel_pwm_dt_ids, &pdev->dev);
307 		if (!match)
308 			return NULL;
309 
310 		return match->data;
311 	} else {
312 		const struct platform_device_id *id;
313 
314 		id = platform_get_device_id(pdev);
315 
316 		return (struct atmel_pwm_data *)id->driver_data;
317 	}
318 }
319 
320 static int atmel_pwm_probe(struct platform_device *pdev)
321 {
322 	const struct atmel_pwm_data *data;
323 	struct atmel_pwm_chip *atmel_pwm;
324 	struct resource *res;
325 	int ret;
326 
327 	data = atmel_pwm_get_driver_data(pdev);
328 	if (!data)
329 		return -ENODEV;
330 
331 	atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
332 	if (!atmel_pwm)
333 		return -ENOMEM;
334 
335 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
336 	atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
337 	if (IS_ERR(atmel_pwm->base))
338 		return PTR_ERR(atmel_pwm->base);
339 
340 	atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
341 	if (IS_ERR(atmel_pwm->clk))
342 		return PTR_ERR(atmel_pwm->clk);
343 
344 	ret = clk_prepare(atmel_pwm->clk);
345 	if (ret) {
346 		dev_err(&pdev->dev, "failed to prepare PWM clock\n");
347 		return ret;
348 	}
349 
350 	atmel_pwm->chip.dev = &pdev->dev;
351 	atmel_pwm->chip.ops = &atmel_pwm_ops;
352 
353 	if (pdev->dev.of_node) {
354 		atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
355 		atmel_pwm->chip.of_pwm_n_cells = 3;
356 	}
357 
358 	atmel_pwm->chip.base = -1;
359 	atmel_pwm->chip.npwm = 4;
360 	atmel_pwm->chip.can_sleep = true;
361 	atmel_pwm->config = data->config;
362 
363 	ret = pwmchip_add(&atmel_pwm->chip);
364 	if (ret < 0) {
365 		dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
366 		goto unprepare_clk;
367 	}
368 
369 	platform_set_drvdata(pdev, atmel_pwm);
370 
371 	return ret;
372 
373 unprepare_clk:
374 	clk_unprepare(atmel_pwm->clk);
375 	return ret;
376 }
377 
378 static int atmel_pwm_remove(struct platform_device *pdev)
379 {
380 	struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
381 
382 	clk_unprepare(atmel_pwm->clk);
383 
384 	return pwmchip_remove(&atmel_pwm->chip);
385 }
386 
387 static struct platform_driver atmel_pwm_driver = {
388 	.driver = {
389 		.name = "atmel-pwm",
390 		.of_match_table = of_match_ptr(atmel_pwm_dt_ids),
391 	},
392 	.id_table = atmel_pwm_devtypes,
393 	.probe = atmel_pwm_probe,
394 	.remove = atmel_pwm_remove,
395 };
396 module_platform_driver(atmel_pwm_driver);
397 
398 MODULE_ALIAS("platform:atmel-pwm");
399 MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
400 MODULE_DESCRIPTION("Atmel PWM driver");
401 MODULE_LICENSE("GPL v2");
402