1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for Atmel Pulse Width Modulation Controller 4 * 5 * Copyright (C) 2013 Atmel Corporation 6 * Bo Shen <voice.shen@atmel.com> 7 * 8 * Links to reference manuals for the supported PWM chips can be found in 9 * Documentation/arm/microchip.rst. 10 * 11 * Limitations: 12 * - Periods start with the inactive level. 13 * - Hardware has to be stopped in general to update settings. 14 * 15 * Software bugs/possible improvements: 16 * - When atmel_pwm_apply() is called with state->enabled=false a change in 17 * state->polarity isn't honored. 18 * - Instead of sleeping to wait for a completed period, the interrupt 19 * functionality could be used. 20 */ 21 22 #include <linux/clk.h> 23 #include <linux/delay.h> 24 #include <linux/err.h> 25 #include <linux/io.h> 26 #include <linux/module.h> 27 #include <linux/mutex.h> 28 #include <linux/of.h> 29 #include <linux/of_device.h> 30 #include <linux/platform_device.h> 31 #include <linux/pwm.h> 32 #include <linux/slab.h> 33 34 /* The following is global registers for PWM controller */ 35 #define PWM_ENA 0x04 36 #define PWM_DIS 0x08 37 #define PWM_SR 0x0C 38 #define PWM_ISR 0x1C 39 /* Bit field in SR */ 40 #define PWM_SR_ALL_CH_ON 0x0F 41 42 /* The following register is PWM channel related registers */ 43 #define PWM_CH_REG_OFFSET 0x200 44 #define PWM_CH_REG_SIZE 0x20 45 46 #define PWM_CMR 0x0 47 /* Bit field in CMR */ 48 #define PWM_CMR_CPOL (1 << 9) 49 #define PWM_CMR_UPD_CDTY (1 << 10) 50 #define PWM_CMR_CPRE_MSK 0xF 51 52 /* The following registers for PWM v1 */ 53 #define PWMV1_CDTY 0x04 54 #define PWMV1_CPRD 0x08 55 #define PWMV1_CUPD 0x10 56 57 /* The following registers for PWM v2 */ 58 #define PWMV2_CDTY 0x04 59 #define PWMV2_CDTYUPD 0x08 60 #define PWMV2_CPRD 0x0C 61 #define PWMV2_CPRDUPD 0x10 62 63 #define PWM_MAX_PRES 10 64 65 struct atmel_pwm_registers { 66 u8 period; 67 u8 period_upd; 68 u8 duty; 69 u8 duty_upd; 70 }; 71 72 struct atmel_pwm_config { 73 u32 period_bits; 74 }; 75 76 struct atmel_pwm_data { 77 struct atmel_pwm_registers regs; 78 struct atmel_pwm_config cfg; 79 }; 80 81 struct atmel_pwm_chip { 82 struct pwm_chip chip; 83 struct clk *clk; 84 void __iomem *base; 85 const struct atmel_pwm_data *data; 86 87 /* 88 * The hardware supports a mechanism to update a channel's duty cycle at 89 * the end of the currently running period. When such an update is 90 * pending we delay disabling the PWM until the new configuration is 91 * active because otherwise pmw_config(duty_cycle=0); pwm_disable(); 92 * might not result in an inactive output. 93 * This bitmask tracks for which channels an update is pending in 94 * hardware. 95 */ 96 u32 update_pending; 97 98 /* Protects .update_pending */ 99 spinlock_t lock; 100 }; 101 102 static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip) 103 { 104 return container_of(chip, struct atmel_pwm_chip, chip); 105 } 106 107 static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip, 108 unsigned long offset) 109 { 110 return readl_relaxed(chip->base + offset); 111 } 112 113 static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip, 114 unsigned long offset, unsigned long val) 115 { 116 writel_relaxed(val, chip->base + offset); 117 } 118 119 static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip, 120 unsigned int ch, unsigned long offset) 121 { 122 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE; 123 124 return atmel_pwm_readl(chip, base + offset); 125 } 126 127 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip, 128 unsigned int ch, unsigned long offset, 129 unsigned long val) 130 { 131 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE; 132 133 atmel_pwm_writel(chip, base + offset, val); 134 } 135 136 static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip) 137 { 138 /* 139 * Each channel that has its bit in ISR set started a new period since 140 * ISR was cleared and so there is no more update pending. Note that 141 * reading ISR clears it, so this needs to handle all channels to not 142 * loose information. 143 */ 144 u32 isr = atmel_pwm_readl(chip, PWM_ISR); 145 146 chip->update_pending &= ~isr; 147 } 148 149 static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch) 150 { 151 spin_lock(&chip->lock); 152 153 /* 154 * Clear pending flags in hardware because otherwise there might still 155 * be a stale flag in ISR. 156 */ 157 atmel_pwm_update_pending(chip); 158 159 chip->update_pending |= (1 << ch); 160 161 spin_unlock(&chip->lock); 162 } 163 164 static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch) 165 { 166 int ret = 0; 167 168 spin_lock(&chip->lock); 169 170 if (chip->update_pending & (1 << ch)) { 171 atmel_pwm_update_pending(chip); 172 173 if (chip->update_pending & (1 << ch)) 174 ret = 1; 175 } 176 177 spin_unlock(&chip->lock); 178 179 return ret; 180 } 181 182 static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch) 183 { 184 unsigned long timeout = jiffies + 2 * HZ; 185 int ret; 186 187 while ((ret = atmel_pwm_test_pending(chip, ch)) && 188 time_before(jiffies, timeout)) 189 usleep_range(10, 100); 190 191 return ret ? -ETIMEDOUT : 0; 192 } 193 194 static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip, 195 unsigned long clkrate, 196 const struct pwm_state *state, 197 unsigned long *cprd, u32 *pres) 198 { 199 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); 200 unsigned long long cycles = state->period; 201 int shift; 202 203 /* Calculate the period cycles and prescale value */ 204 cycles *= clkrate; 205 do_div(cycles, NSEC_PER_SEC); 206 207 /* 208 * The register for the period length is cfg.period_bits bits wide. 209 * So for each bit the number of clock cycles is wider divide the input 210 * clock frequency by two using pres and shift cprd accordingly. 211 */ 212 shift = fls(cycles) - atmel_pwm->data->cfg.period_bits; 213 214 if (shift > PWM_MAX_PRES) { 215 dev_err(chip->dev, "pres exceeds the maximum value\n"); 216 return -EINVAL; 217 } else if (shift > 0) { 218 *pres = shift; 219 cycles >>= *pres; 220 } else { 221 *pres = 0; 222 } 223 224 *cprd = cycles; 225 226 return 0; 227 } 228 229 static void atmel_pwm_calculate_cdty(const struct pwm_state *state, 230 unsigned long clkrate, unsigned long cprd, 231 u32 pres, unsigned long *cdty) 232 { 233 unsigned long long cycles = state->duty_cycle; 234 235 cycles *= clkrate; 236 do_div(cycles, NSEC_PER_SEC); 237 cycles >>= pres; 238 *cdty = cprd - cycles; 239 } 240 241 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm, 242 unsigned long cdty) 243 { 244 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); 245 u32 val; 246 247 if (atmel_pwm->data->regs.duty_upd == 248 atmel_pwm->data->regs.period_upd) { 249 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); 250 val &= ~PWM_CMR_UPD_CDTY; 251 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); 252 } 253 254 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, 255 atmel_pwm->data->regs.duty_upd, cdty); 256 atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm); 257 } 258 259 static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip, 260 struct pwm_device *pwm, 261 unsigned long cprd, unsigned long cdty) 262 { 263 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); 264 265 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, 266 atmel_pwm->data->regs.duty, cdty); 267 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, 268 atmel_pwm->data->regs.period, cprd); 269 } 270 271 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm, 272 bool disable_clk) 273 { 274 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); 275 unsigned long timeout = jiffies + 2 * HZ; 276 277 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm); 278 279 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); 280 281 /* 282 * Wait for the PWM channel disable operation to be effective before 283 * stopping the clock. 284 */ 285 timeout = jiffies + 2 * HZ; 286 287 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) && 288 time_before(jiffies, timeout)) 289 usleep_range(10, 100); 290 291 if (disable_clk) 292 clk_disable(atmel_pwm->clk); 293 } 294 295 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 296 const struct pwm_state *state) 297 { 298 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); 299 struct pwm_state cstate; 300 unsigned long cprd, cdty; 301 u32 pres, val; 302 int ret; 303 304 pwm_get_state(pwm, &cstate); 305 306 if (state->enabled) { 307 unsigned long clkrate = clk_get_rate(atmel_pwm->clk); 308 309 if (cstate.enabled && 310 cstate.polarity == state->polarity && 311 cstate.period == state->period) { 312 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); 313 314 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, 315 atmel_pwm->data->regs.period); 316 pres = cmr & PWM_CMR_CPRE_MSK; 317 318 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty); 319 atmel_pwm_update_cdty(chip, pwm, cdty); 320 return 0; 321 } 322 323 ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd, 324 &pres); 325 if (ret) { 326 dev_err(chip->dev, 327 "failed to calculate cprd and prescaler\n"); 328 return ret; 329 } 330 331 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty); 332 333 if (cstate.enabled) { 334 atmel_pwm_disable(chip, pwm, false); 335 } else { 336 ret = clk_enable(atmel_pwm->clk); 337 if (ret) { 338 dev_err(chip->dev, "failed to enable clock\n"); 339 return ret; 340 } 341 } 342 343 /* It is necessary to preserve CPOL, inside CMR */ 344 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); 345 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK); 346 if (state->polarity == PWM_POLARITY_NORMAL) 347 val &= ~PWM_CMR_CPOL; 348 else 349 val |= PWM_CMR_CPOL; 350 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); 351 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty); 352 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm); 353 } else if (cstate.enabled) { 354 atmel_pwm_disable(chip, pwm, true); 355 } 356 357 return 0; 358 } 359 360 static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 361 struct pwm_state *state) 362 { 363 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); 364 u32 sr, cmr; 365 366 sr = atmel_pwm_readl(atmel_pwm, PWM_SR); 367 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); 368 369 if (sr & (1 << pwm->hwpwm)) { 370 unsigned long rate = clk_get_rate(atmel_pwm->clk); 371 u32 cdty, cprd, pres; 372 u64 tmp; 373 374 pres = cmr & PWM_CMR_CPRE_MSK; 375 376 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, 377 atmel_pwm->data->regs.period); 378 tmp = (u64)cprd * NSEC_PER_SEC; 379 tmp <<= pres; 380 state->period = DIV64_U64_ROUND_UP(tmp, rate); 381 382 /* Wait for an updated duty_cycle queued in hardware */ 383 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm); 384 385 cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, 386 atmel_pwm->data->regs.duty); 387 tmp = (u64)(cprd - cdty) * NSEC_PER_SEC; 388 tmp <<= pres; 389 state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate); 390 391 state->enabled = true; 392 } else { 393 state->enabled = false; 394 } 395 396 if (cmr & PWM_CMR_CPOL) 397 state->polarity = PWM_POLARITY_INVERSED; 398 else 399 state->polarity = PWM_POLARITY_NORMAL; 400 } 401 402 static const struct pwm_ops atmel_pwm_ops = { 403 .apply = atmel_pwm_apply, 404 .get_state = atmel_pwm_get_state, 405 .owner = THIS_MODULE, 406 }; 407 408 static const struct atmel_pwm_data atmel_sam9rl_pwm_data = { 409 .regs = { 410 .period = PWMV1_CPRD, 411 .period_upd = PWMV1_CUPD, 412 .duty = PWMV1_CDTY, 413 .duty_upd = PWMV1_CUPD, 414 }, 415 .cfg = { 416 /* 16 bits to keep period and duty. */ 417 .period_bits = 16, 418 }, 419 }; 420 421 static const struct atmel_pwm_data atmel_sama5_pwm_data = { 422 .regs = { 423 .period = PWMV2_CPRD, 424 .period_upd = PWMV2_CPRDUPD, 425 .duty = PWMV2_CDTY, 426 .duty_upd = PWMV2_CDTYUPD, 427 }, 428 .cfg = { 429 /* 16 bits to keep period and duty. */ 430 .period_bits = 16, 431 }, 432 }; 433 434 static const struct atmel_pwm_data mchp_sam9x60_pwm_data = { 435 .regs = { 436 .period = PWMV1_CPRD, 437 .period_upd = PWMV1_CUPD, 438 .duty = PWMV1_CDTY, 439 .duty_upd = PWMV1_CUPD, 440 }, 441 .cfg = { 442 /* 32 bits to keep period and duty. */ 443 .period_bits = 32, 444 }, 445 }; 446 447 static const struct of_device_id atmel_pwm_dt_ids[] = { 448 { 449 .compatible = "atmel,at91sam9rl-pwm", 450 .data = &atmel_sam9rl_pwm_data, 451 }, { 452 .compatible = "atmel,sama5d3-pwm", 453 .data = &atmel_sama5_pwm_data, 454 }, { 455 .compatible = "atmel,sama5d2-pwm", 456 .data = &atmel_sama5_pwm_data, 457 }, { 458 .compatible = "microchip,sam9x60-pwm", 459 .data = &mchp_sam9x60_pwm_data, 460 }, { 461 /* sentinel */ 462 }, 463 }; 464 MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids); 465 466 static int atmel_pwm_probe(struct platform_device *pdev) 467 { 468 struct atmel_pwm_chip *atmel_pwm; 469 int ret; 470 471 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL); 472 if (!atmel_pwm) 473 return -ENOMEM; 474 475 atmel_pwm->data = of_device_get_match_data(&pdev->dev); 476 477 atmel_pwm->update_pending = 0; 478 spin_lock_init(&atmel_pwm->lock); 479 480 atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0); 481 if (IS_ERR(atmel_pwm->base)) 482 return PTR_ERR(atmel_pwm->base); 483 484 atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL); 485 if (IS_ERR(atmel_pwm->clk)) 486 return PTR_ERR(atmel_pwm->clk); 487 488 ret = clk_prepare(atmel_pwm->clk); 489 if (ret) { 490 dev_err(&pdev->dev, "failed to prepare PWM clock\n"); 491 return ret; 492 } 493 494 atmel_pwm->chip.dev = &pdev->dev; 495 atmel_pwm->chip.ops = &atmel_pwm_ops; 496 atmel_pwm->chip.npwm = 4; 497 498 ret = pwmchip_add(&atmel_pwm->chip); 499 if (ret < 0) { 500 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret); 501 goto unprepare_clk; 502 } 503 504 platform_set_drvdata(pdev, atmel_pwm); 505 506 return ret; 507 508 unprepare_clk: 509 clk_unprepare(atmel_pwm->clk); 510 return ret; 511 } 512 513 static int atmel_pwm_remove(struct platform_device *pdev) 514 { 515 struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev); 516 517 pwmchip_remove(&atmel_pwm->chip); 518 519 clk_unprepare(atmel_pwm->clk); 520 521 return 0; 522 } 523 524 static struct platform_driver atmel_pwm_driver = { 525 .driver = { 526 .name = "atmel-pwm", 527 .of_match_table = of_match_ptr(atmel_pwm_dt_ids), 528 }, 529 .probe = atmel_pwm_probe, 530 .remove = atmel_pwm_remove, 531 }; 532 module_platform_driver(atmel_pwm_driver); 533 534 MODULE_ALIAS("platform:atmel-pwm"); 535 MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>"); 536 MODULE_DESCRIPTION("Atmel PWM driver"); 537 MODULE_LICENSE("GPL v2"); 538