1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) ST-Ericsson SA 2010 4 * 5 * Author: Arun R Murthy <arun.murthy@stericsson.com> 6 * Datasheet: https://web.archive.org/web/20130614115108/http://www.stericsson.com/developers/CD00291561_UM1031_AB8500_user_manual-rev5_CTDS_public.pdf 7 */ 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/slab.h> 11 #include <linux/pwm.h> 12 #include <linux/mfd/abx500.h> 13 #include <linux/mfd/abx500/ab8500.h> 14 #include <linux/module.h> 15 16 /* 17 * PWM Out generators 18 * Bank: 0x10 19 */ 20 #define AB8500_PWM_OUT_CTRL1_REG 0x60 21 #define AB8500_PWM_OUT_CTRL2_REG 0x61 22 #define AB8500_PWM_OUT_CTRL7_REG 0x66 23 24 #define AB8500_PWM_CLKRATE 9600000 25 26 struct ab8500_pwm_chip { 27 struct pwm_chip chip; 28 unsigned int hwid; 29 }; 30 31 static struct ab8500_pwm_chip *ab8500_pwm_from_chip(struct pwm_chip *chip) 32 { 33 return container_of(chip, struct ab8500_pwm_chip, chip); 34 } 35 36 static int ab8500_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 37 const struct pwm_state *state) 38 { 39 int ret; 40 u8 reg; 41 u8 higher_val, lower_val; 42 unsigned int duty_steps, div; 43 struct ab8500_pwm_chip *ab8500 = ab8500_pwm_from_chip(chip); 44 45 if (state->polarity != PWM_POLARITY_NORMAL) 46 return -EINVAL; 47 48 if (state->enabled) { 49 /* 50 * A time quantum is 51 * q = (32 - FreqPWMOutx[3:0]) / AB8500_PWM_CLKRATE 52 * The period is always 1024 q, duty_cycle is between 1q and 1024q. 53 * 54 * FreqPWMOutx[3:0] | output frequency | output frequency | 1024q = period 55 * | (from manual) | (1 / 1024q) | = 1 / freq 56 * -----------------+------------------+------------------+-------------- 57 * b0000 | 293 Hz | 292.968750 Hz | 3413333.33 ns 58 * b0001 | 302 Hz | 302.419355 Hz | 3306666.66 ns 59 * b0010 | 312 Hz | 312.500000 Hz | 3200000 ns 60 * b0011 | 323 Hz | 323.275862 Hz | 3093333.33 ns 61 * b0100 | 334 Hz | 334.821429 Hz | 2986666.66 ns 62 * b0101 | 347 Hz | 347.222222 Hz | 2880000 ns 63 * b0110 | 360 Hz | 360.576923 Hz | 2773333.33 ns 64 * b0111 | 375 Hz | 375.000000 Hz | 2666666.66 ns 65 * b1000 | 390 Hz | 390.625000 Hz | 2560000 ns 66 * b1001 | 407 Hz | 407.608696 Hz | 2453333.33 ns 67 * b1010 | 426 Hz | 426.136364 Hz | 2346666.66 ns 68 * b1011 | 446 Hz | 446.428571 Hz | 2240000 ns 69 * b1100 | 468 Hz | 468.750000 Hz | 2133333.33 ns 70 * b1101 | 493 Hz | 493.421053 Hz | 2026666.66 ns 71 * b1110 | 520 Hz | 520.833333 Hz | 1920000 ns 72 * b1111 | 551 Hz | 551.470588 Hz | 1813333.33 ns 73 * 74 * 75 * AB8500_PWM_CLKRATE is a multiple of 1024, so the division by 76 * 1024 can be done in this factor without loss of precision. 77 */ 78 div = min_t(u64, mul_u64_u64_div_u64(state->period, 79 AB8500_PWM_CLKRATE >> 10, 80 NSEC_PER_SEC), 32); /* 32 - FreqPWMOutx[3:0] */ 81 if (div <= 16) 82 /* requested period < 3413333.33 */ 83 return -EINVAL; 84 85 duty_steps = max_t(u64, mul_u64_u64_div_u64(state->duty_cycle, 86 AB8500_PWM_CLKRATE, 87 (u64)NSEC_PER_SEC * div), 1024); 88 } 89 90 /* 91 * The hardware doesn't support duty_steps = 0 explicitly, but emits low 92 * when disabled. 93 */ 94 if (!state->enabled || duty_steps == 0) { 95 ret = abx500_mask_and_set_register_interruptible(chip->dev, 96 AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, 97 1 << ab8500->hwid, 0); 98 99 if (ret < 0) 100 dev_err(chip->dev, "%s: Failed to disable PWM, Error %d\n", 101 pwm->label, ret); 102 return ret; 103 } 104 105 /* 106 * The lower 8 bits of duty_steps is written to ... 107 * AB8500_PWM_OUT_CTRL1_REG[0:7] 108 */ 109 lower_val = (duty_steps - 1) & 0x00ff; 110 /* 111 * The two remaining high bits to 112 * AB8500_PWM_OUT_CTRL2_REG[0:1]; together with FreqPWMOutx. 113 */ 114 higher_val = ((duty_steps - 1) & 0x0300) >> 8 | (32 - div) << 4; 115 116 reg = AB8500_PWM_OUT_CTRL1_REG + (ab8500->hwid * 2); 117 118 ret = abx500_set_register_interruptible(chip->dev, AB8500_MISC, 119 reg, lower_val); 120 if (ret < 0) 121 return ret; 122 123 ret = abx500_set_register_interruptible(chip->dev, AB8500_MISC, 124 (reg + 1), higher_val); 125 if (ret < 0) 126 return ret; 127 128 /* enable */ 129 ret = abx500_mask_and_set_register_interruptible(chip->dev, 130 AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, 131 1 << ab8500->hwid, 1 << ab8500->hwid); 132 if (ret < 0) 133 dev_err(chip->dev, "%s: Failed to enable PWM, Error %d\n", 134 pwm->label, ret); 135 136 return ret; 137 } 138 139 static int ab8500_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 140 struct pwm_state *state) 141 { 142 u8 ctrl7, lower_val, higher_val; 143 int ret; 144 struct ab8500_pwm_chip *ab8500 = ab8500_pwm_from_chip(chip); 145 unsigned int div, duty_steps; 146 147 ret = abx500_get_register_interruptible(chip->dev, AB8500_MISC, 148 AB8500_PWM_OUT_CTRL7_REG, 149 &ctrl7); 150 if (ret) 151 return ret; 152 153 state->polarity = PWM_POLARITY_NORMAL; 154 155 if (!(ctrl7 & 1 << ab8500->hwid)) { 156 state->enabled = false; 157 return 0; 158 } 159 160 ret = abx500_get_register_interruptible(chip->dev, AB8500_MISC, 161 AB8500_PWM_OUT_CTRL1_REG + (ab8500->hwid * 2), 162 &lower_val); 163 if (ret) 164 return ret; 165 166 ret = abx500_get_register_interruptible(chip->dev, AB8500_MISC, 167 AB8500_PWM_OUT_CTRL2_REG + (ab8500->hwid * 2), 168 &higher_val); 169 if (ret) 170 return ret; 171 172 div = 32 - ((higher_val & 0xf0) >> 4); 173 duty_steps = ((higher_val & 3) << 8 | lower_val) + 1; 174 175 state->period = DIV64_U64_ROUND_UP((u64)div << 10, AB8500_PWM_CLKRATE); 176 state->duty_cycle = DIV64_U64_ROUND_UP((u64)div * duty_steps, AB8500_PWM_CLKRATE); 177 178 return 0; 179 } 180 181 static const struct pwm_ops ab8500_pwm_ops = { 182 .apply = ab8500_pwm_apply, 183 .get_state = ab8500_pwm_get_state, 184 .owner = THIS_MODULE, 185 }; 186 187 static int ab8500_pwm_probe(struct platform_device *pdev) 188 { 189 struct ab8500_pwm_chip *ab8500; 190 int err; 191 192 if (pdev->id < 1 || pdev->id > 31) 193 return dev_err_probe(&pdev->dev, EINVAL, "Invalid device id %d\n", pdev->id); 194 195 /* 196 * Nothing to be done in probe, this is required to get the 197 * device which is required for ab8500 read and write 198 */ 199 ab8500 = devm_kzalloc(&pdev->dev, sizeof(*ab8500), GFP_KERNEL); 200 if (ab8500 == NULL) 201 return -ENOMEM; 202 203 ab8500->chip.dev = &pdev->dev; 204 ab8500->chip.ops = &ab8500_pwm_ops; 205 ab8500->chip.npwm = 1; 206 ab8500->hwid = pdev->id - 1; 207 208 err = devm_pwmchip_add(&pdev->dev, &ab8500->chip); 209 if (err < 0) 210 return dev_err_probe(&pdev->dev, err, "Failed to add pwm chip\n"); 211 212 dev_dbg(&pdev->dev, "pwm probe successful\n"); 213 214 return 0; 215 } 216 217 static struct platform_driver ab8500_pwm_driver = { 218 .driver = { 219 .name = "ab8500-pwm", 220 }, 221 .probe = ab8500_pwm_probe, 222 }; 223 module_platform_driver(ab8500_pwm_driver); 224 225 MODULE_AUTHOR("Arun MURTHY <arun.murthy@stericsson.com>"); 226 MODULE_DESCRIPTION("AB8500 Pulse Width Modulation Driver"); 227 MODULE_ALIAS("platform:ab8500-pwm"); 228 MODULE_LICENSE("GPL v2"); 229