1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PTP 1588 clock using the EG20T PCH 4 * 5 * Copyright (C) 2010 OMICRON electronics GmbH 6 * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD. 7 * 8 * This code was derived from the IXP46X driver. 9 */ 10 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/ptp_clock_kernel.h> 21 #include <linux/slab.h> 22 23 #define STATION_ADDR_LEN 20 24 #define PCI_DEVICE_ID_PCH_1588 0x8819 25 #define IO_MEM_BAR 1 26 27 #define DEFAULT_ADDEND 0xA0000000 28 #define TICKS_NS_SHIFT 5 29 #define N_EXT_TS 2 30 31 enum pch_status { 32 PCH_SUCCESS, 33 PCH_INVALIDPARAM, 34 PCH_NOTIMESTAMP, 35 PCH_INTERRUPTMODEINUSE, 36 PCH_FAILED, 37 PCH_UNSUPPORTED, 38 }; 39 /** 40 * struct pch_ts_regs - IEEE 1588 registers 41 */ 42 struct pch_ts_regs { 43 u32 control; 44 u32 event; 45 u32 addend; 46 u32 accum; 47 u32 test; 48 u32 ts_compare; 49 u32 rsystime_lo; 50 u32 rsystime_hi; 51 u32 systime_lo; 52 u32 systime_hi; 53 u32 trgt_lo; 54 u32 trgt_hi; 55 u32 asms_lo; 56 u32 asms_hi; 57 u32 amms_lo; 58 u32 amms_hi; 59 u32 ch_control; 60 u32 ch_event; 61 u32 tx_snap_lo; 62 u32 tx_snap_hi; 63 u32 rx_snap_lo; 64 u32 rx_snap_hi; 65 u32 src_uuid_lo; 66 u32 src_uuid_hi; 67 u32 can_status; 68 u32 can_snap_lo; 69 u32 can_snap_hi; 70 u32 ts_sel; 71 u32 ts_st[6]; 72 u32 reserve1[14]; 73 u32 stl_max_set_en; 74 u32 stl_max_set; 75 u32 reserve2[13]; 76 u32 srst; 77 }; 78 79 #define PCH_TSC_RESET (1 << 0) 80 #define PCH_TSC_TTM_MASK (1 << 1) 81 #define PCH_TSC_ASMS_MASK (1 << 2) 82 #define PCH_TSC_AMMS_MASK (1 << 3) 83 #define PCH_TSC_PPSM_MASK (1 << 4) 84 #define PCH_TSE_TTIPEND (1 << 1) 85 #define PCH_TSE_SNS (1 << 2) 86 #define PCH_TSE_SNM (1 << 3) 87 #define PCH_TSE_PPS (1 << 4) 88 #define PCH_CC_MM (1 << 0) 89 #define PCH_CC_TA (1 << 1) 90 91 #define PCH_CC_MODE_SHIFT 16 92 #define PCH_CC_MODE_MASK 0x001F0000 93 #define PCH_CC_VERSION (1 << 31) 94 #define PCH_CE_TXS (1 << 0) 95 #define PCH_CE_RXS (1 << 1) 96 #define PCH_CE_OVR (1 << 0) 97 #define PCH_CE_VAL (1 << 1) 98 #define PCH_ECS_ETH (1 << 0) 99 100 #define PCH_ECS_CAN (1 << 1) 101 #define PCH_STATION_BYTES 6 102 103 #define PCH_IEEE1588_ETH (1 << 0) 104 #define PCH_IEEE1588_CAN (1 << 1) 105 /** 106 * struct pch_dev - Driver private data 107 */ 108 struct pch_dev { 109 struct pch_ts_regs __iomem *regs; 110 struct ptp_clock *ptp_clock; 111 struct ptp_clock_info caps; 112 int exts0_enabled; 113 int exts1_enabled; 114 115 u32 mem_base; 116 u32 mem_size; 117 u32 irq; 118 struct pci_dev *pdev; 119 spinlock_t register_lock; 120 }; 121 122 /** 123 * struct pch_params - 1588 module parameter 124 */ 125 struct pch_params { 126 u8 station[STATION_ADDR_LEN]; 127 }; 128 129 /* structure to hold the module parameters */ 130 static struct pch_params pch_param = { 131 "00:00:00:00:00:00" 132 }; 133 134 /* 135 * Register access functions 136 */ 137 static inline void pch_eth_enable_set(struct pch_dev *chip) 138 { 139 u32 val; 140 /* SET the eth_enable bit */ 141 val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH); 142 iowrite32(val, (&chip->regs->ts_sel)); 143 } 144 145 static u64 pch_systime_read(struct pch_ts_regs __iomem *regs) 146 { 147 u64 ns; 148 u32 lo, hi; 149 150 lo = ioread32(®s->systime_lo); 151 hi = ioread32(®s->systime_hi); 152 153 ns = ((u64) hi) << 32; 154 ns |= lo; 155 ns <<= TICKS_NS_SHIFT; 156 157 return ns; 158 } 159 160 static void pch_systime_write(struct pch_ts_regs __iomem *regs, u64 ns) 161 { 162 u32 hi, lo; 163 164 ns >>= TICKS_NS_SHIFT; 165 hi = ns >> 32; 166 lo = ns & 0xffffffff; 167 168 iowrite32(lo, ®s->systime_lo); 169 iowrite32(hi, ®s->systime_hi); 170 } 171 172 static inline void pch_block_reset(struct pch_dev *chip) 173 { 174 u32 val; 175 /* Reset Hardware Assist block */ 176 val = ioread32(&chip->regs->control) | PCH_TSC_RESET; 177 iowrite32(val, (&chip->regs->control)); 178 val = val & ~PCH_TSC_RESET; 179 iowrite32(val, (&chip->regs->control)); 180 } 181 182 u32 pch_ch_control_read(struct pci_dev *pdev) 183 { 184 struct pch_dev *chip = pci_get_drvdata(pdev); 185 u32 val; 186 187 val = ioread32(&chip->regs->ch_control); 188 189 return val; 190 } 191 EXPORT_SYMBOL(pch_ch_control_read); 192 193 void pch_ch_control_write(struct pci_dev *pdev, u32 val) 194 { 195 struct pch_dev *chip = pci_get_drvdata(pdev); 196 197 iowrite32(val, (&chip->regs->ch_control)); 198 } 199 EXPORT_SYMBOL(pch_ch_control_write); 200 201 u32 pch_ch_event_read(struct pci_dev *pdev) 202 { 203 struct pch_dev *chip = pci_get_drvdata(pdev); 204 u32 val; 205 206 val = ioread32(&chip->regs->ch_event); 207 208 return val; 209 } 210 EXPORT_SYMBOL(pch_ch_event_read); 211 212 void pch_ch_event_write(struct pci_dev *pdev, u32 val) 213 { 214 struct pch_dev *chip = pci_get_drvdata(pdev); 215 216 iowrite32(val, (&chip->regs->ch_event)); 217 } 218 EXPORT_SYMBOL(pch_ch_event_write); 219 220 u32 pch_src_uuid_lo_read(struct pci_dev *pdev) 221 { 222 struct pch_dev *chip = pci_get_drvdata(pdev); 223 u32 val; 224 225 val = ioread32(&chip->regs->src_uuid_lo); 226 227 return val; 228 } 229 EXPORT_SYMBOL(pch_src_uuid_lo_read); 230 231 u32 pch_src_uuid_hi_read(struct pci_dev *pdev) 232 { 233 struct pch_dev *chip = pci_get_drvdata(pdev); 234 u32 val; 235 236 val = ioread32(&chip->regs->src_uuid_hi); 237 238 return val; 239 } 240 EXPORT_SYMBOL(pch_src_uuid_hi_read); 241 242 u64 pch_rx_snap_read(struct pci_dev *pdev) 243 { 244 struct pch_dev *chip = pci_get_drvdata(pdev); 245 u64 ns; 246 u32 lo, hi; 247 248 lo = ioread32(&chip->regs->rx_snap_lo); 249 hi = ioread32(&chip->regs->rx_snap_hi); 250 251 ns = ((u64) hi) << 32; 252 ns |= lo; 253 ns <<= TICKS_NS_SHIFT; 254 255 return ns; 256 } 257 EXPORT_SYMBOL(pch_rx_snap_read); 258 259 u64 pch_tx_snap_read(struct pci_dev *pdev) 260 { 261 struct pch_dev *chip = pci_get_drvdata(pdev); 262 u64 ns; 263 u32 lo, hi; 264 265 lo = ioread32(&chip->regs->tx_snap_lo); 266 hi = ioread32(&chip->regs->tx_snap_hi); 267 268 ns = ((u64) hi) << 32; 269 ns |= lo; 270 ns <<= TICKS_NS_SHIFT; 271 272 return ns; 273 } 274 EXPORT_SYMBOL(pch_tx_snap_read); 275 276 /* This function enables all 64 bits in system time registers [high & low]. 277 This is a work-around for non continuous value in the SystemTime Register*/ 278 static void pch_set_system_time_count(struct pch_dev *chip) 279 { 280 iowrite32(0x01, &chip->regs->stl_max_set_en); 281 iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set); 282 iowrite32(0x00, &chip->regs->stl_max_set_en); 283 } 284 285 static void pch_reset(struct pch_dev *chip) 286 { 287 /* Reset Hardware Assist */ 288 pch_block_reset(chip); 289 290 /* enable all 32 bits in system time registers */ 291 pch_set_system_time_count(chip); 292 } 293 294 /** 295 * pch_set_station_address() - This API sets the station address used by 296 * IEEE 1588 hardware when looking at PTP 297 * traffic on the ethernet interface 298 * @addr: dress which contain the column separated address to be used. 299 */ 300 int pch_set_station_address(u8 *addr, struct pci_dev *pdev) 301 { 302 s32 i; 303 struct pch_dev *chip = pci_get_drvdata(pdev); 304 305 /* Verify the parameter */ 306 if ((chip->regs == NULL) || addr == (u8 *)NULL) { 307 dev_err(&pdev->dev, 308 "invalid params returning PCH_INVALIDPARAM\n"); 309 return PCH_INVALIDPARAM; 310 } 311 /* For all station address bytes */ 312 for (i = 0; i < PCH_STATION_BYTES; i++) { 313 u32 val; 314 s32 tmp; 315 316 tmp = hex_to_bin(addr[i * 3]); 317 if (tmp < 0) { 318 dev_err(&pdev->dev, 319 "invalid params returning PCH_INVALIDPARAM\n"); 320 return PCH_INVALIDPARAM; 321 } 322 val = tmp * 16; 323 tmp = hex_to_bin(addr[(i * 3) + 1]); 324 if (tmp < 0) { 325 dev_err(&pdev->dev, 326 "invalid params returning PCH_INVALIDPARAM\n"); 327 return PCH_INVALIDPARAM; 328 } 329 val += tmp; 330 /* Expects ':' separated addresses */ 331 if ((i < 5) && (addr[(i * 3) + 2] != ':')) { 332 dev_err(&pdev->dev, 333 "invalid params returning PCH_INVALIDPARAM\n"); 334 return PCH_INVALIDPARAM; 335 } 336 337 /* Ideally we should set the address only after validating 338 entire string */ 339 dev_dbg(&pdev->dev, "invoking pch_station_set\n"); 340 iowrite32(val, &chip->regs->ts_st[i]); 341 } 342 return 0; 343 } 344 EXPORT_SYMBOL(pch_set_station_address); 345 346 /* 347 * Interrupt service routine 348 */ 349 static irqreturn_t isr(int irq, void *priv) 350 { 351 struct pch_dev *pch_dev = priv; 352 struct pch_ts_regs __iomem *regs = pch_dev->regs; 353 struct ptp_clock_event event; 354 u32 ack = 0, lo, hi, val; 355 356 val = ioread32(®s->event); 357 358 if (val & PCH_TSE_SNS) { 359 ack |= PCH_TSE_SNS; 360 if (pch_dev->exts0_enabled) { 361 hi = ioread32(®s->asms_hi); 362 lo = ioread32(®s->asms_lo); 363 event.type = PTP_CLOCK_EXTTS; 364 event.index = 0; 365 event.timestamp = ((u64) hi) << 32; 366 event.timestamp |= lo; 367 event.timestamp <<= TICKS_NS_SHIFT; 368 ptp_clock_event(pch_dev->ptp_clock, &event); 369 } 370 } 371 372 if (val & PCH_TSE_SNM) { 373 ack |= PCH_TSE_SNM; 374 if (pch_dev->exts1_enabled) { 375 hi = ioread32(®s->amms_hi); 376 lo = ioread32(®s->amms_lo); 377 event.type = PTP_CLOCK_EXTTS; 378 event.index = 1; 379 event.timestamp = ((u64) hi) << 32; 380 event.timestamp |= lo; 381 event.timestamp <<= TICKS_NS_SHIFT; 382 ptp_clock_event(pch_dev->ptp_clock, &event); 383 } 384 } 385 386 if (val & PCH_TSE_TTIPEND) 387 ack |= PCH_TSE_TTIPEND; /* this bit seems to be always set */ 388 389 if (ack) { 390 iowrite32(ack, ®s->event); 391 return IRQ_HANDLED; 392 } else 393 return IRQ_NONE; 394 } 395 396 /* 397 * PTP clock operations 398 */ 399 400 static int ptp_pch_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 401 { 402 u64 adj; 403 u32 diff, addend; 404 int neg_adj = 0; 405 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps); 406 struct pch_ts_regs __iomem *regs = pch_dev->regs; 407 408 if (ppb < 0) { 409 neg_adj = 1; 410 ppb = -ppb; 411 } 412 addend = DEFAULT_ADDEND; 413 adj = addend; 414 adj *= ppb; 415 diff = div_u64(adj, 1000000000ULL); 416 417 addend = neg_adj ? addend - diff : addend + diff; 418 419 iowrite32(addend, ®s->addend); 420 421 return 0; 422 } 423 424 static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta) 425 { 426 s64 now; 427 unsigned long flags; 428 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps); 429 struct pch_ts_regs __iomem *regs = pch_dev->regs; 430 431 spin_lock_irqsave(&pch_dev->register_lock, flags); 432 now = pch_systime_read(regs); 433 now += delta; 434 pch_systime_write(regs, now); 435 spin_unlock_irqrestore(&pch_dev->register_lock, flags); 436 437 return 0; 438 } 439 440 static int ptp_pch_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 441 { 442 u64 ns; 443 unsigned long flags; 444 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps); 445 struct pch_ts_regs __iomem *regs = pch_dev->regs; 446 447 spin_lock_irqsave(&pch_dev->register_lock, flags); 448 ns = pch_systime_read(regs); 449 spin_unlock_irqrestore(&pch_dev->register_lock, flags); 450 451 *ts = ns_to_timespec64(ns); 452 return 0; 453 } 454 455 static int ptp_pch_settime(struct ptp_clock_info *ptp, 456 const struct timespec64 *ts) 457 { 458 u64 ns; 459 unsigned long flags; 460 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps); 461 struct pch_ts_regs __iomem *regs = pch_dev->regs; 462 463 ns = timespec64_to_ns(ts); 464 465 spin_lock_irqsave(&pch_dev->register_lock, flags); 466 pch_systime_write(regs, ns); 467 spin_unlock_irqrestore(&pch_dev->register_lock, flags); 468 469 return 0; 470 } 471 472 static int ptp_pch_enable(struct ptp_clock_info *ptp, 473 struct ptp_clock_request *rq, int on) 474 { 475 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps); 476 477 switch (rq->type) { 478 case PTP_CLK_REQ_EXTTS: 479 switch (rq->extts.index) { 480 case 0: 481 pch_dev->exts0_enabled = on ? 1 : 0; 482 break; 483 case 1: 484 pch_dev->exts1_enabled = on ? 1 : 0; 485 break; 486 default: 487 return -EINVAL; 488 } 489 return 0; 490 default: 491 break; 492 } 493 494 return -EOPNOTSUPP; 495 } 496 497 static const struct ptp_clock_info ptp_pch_caps = { 498 .owner = THIS_MODULE, 499 .name = "PCH timer", 500 .max_adj = 50000000, 501 .n_ext_ts = N_EXT_TS, 502 .n_pins = 0, 503 .pps = 0, 504 .adjfreq = ptp_pch_adjfreq, 505 .adjtime = ptp_pch_adjtime, 506 .gettime64 = ptp_pch_gettime, 507 .settime64 = ptp_pch_settime, 508 .enable = ptp_pch_enable, 509 }; 510 511 512 #ifdef CONFIG_PM 513 static s32 pch_suspend(struct pci_dev *pdev, pm_message_t state) 514 { 515 pci_disable_device(pdev); 516 pci_enable_wake(pdev, PCI_D3hot, 0); 517 518 if (pci_save_state(pdev) != 0) { 519 dev_err(&pdev->dev, "could not save PCI config state\n"); 520 return -ENOMEM; 521 } 522 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 523 524 return 0; 525 } 526 527 static s32 pch_resume(struct pci_dev *pdev) 528 { 529 s32 ret; 530 531 pci_set_power_state(pdev, PCI_D0); 532 pci_restore_state(pdev); 533 ret = pci_enable_device(pdev); 534 if (ret) { 535 dev_err(&pdev->dev, "pci_enable_device failed\n"); 536 return ret; 537 } 538 pci_enable_wake(pdev, PCI_D3hot, 0); 539 return 0; 540 } 541 #else 542 #define pch_suspend NULL 543 #define pch_resume NULL 544 #endif 545 546 static void pch_remove(struct pci_dev *pdev) 547 { 548 struct pch_dev *chip = pci_get_drvdata(pdev); 549 550 ptp_clock_unregister(chip->ptp_clock); 551 /* free the interrupt */ 552 if (pdev->irq != 0) 553 free_irq(pdev->irq, chip); 554 555 /* unmap the virtual IO memory space */ 556 if (chip->regs != NULL) { 557 iounmap(chip->regs); 558 chip->regs = NULL; 559 } 560 /* release the reserved IO memory space */ 561 if (chip->mem_base != 0) { 562 release_mem_region(chip->mem_base, chip->mem_size); 563 chip->mem_base = 0; 564 } 565 pci_disable_device(pdev); 566 kfree(chip); 567 dev_info(&pdev->dev, "complete\n"); 568 } 569 570 static s32 571 pch_probe(struct pci_dev *pdev, const struct pci_device_id *id) 572 { 573 s32 ret; 574 unsigned long flags; 575 struct pch_dev *chip; 576 577 chip = kzalloc(sizeof(struct pch_dev), GFP_KERNEL); 578 if (chip == NULL) 579 return -ENOMEM; 580 581 /* enable the 1588 pci device */ 582 ret = pci_enable_device(pdev); 583 if (ret != 0) { 584 dev_err(&pdev->dev, "could not enable the pci device\n"); 585 goto err_pci_en; 586 } 587 588 chip->mem_base = pci_resource_start(pdev, IO_MEM_BAR); 589 if (!chip->mem_base) { 590 dev_err(&pdev->dev, "could not locate IO memory address\n"); 591 ret = -ENODEV; 592 goto err_pci_start; 593 } 594 595 /* retrieve the available length of the IO memory space */ 596 chip->mem_size = pci_resource_len(pdev, IO_MEM_BAR); 597 598 /* allocate the memory for the device registers */ 599 if (!request_mem_region(chip->mem_base, chip->mem_size, "1588_regs")) { 600 dev_err(&pdev->dev, 601 "could not allocate register memory space\n"); 602 ret = -EBUSY; 603 goto err_req_mem_region; 604 } 605 606 /* get the virtual address to the 1588 registers */ 607 chip->regs = ioremap(chip->mem_base, chip->mem_size); 608 609 if (!chip->regs) { 610 dev_err(&pdev->dev, "Could not get virtual address\n"); 611 ret = -ENOMEM; 612 goto err_ioremap; 613 } 614 615 chip->caps = ptp_pch_caps; 616 chip->ptp_clock = ptp_clock_register(&chip->caps, &pdev->dev); 617 if (IS_ERR(chip->ptp_clock)) { 618 ret = PTR_ERR(chip->ptp_clock); 619 goto err_ptp_clock_reg; 620 } 621 622 spin_lock_init(&chip->register_lock); 623 624 ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip); 625 if (ret != 0) { 626 dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq); 627 goto err_req_irq; 628 } 629 630 /* indicate success */ 631 chip->irq = pdev->irq; 632 chip->pdev = pdev; 633 pci_set_drvdata(pdev, chip); 634 635 spin_lock_irqsave(&chip->register_lock, flags); 636 /* reset the ieee1588 h/w */ 637 pch_reset(chip); 638 639 iowrite32(DEFAULT_ADDEND, &chip->regs->addend); 640 iowrite32(1, &chip->regs->trgt_lo); 641 iowrite32(0, &chip->regs->trgt_hi); 642 iowrite32(PCH_TSE_TTIPEND, &chip->regs->event); 643 644 pch_eth_enable_set(chip); 645 646 if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) { 647 if (pch_set_station_address(pch_param.station, pdev) != 0) { 648 dev_err(&pdev->dev, 649 "Invalid station address parameter\n" 650 "Module loaded but station address not set correctly\n" 651 ); 652 } 653 } 654 spin_unlock_irqrestore(&chip->register_lock, flags); 655 return 0; 656 657 err_req_irq: 658 ptp_clock_unregister(chip->ptp_clock); 659 err_ptp_clock_reg: 660 iounmap(chip->regs); 661 chip->regs = NULL; 662 663 err_ioremap: 664 release_mem_region(chip->mem_base, chip->mem_size); 665 666 err_req_mem_region: 667 chip->mem_base = 0; 668 669 err_pci_start: 670 pci_disable_device(pdev); 671 672 err_pci_en: 673 kfree(chip); 674 dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret); 675 676 return ret; 677 } 678 679 static const struct pci_device_id pch_ieee1588_pcidev_id[] = { 680 { 681 .vendor = PCI_VENDOR_ID_INTEL, 682 .device = PCI_DEVICE_ID_PCH_1588 683 }, 684 {0} 685 }; 686 687 static struct pci_driver pch_driver = { 688 .name = KBUILD_MODNAME, 689 .id_table = pch_ieee1588_pcidev_id, 690 .probe = pch_probe, 691 .remove = pch_remove, 692 .suspend = pch_suspend, 693 .resume = pch_resume, 694 }; 695 696 static void __exit ptp_pch_exit(void) 697 { 698 pci_unregister_driver(&pch_driver); 699 } 700 701 static s32 __init ptp_pch_init(void) 702 { 703 s32 ret; 704 705 /* register the driver with the pci core */ 706 ret = pci_register_driver(&pch_driver); 707 708 return ret; 709 } 710 711 module_init(ptp_pch_init); 712 module_exit(ptp_pch_exit); 713 714 module_param_string(station, 715 pch_param.station, sizeof(pch_param.station), 0444); 716 MODULE_PARM_DESC(station, 717 "IEEE 1588 station address to use - colon separated hex values"); 718 719 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>"); 720 MODULE_DESCRIPTION("PTP clock using the EG20T timer"); 721 MODULE_LICENSE("GPL"); 722