xref: /openbmc/linux/drivers/ptp/ptp_ocp.c (revision 54a611b6)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
3 
4 #include <linux/bits.h>
5 #include <linux/err.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/ptp_clock_kernel.h>
17 #include <linux/spi/spi.h>
18 #include <linux/spi/xilinx_spi.h>
19 #include <net/devlink.h>
20 #include <linux/i2c.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/nvmem-consumer.h>
23 #include <linux/crc16.h>
24 
25 #define PCI_VENDOR_ID_FACEBOOK			0x1d9b
26 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD		0x0400
27 
28 #define PCI_VENDOR_ID_CELESTICA			0x18d4
29 #define PCI_DEVICE_ID_CELESTICA_TIMECARD	0x1008
30 
31 static struct class timecard_class = {
32 	.owner		= THIS_MODULE,
33 	.name		= "timecard",
34 };
35 
36 struct ocp_reg {
37 	u32	ctrl;
38 	u32	status;
39 	u32	select;
40 	u32	version;
41 	u32	time_ns;
42 	u32	time_sec;
43 	u32	__pad0[2];
44 	u32	adjust_ns;
45 	u32	adjust_sec;
46 	u32	__pad1[2];
47 	u32	offset_ns;
48 	u32	offset_window_ns;
49 	u32	__pad2[2];
50 	u32	drift_ns;
51 	u32	drift_window_ns;
52 	u32	__pad3[6];
53 	u32	servo_offset_p;
54 	u32	servo_offset_i;
55 	u32	servo_drift_p;
56 	u32	servo_drift_i;
57 	u32	status_offset;
58 	u32	status_drift;
59 };
60 
61 #define OCP_CTRL_ENABLE		BIT(0)
62 #define OCP_CTRL_ADJUST_TIME	BIT(1)
63 #define OCP_CTRL_ADJUST_OFFSET	BIT(2)
64 #define OCP_CTRL_ADJUST_DRIFT	BIT(3)
65 #define OCP_CTRL_ADJUST_SERVO	BIT(8)
66 #define OCP_CTRL_READ_TIME_REQ	BIT(30)
67 #define OCP_CTRL_READ_TIME_DONE	BIT(31)
68 
69 #define OCP_STATUS_IN_SYNC	BIT(0)
70 #define OCP_STATUS_IN_HOLDOVER	BIT(1)
71 
72 #define OCP_SELECT_CLK_NONE	0
73 #define OCP_SELECT_CLK_REG	0xfe
74 
75 struct tod_reg {
76 	u32	ctrl;
77 	u32	status;
78 	u32	uart_polarity;
79 	u32	version;
80 	u32	adj_sec;
81 	u32	__pad0[3];
82 	u32	uart_baud;
83 	u32	__pad1[3];
84 	u32	utc_status;
85 	u32	leap;
86 };
87 
88 #define TOD_CTRL_PROTOCOL	BIT(28)
89 #define TOD_CTRL_DISABLE_FMT_A	BIT(17)
90 #define TOD_CTRL_DISABLE_FMT_B	BIT(16)
91 #define TOD_CTRL_ENABLE		BIT(0)
92 #define TOD_CTRL_GNSS_MASK	GENMASK(3, 0)
93 #define TOD_CTRL_GNSS_SHIFT	24
94 
95 #define TOD_STATUS_UTC_MASK		GENMASK(7, 0)
96 #define TOD_STATUS_UTC_VALID		BIT(8)
97 #define TOD_STATUS_LEAP_ANNOUNCE	BIT(12)
98 #define TOD_STATUS_LEAP_VALID		BIT(16)
99 
100 struct ts_reg {
101 	u32	enable;
102 	u32	error;
103 	u32	polarity;
104 	u32	version;
105 	u32	__pad0[4];
106 	u32	cable_delay;
107 	u32	__pad1[3];
108 	u32	intr;
109 	u32	intr_mask;
110 	u32	event_count;
111 	u32	__pad2[1];
112 	u32	ts_count;
113 	u32	time_ns;
114 	u32	time_sec;
115 	u32	data_width;
116 	u32	data;
117 };
118 
119 struct pps_reg {
120 	u32	ctrl;
121 	u32	status;
122 	u32	__pad0[6];
123 	u32	cable_delay;
124 };
125 
126 #define PPS_STATUS_FILTER_ERR	BIT(0)
127 #define PPS_STATUS_SUPERV_ERR	BIT(1)
128 
129 struct img_reg {
130 	u32	version;
131 };
132 
133 struct gpio_reg {
134 	u32	gpio1;
135 	u32	__pad0;
136 	u32	gpio2;
137 	u32	__pad1;
138 };
139 
140 struct irig_master_reg {
141 	u32	ctrl;
142 	u32	status;
143 	u32	__pad0;
144 	u32	version;
145 	u32	adj_sec;
146 	u32	mode_ctrl;
147 };
148 
149 #define IRIG_M_CTRL_ENABLE	BIT(0)
150 
151 struct irig_slave_reg {
152 	u32	ctrl;
153 	u32	status;
154 	u32	__pad0;
155 	u32	version;
156 	u32	adj_sec;
157 	u32	mode_ctrl;
158 };
159 
160 #define IRIG_S_CTRL_ENABLE	BIT(0)
161 
162 struct dcf_master_reg {
163 	u32	ctrl;
164 	u32	status;
165 	u32	__pad0;
166 	u32	version;
167 	u32	adj_sec;
168 };
169 
170 #define DCF_M_CTRL_ENABLE	BIT(0)
171 
172 struct dcf_slave_reg {
173 	u32	ctrl;
174 	u32	status;
175 	u32	__pad0;
176 	u32	version;
177 	u32	adj_sec;
178 };
179 
180 #define DCF_S_CTRL_ENABLE	BIT(0)
181 
182 struct signal_reg {
183 	u32	enable;
184 	u32	status;
185 	u32	polarity;
186 	u32	version;
187 	u32	__pad0[4];
188 	u32	cable_delay;
189 	u32	__pad1[3];
190 	u32	intr;
191 	u32	intr_mask;
192 	u32	__pad2[2];
193 	u32	start_ns;
194 	u32	start_sec;
195 	u32	pulse_ns;
196 	u32	pulse_sec;
197 	u32	period_ns;
198 	u32	period_sec;
199 	u32	repeat_count;
200 };
201 
202 struct frequency_reg {
203 	u32	ctrl;
204 	u32	status;
205 };
206 #define FREQ_STATUS_VALID	BIT(31)
207 #define FREQ_STATUS_ERROR	BIT(30)
208 #define FREQ_STATUS_OVERRUN	BIT(29)
209 #define FREQ_STATUS_MASK	GENMASK(23, 0)
210 
211 struct ptp_ocp_flash_info {
212 	const char *name;
213 	int pci_offset;
214 	int data_size;
215 	void *data;
216 };
217 
218 struct ptp_ocp_firmware_header {
219 	char magic[4];
220 	__be16 pci_vendor_id;
221 	__be16 pci_device_id;
222 	__be32 image_size;
223 	__be16 hw_revision;
224 	__be16 crc;
225 };
226 
227 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
228 
229 struct ptp_ocp_i2c_info {
230 	const char *name;
231 	unsigned long fixed_rate;
232 	size_t data_size;
233 	void *data;
234 };
235 
236 struct ptp_ocp_ext_info {
237 	int index;
238 	irqreturn_t (*irq_fcn)(int irq, void *priv);
239 	int (*enable)(void *priv, u32 req, bool enable);
240 };
241 
242 struct ptp_ocp_ext_src {
243 	void __iomem		*mem;
244 	struct ptp_ocp		*bp;
245 	struct ptp_ocp_ext_info	*info;
246 	int			irq_vec;
247 };
248 
249 enum ptp_ocp_sma_mode {
250 	SMA_MODE_IN,
251 	SMA_MODE_OUT,
252 };
253 
254 struct ptp_ocp_sma_connector {
255 	enum	ptp_ocp_sma_mode mode;
256 	bool	fixed_fcn;
257 	bool	fixed_dir;
258 	bool	disabled;
259 	u8	default_fcn;
260 };
261 
262 struct ocp_attr_group {
263 	u64 cap;
264 	const struct attribute_group *group;
265 };
266 
267 #define OCP_CAP_BASIC	BIT(0)
268 #define OCP_CAP_SIGNAL	BIT(1)
269 #define OCP_CAP_FREQ	BIT(2)
270 
271 struct ptp_ocp_signal {
272 	ktime_t		period;
273 	ktime_t		pulse;
274 	ktime_t		phase;
275 	ktime_t		start;
276 	int		duty;
277 	bool		polarity;
278 	bool		running;
279 };
280 
281 #define OCP_BOARD_ID_LEN		13
282 #define OCP_SERIAL_LEN			6
283 
284 struct ptp_ocp {
285 	struct pci_dev		*pdev;
286 	struct device		dev;
287 	spinlock_t		lock;
288 	struct ocp_reg __iomem	*reg;
289 	struct tod_reg __iomem	*tod;
290 	struct pps_reg __iomem	*pps_to_ext;
291 	struct pps_reg __iomem	*pps_to_clk;
292 	struct gpio_reg __iomem	*pps_select;
293 	struct gpio_reg __iomem	*sma_map1;
294 	struct gpio_reg __iomem	*sma_map2;
295 	struct irig_master_reg	__iomem *irig_out;
296 	struct irig_slave_reg	__iomem *irig_in;
297 	struct dcf_master_reg	__iomem *dcf_out;
298 	struct dcf_slave_reg	__iomem *dcf_in;
299 	struct tod_reg		__iomem *nmea_out;
300 	struct frequency_reg	__iomem *freq_in[4];
301 	struct ptp_ocp_ext_src	*signal_out[4];
302 	struct ptp_ocp_ext_src	*pps;
303 	struct ptp_ocp_ext_src	*ts0;
304 	struct ptp_ocp_ext_src	*ts1;
305 	struct ptp_ocp_ext_src	*ts2;
306 	struct ptp_ocp_ext_src	*ts3;
307 	struct ptp_ocp_ext_src	*ts4;
308 	struct img_reg __iomem	*image;
309 	struct ptp_clock	*ptp;
310 	struct ptp_clock_info	ptp_info;
311 	struct platform_device	*i2c_ctrl;
312 	struct platform_device	*spi_flash;
313 	struct clk_hw		*i2c_clk;
314 	struct timer_list	watchdog;
315 	const struct attribute_group **attr_group;
316 	const struct ptp_ocp_eeprom_map *eeprom_map;
317 	struct dentry		*debug_root;
318 	time64_t		gnss_lost;
319 	int			id;
320 	int			n_irqs;
321 	int			gnss_port;
322 	int			gnss2_port;
323 	int			mac_port;	/* miniature atomic clock */
324 	int			nmea_port;
325 	bool			fw_loader;
326 	u8			fw_tag;
327 	u16			fw_version;
328 	u8			board_id[OCP_BOARD_ID_LEN];
329 	u8			serial[OCP_SERIAL_LEN];
330 	bool			has_eeprom_data;
331 	u32			pps_req_map;
332 	int			flash_start;
333 	u32			utc_tai_offset;
334 	u32			ts_window_adjust;
335 	u64			fw_cap;
336 	struct ptp_ocp_signal	signal[4];
337 	struct ptp_ocp_sma_connector sma[4];
338 	const struct ocp_sma_op *sma_op;
339 };
340 
341 #define OCP_REQ_TIMESTAMP	BIT(0)
342 #define OCP_REQ_PPS		BIT(1)
343 
344 struct ocp_resource {
345 	unsigned long offset;
346 	int size;
347 	int irq_vec;
348 	int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
349 	void *extra;
350 	unsigned long bp_offset;
351 	const char * const name;
352 };
353 
354 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
355 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
356 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
357 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
358 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
359 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
360 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
361 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
362 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
363 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
364 				      struct ptp_perout_request *req);
365 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
366 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
367 
368 static const struct ocp_attr_group fb_timecard_groups[];
369 
370 struct ptp_ocp_eeprom_map {
371 	u16	off;
372 	u16	len;
373 	u32	bp_offset;
374 	const void * const tag;
375 };
376 
377 #define EEPROM_ENTRY(addr, member)				\
378 	.off = addr,						\
379 	.len = sizeof_field(struct ptp_ocp, member),		\
380 	.bp_offset = offsetof(struct ptp_ocp, member)
381 
382 #define BP_MAP_ENTRY_ADDR(bp, map) ({				\
383 	(void *)((uintptr_t)(bp) + (map)->bp_offset);		\
384 })
385 
386 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
387 	{ EEPROM_ENTRY(0x43, board_id) },
388 	{ EEPROM_ENTRY(0x00, serial), .tag = "mac" },
389 	{ }
390 };
391 
392 #define bp_assign_entry(bp, res, val) ({				\
393 	uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset;		\
394 	*(typeof(val) *)addr = val;					\
395 })
396 
397 #define OCP_RES_LOCATION(member) \
398 	.name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
399 
400 #define OCP_MEM_RESOURCE(member) \
401 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
402 
403 #define OCP_SERIAL_RESOURCE(member) \
404 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
405 
406 #define OCP_I2C_RESOURCE(member) \
407 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
408 
409 #define OCP_SPI_RESOURCE(member) \
410 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
411 
412 #define OCP_EXT_RESOURCE(member) \
413 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
414 
415 /* This is the MSI vector mapping used.
416  * 0: PPS (TS5)
417  * 1: TS0
418  * 2: TS1
419  * 3: GNSS1
420  * 4: GNSS2
421  * 5: MAC
422  * 6: TS2
423  * 7: I2C controller
424  * 8: HWICAP (notused)
425  * 9: SPI Flash
426  * 10: NMEA
427  * 11: Signal Generator 1
428  * 12: Signal Generator 2
429  * 13: Signal Generator 3
430  * 14: Signal Generator 4
431  * 15: TS3
432  * 16: TS4
433  */
434 
435 static struct ocp_resource ocp_fb_resource[] = {
436 	{
437 		OCP_MEM_RESOURCE(reg),
438 		.offset = 0x01000000, .size = 0x10000,
439 	},
440 	{
441 		OCP_EXT_RESOURCE(ts0),
442 		.offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
443 		.extra = &(struct ptp_ocp_ext_info) {
444 			.index = 0,
445 			.irq_fcn = ptp_ocp_ts_irq,
446 			.enable = ptp_ocp_ts_enable,
447 		},
448 	},
449 	{
450 		OCP_EXT_RESOURCE(ts1),
451 		.offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
452 		.extra = &(struct ptp_ocp_ext_info) {
453 			.index = 1,
454 			.irq_fcn = ptp_ocp_ts_irq,
455 			.enable = ptp_ocp_ts_enable,
456 		},
457 	},
458 	{
459 		OCP_EXT_RESOURCE(ts2),
460 		.offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
461 		.extra = &(struct ptp_ocp_ext_info) {
462 			.index = 2,
463 			.irq_fcn = ptp_ocp_ts_irq,
464 			.enable = ptp_ocp_ts_enable,
465 		},
466 	},
467 	{
468 		OCP_EXT_RESOURCE(ts3),
469 		.offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
470 		.extra = &(struct ptp_ocp_ext_info) {
471 			.index = 3,
472 			.irq_fcn = ptp_ocp_ts_irq,
473 			.enable = ptp_ocp_ts_enable,
474 		},
475 	},
476 	{
477 		OCP_EXT_RESOURCE(ts4),
478 		.offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
479 		.extra = &(struct ptp_ocp_ext_info) {
480 			.index = 4,
481 			.irq_fcn = ptp_ocp_ts_irq,
482 			.enable = ptp_ocp_ts_enable,
483 		},
484 	},
485 	/* Timestamp for PHC and/or PPS generator */
486 	{
487 		OCP_EXT_RESOURCE(pps),
488 		.offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
489 		.extra = &(struct ptp_ocp_ext_info) {
490 			.index = 5,
491 			.irq_fcn = ptp_ocp_ts_irq,
492 			.enable = ptp_ocp_ts_enable,
493 		},
494 	},
495 	{
496 		OCP_EXT_RESOURCE(signal_out[0]),
497 		.offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
498 		.extra = &(struct ptp_ocp_ext_info) {
499 			.index = 1,
500 			.irq_fcn = ptp_ocp_signal_irq,
501 			.enable = ptp_ocp_signal_enable,
502 		},
503 	},
504 	{
505 		OCP_EXT_RESOURCE(signal_out[1]),
506 		.offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
507 		.extra = &(struct ptp_ocp_ext_info) {
508 			.index = 2,
509 			.irq_fcn = ptp_ocp_signal_irq,
510 			.enable = ptp_ocp_signal_enable,
511 		},
512 	},
513 	{
514 		OCP_EXT_RESOURCE(signal_out[2]),
515 		.offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
516 		.extra = &(struct ptp_ocp_ext_info) {
517 			.index = 3,
518 			.irq_fcn = ptp_ocp_signal_irq,
519 			.enable = ptp_ocp_signal_enable,
520 		},
521 	},
522 	{
523 		OCP_EXT_RESOURCE(signal_out[3]),
524 		.offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
525 		.extra = &(struct ptp_ocp_ext_info) {
526 			.index = 4,
527 			.irq_fcn = ptp_ocp_signal_irq,
528 			.enable = ptp_ocp_signal_enable,
529 		},
530 	},
531 	{
532 		OCP_MEM_RESOURCE(pps_to_ext),
533 		.offset = 0x01030000, .size = 0x10000,
534 	},
535 	{
536 		OCP_MEM_RESOURCE(pps_to_clk),
537 		.offset = 0x01040000, .size = 0x10000,
538 	},
539 	{
540 		OCP_MEM_RESOURCE(tod),
541 		.offset = 0x01050000, .size = 0x10000,
542 	},
543 	{
544 		OCP_MEM_RESOURCE(irig_in),
545 		.offset = 0x01070000, .size = 0x10000,
546 	},
547 	{
548 		OCP_MEM_RESOURCE(irig_out),
549 		.offset = 0x01080000, .size = 0x10000,
550 	},
551 	{
552 		OCP_MEM_RESOURCE(dcf_in),
553 		.offset = 0x01090000, .size = 0x10000,
554 	},
555 	{
556 		OCP_MEM_RESOURCE(dcf_out),
557 		.offset = 0x010A0000, .size = 0x10000,
558 	},
559 	{
560 		OCP_MEM_RESOURCE(nmea_out),
561 		.offset = 0x010B0000, .size = 0x10000,
562 	},
563 	{
564 		OCP_MEM_RESOURCE(image),
565 		.offset = 0x00020000, .size = 0x1000,
566 	},
567 	{
568 		OCP_MEM_RESOURCE(pps_select),
569 		.offset = 0x00130000, .size = 0x1000,
570 	},
571 	{
572 		OCP_MEM_RESOURCE(sma_map1),
573 		.offset = 0x00140000, .size = 0x1000,
574 	},
575 	{
576 		OCP_MEM_RESOURCE(sma_map2),
577 		.offset = 0x00220000, .size = 0x1000,
578 	},
579 	{
580 		OCP_I2C_RESOURCE(i2c_ctrl),
581 		.offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
582 		.extra = &(struct ptp_ocp_i2c_info) {
583 			.name = "xiic-i2c",
584 			.fixed_rate = 50000000,
585 			.data_size = sizeof(struct xiic_i2c_platform_data),
586 			.data = &(struct xiic_i2c_platform_data) {
587 				.num_devices = 2,
588 				.devices = (struct i2c_board_info[]) {
589 					{ I2C_BOARD_INFO("24c02", 0x50) },
590 					{ I2C_BOARD_INFO("24mac402", 0x58),
591 					  .platform_data = "mac" },
592 				},
593 			},
594 		},
595 	},
596 	{
597 		OCP_SERIAL_RESOURCE(gnss_port),
598 		.offset = 0x00160000 + 0x1000, .irq_vec = 3,
599 	},
600 	{
601 		OCP_SERIAL_RESOURCE(gnss2_port),
602 		.offset = 0x00170000 + 0x1000, .irq_vec = 4,
603 	},
604 	{
605 		OCP_SERIAL_RESOURCE(mac_port),
606 		.offset = 0x00180000 + 0x1000, .irq_vec = 5,
607 	},
608 	{
609 		OCP_SERIAL_RESOURCE(nmea_port),
610 		.offset = 0x00190000 + 0x1000, .irq_vec = 10,
611 	},
612 	{
613 		OCP_SPI_RESOURCE(spi_flash),
614 		.offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
615 		.extra = &(struct ptp_ocp_flash_info) {
616 			.name = "xilinx_spi", .pci_offset = 0,
617 			.data_size = sizeof(struct xspi_platform_data),
618 			.data = &(struct xspi_platform_data) {
619 				.num_chipselect = 1,
620 				.bits_per_word = 8,
621 				.num_devices = 1,
622 				.devices = &(struct spi_board_info) {
623 					.modalias = "spi-nor",
624 				},
625 			},
626 		},
627 	},
628 	{
629 		OCP_MEM_RESOURCE(freq_in[0]),
630 		.offset = 0x01200000, .size = 0x10000,
631 	},
632 	{
633 		OCP_MEM_RESOURCE(freq_in[1]),
634 		.offset = 0x01210000, .size = 0x10000,
635 	},
636 	{
637 		OCP_MEM_RESOURCE(freq_in[2]),
638 		.offset = 0x01220000, .size = 0x10000,
639 	},
640 	{
641 		OCP_MEM_RESOURCE(freq_in[3]),
642 		.offset = 0x01230000, .size = 0x10000,
643 	},
644 	{
645 		.setup = ptp_ocp_fb_board_init,
646 	},
647 	{ }
648 };
649 
650 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
651 	{ PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
652 	{ PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
653 	{ }
654 };
655 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
656 
657 static DEFINE_MUTEX(ptp_ocp_lock);
658 static DEFINE_IDR(ptp_ocp_idr);
659 
660 struct ocp_selector {
661 	const char *name;
662 	int value;
663 };
664 
665 static const struct ocp_selector ptp_ocp_clock[] = {
666 	{ .name = "NONE",	.value = 0 },
667 	{ .name = "TOD",	.value = 1 },
668 	{ .name = "IRIG",	.value = 2 },
669 	{ .name = "PPS",	.value = 3 },
670 	{ .name = "PTP",	.value = 4 },
671 	{ .name = "RTC",	.value = 5 },
672 	{ .name = "DCF",	.value = 6 },
673 	{ .name = "REGS",	.value = 0xfe },
674 	{ .name = "EXT",	.value = 0xff },
675 	{ }
676 };
677 
678 #define SMA_DISABLE		BIT(16)
679 #define SMA_ENABLE		BIT(15)
680 #define SMA_SELECT_MASK		GENMASK(14, 0)
681 
682 static const struct ocp_selector ptp_ocp_sma_in[] = {
683 	{ .name = "10Mhz",	.value = 0x0000 },
684 	{ .name = "PPS1",	.value = 0x0001 },
685 	{ .name = "PPS2",	.value = 0x0002 },
686 	{ .name = "TS1",	.value = 0x0004 },
687 	{ .name = "TS2",	.value = 0x0008 },
688 	{ .name = "IRIG",	.value = 0x0010 },
689 	{ .name = "DCF",	.value = 0x0020 },
690 	{ .name = "TS3",	.value = 0x0040 },
691 	{ .name = "TS4",	.value = 0x0080 },
692 	{ .name = "FREQ1",	.value = 0x0100 },
693 	{ .name = "FREQ2",	.value = 0x0200 },
694 	{ .name = "FREQ3",	.value = 0x0400 },
695 	{ .name = "FREQ4",	.value = 0x0800 },
696 	{ .name = "None",	.value = SMA_DISABLE },
697 	{ }
698 };
699 
700 static const struct ocp_selector ptp_ocp_sma_out[] = {
701 	{ .name = "10Mhz",	.value = 0x0000 },
702 	{ .name = "PHC",	.value = 0x0001 },
703 	{ .name = "MAC",	.value = 0x0002 },
704 	{ .name = "GNSS1",	.value = 0x0004 },
705 	{ .name = "GNSS2",	.value = 0x0008 },
706 	{ .name = "IRIG",	.value = 0x0010 },
707 	{ .name = "DCF",	.value = 0x0020 },
708 	{ .name = "GEN1",	.value = 0x0040 },
709 	{ .name = "GEN2",	.value = 0x0080 },
710 	{ .name = "GEN3",	.value = 0x0100 },
711 	{ .name = "GEN4",	.value = 0x0200 },
712 	{ .name = "GND",	.value = 0x2000 },
713 	{ .name = "VCC",	.value = 0x4000 },
714 	{ }
715 };
716 
717 struct ocp_sma_op {
718 	const struct ocp_selector *tbl[2];
719 	void (*init)(struct ptp_ocp *bp);
720 	u32 (*get)(struct ptp_ocp *bp, int sma_nr);
721 	int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
722 	int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
723 };
724 
725 static void
726 ptp_ocp_sma_init(struct ptp_ocp *bp)
727 {
728 	return bp->sma_op->init(bp);
729 }
730 
731 static u32
732 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
733 {
734 	return bp->sma_op->get(bp, sma_nr);
735 }
736 
737 static int
738 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
739 {
740 	return bp->sma_op->set_inputs(bp, sma_nr, val);
741 }
742 
743 static int
744 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
745 {
746 	return bp->sma_op->set_output(bp, sma_nr, val);
747 }
748 
749 static const char *
750 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
751 {
752 	int i;
753 
754 	for (i = 0; tbl[i].name; i++)
755 		if (tbl[i].value == val)
756 			return tbl[i].name;
757 	return NULL;
758 }
759 
760 static int
761 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
762 {
763 	const char *select;
764 	int i;
765 
766 	for (i = 0; tbl[i].name; i++) {
767 		select = tbl[i].name;
768 		if (!strncasecmp(name, select, strlen(select)))
769 			return tbl[i].value;
770 	}
771 	return -EINVAL;
772 }
773 
774 static ssize_t
775 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
776 {
777 	ssize_t count;
778 	int i;
779 
780 	count = 0;
781 	for (i = 0; tbl[i].name; i++)
782 		count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
783 	if (count)
784 		count--;
785 	count += sysfs_emit_at(buf, count, "\n");
786 	return count;
787 }
788 
789 static int
790 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
791 			 struct ptp_system_timestamp *sts)
792 {
793 	u32 ctrl, time_sec, time_ns;
794 	int i;
795 
796 	ptp_read_system_prets(sts);
797 
798 	ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
799 	iowrite32(ctrl, &bp->reg->ctrl);
800 
801 	for (i = 0; i < 100; i++) {
802 		ctrl = ioread32(&bp->reg->ctrl);
803 		if (ctrl & OCP_CTRL_READ_TIME_DONE)
804 			break;
805 	}
806 	ptp_read_system_postts(sts);
807 
808 	if (sts && bp->ts_window_adjust) {
809 		s64 ns = timespec64_to_ns(&sts->post_ts);
810 
811 		sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
812 	}
813 
814 	time_ns = ioread32(&bp->reg->time_ns);
815 	time_sec = ioread32(&bp->reg->time_sec);
816 
817 	ts->tv_sec = time_sec;
818 	ts->tv_nsec = time_ns;
819 
820 	return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
821 }
822 
823 static int
824 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
825 		 struct ptp_system_timestamp *sts)
826 {
827 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
828 	unsigned long flags;
829 	int err;
830 
831 	spin_lock_irqsave(&bp->lock, flags);
832 	err = __ptp_ocp_gettime_locked(bp, ts, sts);
833 	spin_unlock_irqrestore(&bp->lock, flags);
834 
835 	return err;
836 }
837 
838 static void
839 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
840 {
841 	u32 ctrl, time_sec, time_ns;
842 	u32 select;
843 
844 	time_ns = ts->tv_nsec;
845 	time_sec = ts->tv_sec;
846 
847 	select = ioread32(&bp->reg->select);
848 	iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
849 
850 	iowrite32(time_ns, &bp->reg->adjust_ns);
851 	iowrite32(time_sec, &bp->reg->adjust_sec);
852 
853 	ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
854 	iowrite32(ctrl, &bp->reg->ctrl);
855 
856 	/* restore clock selection */
857 	iowrite32(select >> 16, &bp->reg->select);
858 }
859 
860 static int
861 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
862 {
863 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
864 	unsigned long flags;
865 
866 	spin_lock_irqsave(&bp->lock, flags);
867 	__ptp_ocp_settime_locked(bp, ts);
868 	spin_unlock_irqrestore(&bp->lock, flags);
869 
870 	return 0;
871 }
872 
873 static void
874 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
875 {
876 	u32 select, ctrl;
877 
878 	select = ioread32(&bp->reg->select);
879 	iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
880 
881 	iowrite32(adj_val, &bp->reg->offset_ns);
882 	iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
883 
884 	ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
885 	iowrite32(ctrl, &bp->reg->ctrl);
886 
887 	/* restore clock selection */
888 	iowrite32(select >> 16, &bp->reg->select);
889 }
890 
891 static void
892 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
893 {
894 	struct timespec64 ts;
895 	unsigned long flags;
896 	int err;
897 
898 	spin_lock_irqsave(&bp->lock, flags);
899 	err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
900 	if (likely(!err)) {
901 		set_normalized_timespec64(&ts, ts.tv_sec,
902 					  ts.tv_nsec + delta_ns);
903 		__ptp_ocp_settime_locked(bp, &ts);
904 	}
905 	spin_unlock_irqrestore(&bp->lock, flags);
906 }
907 
908 static int
909 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
910 {
911 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
912 	unsigned long flags;
913 	u32 adj_ns, sign;
914 
915 	if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
916 		ptp_ocp_adjtime_coarse(bp, delta_ns);
917 		return 0;
918 	}
919 
920 	sign = delta_ns < 0 ? BIT(31) : 0;
921 	adj_ns = sign ? -delta_ns : delta_ns;
922 
923 	spin_lock_irqsave(&bp->lock, flags);
924 	__ptp_ocp_adjtime_locked(bp, sign | adj_ns);
925 	spin_unlock_irqrestore(&bp->lock, flags);
926 
927 	return 0;
928 }
929 
930 static int
931 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
932 {
933 	if (scaled_ppm == 0)
934 		return 0;
935 
936 	return -EOPNOTSUPP;
937 }
938 
939 static int
940 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
941 {
942 	return -EOPNOTSUPP;
943 }
944 
945 static int
946 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
947 	       int on)
948 {
949 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
950 	struct ptp_ocp_ext_src *ext = NULL;
951 	u32 req;
952 	int err;
953 
954 	switch (rq->type) {
955 	case PTP_CLK_REQ_EXTTS:
956 		req = OCP_REQ_TIMESTAMP;
957 		switch (rq->extts.index) {
958 		case 0:
959 			ext = bp->ts0;
960 			break;
961 		case 1:
962 			ext = bp->ts1;
963 			break;
964 		case 2:
965 			ext = bp->ts2;
966 			break;
967 		case 3:
968 			ext = bp->ts3;
969 			break;
970 		case 4:
971 			ext = bp->ts4;
972 			break;
973 		case 5:
974 			ext = bp->pps;
975 			break;
976 		}
977 		break;
978 	case PTP_CLK_REQ_PPS:
979 		req = OCP_REQ_PPS;
980 		ext = bp->pps;
981 		break;
982 	case PTP_CLK_REQ_PEROUT:
983 		switch (rq->perout.index) {
984 		case 0:
985 			/* This is a request for 1PPS on an output SMA.
986 			 * Allow, but assume manual configuration.
987 			 */
988 			if (on && (rq->perout.period.sec != 1 ||
989 				   rq->perout.period.nsec != 0))
990 				return -EINVAL;
991 			return 0;
992 		case 1:
993 		case 2:
994 		case 3:
995 		case 4:
996 			req = rq->perout.index - 1;
997 			ext = bp->signal_out[req];
998 			err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
999 			if (err)
1000 				return err;
1001 			break;
1002 		}
1003 		break;
1004 	default:
1005 		return -EOPNOTSUPP;
1006 	}
1007 
1008 	err = -ENXIO;
1009 	if (ext)
1010 		err = ext->info->enable(ext, req, on);
1011 
1012 	return err;
1013 }
1014 
1015 static int
1016 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1017 	       enum ptp_pin_function func, unsigned chan)
1018 {
1019 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1020 	char buf[16];
1021 
1022 	switch (func) {
1023 	case PTP_PF_NONE:
1024 		snprintf(buf, sizeof(buf), "IN: None");
1025 		break;
1026 	case PTP_PF_EXTTS:
1027 		/* Allow timestamps, but require sysfs configuration. */
1028 		return 0;
1029 	case PTP_PF_PEROUT:
1030 		/* channel 0 is 1PPS from PHC.
1031 		 * channels 1..4 are the frequency generators.
1032 		 */
1033 		if (chan)
1034 			snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1035 		else
1036 			snprintf(buf, sizeof(buf), "OUT: PHC");
1037 		break;
1038 	default:
1039 		return -EOPNOTSUPP;
1040 	}
1041 
1042 	return ptp_ocp_sma_store(bp, buf, pin + 1);
1043 }
1044 
1045 static const struct ptp_clock_info ptp_ocp_clock_info = {
1046 	.owner		= THIS_MODULE,
1047 	.name		= KBUILD_MODNAME,
1048 	.max_adj	= 100000000,
1049 	.gettimex64	= ptp_ocp_gettimex,
1050 	.settime64	= ptp_ocp_settime,
1051 	.adjtime	= ptp_ocp_adjtime,
1052 	.adjfine	= ptp_ocp_null_adjfine,
1053 	.adjphase	= ptp_ocp_null_adjphase,
1054 	.enable		= ptp_ocp_enable,
1055 	.verify		= ptp_ocp_verify,
1056 	.pps		= true,
1057 	.n_ext_ts	= 6,
1058 	.n_per_out	= 5,
1059 };
1060 
1061 static void
1062 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1063 {
1064 	u32 ctrl, select;
1065 
1066 	select = ioread32(&bp->reg->select);
1067 	iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1068 
1069 	iowrite32(0, &bp->reg->drift_ns);
1070 
1071 	ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1072 	iowrite32(ctrl, &bp->reg->ctrl);
1073 
1074 	/* restore clock selection */
1075 	iowrite32(select >> 16, &bp->reg->select);
1076 }
1077 
1078 static void
1079 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1080 {
1081 	unsigned long flags;
1082 
1083 	spin_lock_irqsave(&bp->lock, flags);
1084 
1085 	bp->utc_tai_offset = val;
1086 
1087 	if (bp->irig_out)
1088 		iowrite32(val, &bp->irig_out->adj_sec);
1089 	if (bp->dcf_out)
1090 		iowrite32(val, &bp->dcf_out->adj_sec);
1091 	if (bp->nmea_out)
1092 		iowrite32(val, &bp->nmea_out->adj_sec);
1093 
1094 	spin_unlock_irqrestore(&bp->lock, flags);
1095 }
1096 
1097 static void
1098 ptp_ocp_watchdog(struct timer_list *t)
1099 {
1100 	struct ptp_ocp *bp = from_timer(bp, t, watchdog);
1101 	unsigned long flags;
1102 	u32 status, utc_offset;
1103 
1104 	status = ioread32(&bp->pps_to_clk->status);
1105 
1106 	if (status & PPS_STATUS_SUPERV_ERR) {
1107 		iowrite32(status, &bp->pps_to_clk->status);
1108 		if (!bp->gnss_lost) {
1109 			spin_lock_irqsave(&bp->lock, flags);
1110 			__ptp_ocp_clear_drift_locked(bp);
1111 			spin_unlock_irqrestore(&bp->lock, flags);
1112 			bp->gnss_lost = ktime_get_real_seconds();
1113 		}
1114 
1115 	} else if (bp->gnss_lost) {
1116 		bp->gnss_lost = 0;
1117 	}
1118 
1119 	/* if GNSS provides correct data we can rely on
1120 	 * it to get leap second information
1121 	 */
1122 	if (bp->tod) {
1123 		status = ioread32(&bp->tod->utc_status);
1124 		utc_offset = status & TOD_STATUS_UTC_MASK;
1125 		if (status & TOD_STATUS_UTC_VALID &&
1126 		    utc_offset != bp->utc_tai_offset)
1127 			ptp_ocp_utc_distribute(bp, utc_offset);
1128 	}
1129 
1130 	mod_timer(&bp->watchdog, jiffies + HZ);
1131 }
1132 
1133 static void
1134 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1135 {
1136 	ktime_t start, end;
1137 	ktime_t delay;
1138 	u32 ctrl;
1139 
1140 	ctrl = ioread32(&bp->reg->ctrl);
1141 	ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1142 
1143 	iowrite32(ctrl, &bp->reg->ctrl);
1144 
1145 	start = ktime_get_ns();
1146 
1147 	ctrl = ioread32(&bp->reg->ctrl);
1148 
1149 	end = ktime_get_ns();
1150 
1151 	delay = end - start;
1152 	bp->ts_window_adjust = (delay >> 5) * 3;
1153 }
1154 
1155 static int
1156 ptp_ocp_init_clock(struct ptp_ocp *bp)
1157 {
1158 	struct timespec64 ts;
1159 	bool sync;
1160 	u32 ctrl;
1161 
1162 	ctrl = OCP_CTRL_ENABLE;
1163 	iowrite32(ctrl, &bp->reg->ctrl);
1164 
1165 	/* NO DRIFT Correction */
1166 	/* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */
1167 	iowrite32(0x2000, &bp->reg->servo_offset_p);
1168 	iowrite32(0x1000, &bp->reg->servo_offset_i);
1169 	iowrite32(0,	  &bp->reg->servo_drift_p);
1170 	iowrite32(0,	  &bp->reg->servo_drift_i);
1171 
1172 	/* latch servo values */
1173 	ctrl |= OCP_CTRL_ADJUST_SERVO;
1174 	iowrite32(ctrl, &bp->reg->ctrl);
1175 
1176 	if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1177 		dev_err(&bp->pdev->dev, "clock not enabled\n");
1178 		return -ENODEV;
1179 	}
1180 
1181 	ptp_ocp_estimate_pci_timing(bp);
1182 
1183 	sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1184 	if (!sync) {
1185 		ktime_get_clocktai_ts64(&ts);
1186 		ptp_ocp_settime(&bp->ptp_info, &ts);
1187 	}
1188 
1189 	/* If there is a clock supervisor, then enable the watchdog */
1190 	if (bp->pps_to_clk) {
1191 		timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1192 		mod_timer(&bp->watchdog, jiffies + HZ);
1193 	}
1194 
1195 	return 0;
1196 }
1197 
1198 static void
1199 ptp_ocp_tod_init(struct ptp_ocp *bp)
1200 {
1201 	u32 ctrl, reg;
1202 
1203 	ctrl = ioread32(&bp->tod->ctrl);
1204 	ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1205 	ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1206 	iowrite32(ctrl, &bp->tod->ctrl);
1207 
1208 	reg = ioread32(&bp->tod->utc_status);
1209 	if (reg & TOD_STATUS_UTC_VALID)
1210 		ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1211 }
1212 
1213 static const char *
1214 ptp_ocp_tod_proto_name(const int idx)
1215 {
1216 	static const char * const proto_name[] = {
1217 		"NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1218 		"UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1219 	};
1220 	return proto_name[idx];
1221 }
1222 
1223 static const char *
1224 ptp_ocp_tod_gnss_name(int idx)
1225 {
1226 	static const char * const gnss_name[] = {
1227 		"ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1228 		"Unknown"
1229 	};
1230 	if (idx >= ARRAY_SIZE(gnss_name))
1231 		idx = ARRAY_SIZE(gnss_name) - 1;
1232 	return gnss_name[idx];
1233 }
1234 
1235 struct ptp_ocp_nvmem_match_info {
1236 	struct ptp_ocp *bp;
1237 	const void * const tag;
1238 };
1239 
1240 static int
1241 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1242 {
1243 	const struct ptp_ocp_nvmem_match_info *info = data;
1244 
1245 	dev = dev->parent;
1246 	if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1247 		return 0;
1248 
1249 	while ((dev = dev->parent))
1250 		if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1251 			return info->bp == dev_get_drvdata(dev);
1252 	return 0;
1253 }
1254 
1255 static inline struct nvmem_device *
1256 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1257 {
1258 	struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1259 
1260 	return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1261 }
1262 
1263 static inline void
1264 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1265 {
1266 	if (!IS_ERR_OR_NULL(*nvmemp))
1267 		nvmem_device_put(*nvmemp);
1268 	*nvmemp = NULL;
1269 }
1270 
1271 static void
1272 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1273 {
1274 	const struct ptp_ocp_eeprom_map *map;
1275 	struct nvmem_device *nvmem;
1276 	const void *tag;
1277 	int ret;
1278 
1279 	if (!bp->i2c_ctrl)
1280 		return;
1281 
1282 	tag = NULL;
1283 	nvmem = NULL;
1284 
1285 	for (map = bp->eeprom_map; map->len; map++) {
1286 		if (map->tag != tag) {
1287 			tag = map->tag;
1288 			ptp_ocp_nvmem_device_put(&nvmem);
1289 		}
1290 		if (!nvmem) {
1291 			nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1292 			if (IS_ERR(nvmem)) {
1293 				ret = PTR_ERR(nvmem);
1294 				goto fail;
1295 			}
1296 		}
1297 		ret = nvmem_device_read(nvmem, map->off, map->len,
1298 					BP_MAP_ENTRY_ADDR(bp, map));
1299 		if (ret != map->len)
1300 			goto fail;
1301 	}
1302 
1303 	bp->has_eeprom_data = true;
1304 
1305 out:
1306 	ptp_ocp_nvmem_device_put(&nvmem);
1307 	return;
1308 
1309 fail:
1310 	dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1311 	goto out;
1312 }
1313 
1314 static int
1315 ptp_ocp_firstchild(struct device *dev, void *data)
1316 {
1317 	return 1;
1318 }
1319 
1320 static struct device *
1321 ptp_ocp_find_flash(struct ptp_ocp *bp)
1322 {
1323 	struct device *dev, *last;
1324 
1325 	last = NULL;
1326 	dev = &bp->spi_flash->dev;
1327 
1328 	while ((dev = device_find_child(dev, NULL, ptp_ocp_firstchild))) {
1329 		if (!strcmp("mtd", dev_bus_name(dev)))
1330 			break;
1331 		put_device(last);
1332 		last = dev;
1333 	}
1334 	put_device(last);
1335 
1336 	return dev;
1337 }
1338 
1339 static int
1340 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1341 			 const u8 **data, size_t *size)
1342 {
1343 	struct ptp_ocp *bp = devlink_priv(devlink);
1344 	const struct ptp_ocp_firmware_header *hdr;
1345 	size_t offset, length;
1346 	u16 crc;
1347 
1348 	hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1349 	if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1350 		devlink_flash_update_status_notify(devlink,
1351 			"No firmware header found, flashing raw image",
1352 			NULL, 0, 0);
1353 		offset = 0;
1354 		length = fw->size;
1355 		goto out;
1356 	}
1357 
1358 	if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1359 	    be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1360 		devlink_flash_update_status_notify(devlink,
1361 			"Firmware image compatibility check failed",
1362 			NULL, 0, 0);
1363 		return -EINVAL;
1364 	}
1365 
1366 	offset = sizeof(*hdr);
1367 	length = be32_to_cpu(hdr->image_size);
1368 	if (length != (fw->size - offset)) {
1369 		devlink_flash_update_status_notify(devlink,
1370 			"Firmware image size check failed",
1371 			NULL, 0, 0);
1372 		return -EINVAL;
1373 	}
1374 
1375 	crc = crc16(0xffff, &fw->data[offset], length);
1376 	if (be16_to_cpu(hdr->crc) != crc) {
1377 		devlink_flash_update_status_notify(devlink,
1378 			"Firmware image CRC check failed",
1379 			NULL, 0, 0);
1380 		return -EINVAL;
1381 	}
1382 
1383 out:
1384 	*data = &fw->data[offset];
1385 	*size = length;
1386 
1387 	return 0;
1388 }
1389 
1390 static int
1391 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1392 		      const struct firmware *fw)
1393 {
1394 	struct mtd_info *mtd = dev_get_drvdata(dev);
1395 	struct ptp_ocp *bp = devlink_priv(devlink);
1396 	size_t off, len, size, resid, wrote;
1397 	struct erase_info erase;
1398 	size_t base, blksz;
1399 	const u8 *data;
1400 	int err;
1401 
1402 	err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1403 	if (err)
1404 		goto out;
1405 
1406 	off = 0;
1407 	base = bp->flash_start;
1408 	blksz = 4096;
1409 	resid = size;
1410 
1411 	while (resid) {
1412 		devlink_flash_update_status_notify(devlink, "Flashing",
1413 						   NULL, off, size);
1414 
1415 		len = min_t(size_t, resid, blksz);
1416 		erase.addr = base + off;
1417 		erase.len = blksz;
1418 
1419 		err = mtd_erase(mtd, &erase);
1420 		if (err)
1421 			goto out;
1422 
1423 		err = mtd_write(mtd, base + off, len, &wrote, data + off);
1424 		if (err)
1425 			goto out;
1426 
1427 		off += blksz;
1428 		resid -= len;
1429 	}
1430 out:
1431 	return err;
1432 }
1433 
1434 static int
1435 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1436 			     struct devlink_flash_update_params *params,
1437 			     struct netlink_ext_ack *extack)
1438 {
1439 	struct ptp_ocp *bp = devlink_priv(devlink);
1440 	struct device *dev;
1441 	const char *msg;
1442 	int err;
1443 
1444 	dev = ptp_ocp_find_flash(bp);
1445 	if (!dev) {
1446 		dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1447 		return -ENODEV;
1448 	}
1449 
1450 	devlink_flash_update_status_notify(devlink, "Preparing to flash",
1451 					   NULL, 0, 0);
1452 
1453 	err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1454 
1455 	msg = err ? "Flash error" : "Flash complete";
1456 	devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1457 
1458 	put_device(dev);
1459 	return err;
1460 }
1461 
1462 static int
1463 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1464 			 struct netlink_ext_ack *extack)
1465 {
1466 	struct ptp_ocp *bp = devlink_priv(devlink);
1467 	const char *fw_image;
1468 	char buf[32];
1469 	int err;
1470 
1471 	err = devlink_info_driver_name_put(req, KBUILD_MODNAME);
1472 	if (err)
1473 		return err;
1474 
1475 	fw_image = bp->fw_loader ? "loader" : "fw";
1476 	sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1477 	err = devlink_info_version_running_put(req, fw_image, buf);
1478 	if (err)
1479 		return err;
1480 
1481 	if (!bp->has_eeprom_data) {
1482 		ptp_ocp_read_eeprom(bp);
1483 		if (!bp->has_eeprom_data)
1484 			return 0;
1485 	}
1486 
1487 	sprintf(buf, "%pM", bp->serial);
1488 	err = devlink_info_serial_number_put(req, buf);
1489 	if (err)
1490 		return err;
1491 
1492 	err = devlink_info_version_fixed_put(req,
1493 			DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1494 			bp->board_id);
1495 	if (err)
1496 		return err;
1497 
1498 	return 0;
1499 }
1500 
1501 static const struct devlink_ops ptp_ocp_devlink_ops = {
1502 	.flash_update = ptp_ocp_devlink_flash_update,
1503 	.info_get = ptp_ocp_devlink_info_get,
1504 };
1505 
1506 static void __iomem *
1507 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1508 {
1509 	struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1510 
1511 	return devm_ioremap_resource(&bp->pdev->dev, &res);
1512 }
1513 
1514 static void __iomem *
1515 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1516 {
1517 	resource_size_t start;
1518 
1519 	start = pci_resource_start(bp->pdev, 0) + r->offset;
1520 	return __ptp_ocp_get_mem(bp, start, r->size);
1521 }
1522 
1523 static void
1524 ptp_ocp_set_irq_resource(struct resource *res, int irq)
1525 {
1526 	struct resource r = DEFINE_RES_IRQ(irq);
1527 	*res = r;
1528 }
1529 
1530 static void
1531 ptp_ocp_set_mem_resource(struct resource *res, resource_size_t start, int size)
1532 {
1533 	struct resource r = DEFINE_RES_MEM(start, size);
1534 	*res = r;
1535 }
1536 
1537 static int
1538 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1539 {
1540 	struct ptp_ocp_flash_info *info;
1541 	struct pci_dev *pdev = bp->pdev;
1542 	struct platform_device *p;
1543 	struct resource res[2];
1544 	resource_size_t start;
1545 	int id;
1546 
1547 	start = pci_resource_start(pdev, 0) + r->offset;
1548 	ptp_ocp_set_mem_resource(&res[0], start, r->size);
1549 	ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1550 
1551 	info = r->extra;
1552 	id = pci_dev_id(pdev) << 1;
1553 	id += info->pci_offset;
1554 
1555 	p = platform_device_register_resndata(&pdev->dev, info->name, id,
1556 					      res, 2, info->data,
1557 					      info->data_size);
1558 	if (IS_ERR(p))
1559 		return PTR_ERR(p);
1560 
1561 	bp_assign_entry(bp, r, p);
1562 
1563 	return 0;
1564 }
1565 
1566 static struct platform_device *
1567 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1568 {
1569 	struct ptp_ocp_i2c_info *info;
1570 	struct resource res[2];
1571 	resource_size_t start;
1572 
1573 	info = r->extra;
1574 	start = pci_resource_start(pdev, 0) + r->offset;
1575 	ptp_ocp_set_mem_resource(&res[0], start, r->size);
1576 	ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1577 
1578 	return platform_device_register_resndata(&pdev->dev, info->name,
1579 						 id, res, 2,
1580 						 info->data, info->data_size);
1581 }
1582 
1583 static int
1584 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1585 {
1586 	struct pci_dev *pdev = bp->pdev;
1587 	struct ptp_ocp_i2c_info *info;
1588 	struct platform_device *p;
1589 	struct clk_hw *clk;
1590 	char buf[32];
1591 	int id;
1592 
1593 	info = r->extra;
1594 	id = pci_dev_id(bp->pdev);
1595 
1596 	sprintf(buf, "AXI.%d", id);
1597 	clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
1598 					 info->fixed_rate);
1599 	if (IS_ERR(clk))
1600 		return PTR_ERR(clk);
1601 	bp->i2c_clk = clk;
1602 
1603 	sprintf(buf, "%s.%d", info->name, id);
1604 	devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
1605 	p = ptp_ocp_i2c_bus(bp->pdev, r, id);
1606 	if (IS_ERR(p))
1607 		return PTR_ERR(p);
1608 
1609 	bp_assign_entry(bp, r, p);
1610 
1611 	return 0;
1612 }
1613 
1614 /* The expectation is that this is triggered only on error. */
1615 static irqreturn_t
1616 ptp_ocp_signal_irq(int irq, void *priv)
1617 {
1618 	struct ptp_ocp_ext_src *ext = priv;
1619 	struct signal_reg __iomem *reg = ext->mem;
1620 	struct ptp_ocp *bp = ext->bp;
1621 	u32 enable, status;
1622 	int gen;
1623 
1624 	gen = ext->info->index - 1;
1625 
1626 	enable = ioread32(&reg->enable);
1627 	status = ioread32(&reg->status);
1628 
1629 	/* disable generator on error */
1630 	if (status || !enable) {
1631 		iowrite32(0, &reg->intr_mask);
1632 		iowrite32(0, &reg->enable);
1633 		bp->signal[gen].running = false;
1634 	}
1635 
1636 	iowrite32(0, &reg->intr);	/* ack interrupt */
1637 
1638 	return IRQ_HANDLED;
1639 }
1640 
1641 static int
1642 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
1643 {
1644 	struct ptp_system_timestamp sts;
1645 	struct timespec64 ts;
1646 	ktime_t start_ns;
1647 	int err;
1648 
1649 	if (!s->period)
1650 		return 0;
1651 
1652 	if (!s->pulse)
1653 		s->pulse = ktime_divns(s->period * s->duty, 100);
1654 
1655 	err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
1656 	if (err)
1657 		return err;
1658 
1659 	start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
1660 	if (!s->start) {
1661 		/* roundup() does not work on 32-bit systems */
1662 		s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
1663 		s->start = ktime_add(s->start, s->phase);
1664 	}
1665 
1666 	if (s->duty < 1 || s->duty > 99)
1667 		return -EINVAL;
1668 
1669 	if (s->pulse < 1 || s->pulse > s->period)
1670 		return -EINVAL;
1671 
1672 	if (s->start < start_ns)
1673 		return -EINVAL;
1674 
1675 	bp->signal[gen] = *s;
1676 
1677 	return 0;
1678 }
1679 
1680 static int
1681 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
1682 			   struct ptp_perout_request *req)
1683 {
1684 	struct ptp_ocp_signal s = { };
1685 
1686 	s.polarity = bp->signal[gen].polarity;
1687 	s.period = ktime_set(req->period.sec, req->period.nsec);
1688 	if (!s.period)
1689 		return 0;
1690 
1691 	if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
1692 		s.pulse = ktime_set(req->on.sec, req->on.nsec);
1693 		s.duty = ktime_divns(s.pulse * 100, s.period);
1694 	}
1695 
1696 	if (req->flags & PTP_PEROUT_PHASE)
1697 		s.phase = ktime_set(req->phase.sec, req->phase.nsec);
1698 	else
1699 		s.start = ktime_set(req->start.sec, req->start.nsec);
1700 
1701 	return ptp_ocp_signal_set(bp, gen, &s);
1702 }
1703 
1704 static int
1705 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
1706 {
1707 	struct ptp_ocp_ext_src *ext = priv;
1708 	struct signal_reg __iomem *reg = ext->mem;
1709 	struct ptp_ocp *bp = ext->bp;
1710 	struct timespec64 ts;
1711 	int gen;
1712 
1713 	gen = ext->info->index - 1;
1714 
1715 	iowrite32(0, &reg->intr_mask);
1716 	iowrite32(0, &reg->enable);
1717 	bp->signal[gen].running = false;
1718 	if (!enable)
1719 		return 0;
1720 
1721 	ts = ktime_to_timespec64(bp->signal[gen].start);
1722 	iowrite32(ts.tv_sec, &reg->start_sec);
1723 	iowrite32(ts.tv_nsec, &reg->start_ns);
1724 
1725 	ts = ktime_to_timespec64(bp->signal[gen].period);
1726 	iowrite32(ts.tv_sec, &reg->period_sec);
1727 	iowrite32(ts.tv_nsec, &reg->period_ns);
1728 
1729 	ts = ktime_to_timespec64(bp->signal[gen].pulse);
1730 	iowrite32(ts.tv_sec, &reg->pulse_sec);
1731 	iowrite32(ts.tv_nsec, &reg->pulse_ns);
1732 
1733 	iowrite32(bp->signal[gen].polarity, &reg->polarity);
1734 	iowrite32(0, &reg->repeat_count);
1735 
1736 	iowrite32(0, &reg->intr);		/* clear interrupt state */
1737 	iowrite32(1, &reg->intr_mask);		/* enable interrupt */
1738 	iowrite32(3, &reg->enable);		/* valid & enable */
1739 
1740 	bp->signal[gen].running = true;
1741 
1742 	return 0;
1743 }
1744 
1745 static irqreturn_t
1746 ptp_ocp_ts_irq(int irq, void *priv)
1747 {
1748 	struct ptp_ocp_ext_src *ext = priv;
1749 	struct ts_reg __iomem *reg = ext->mem;
1750 	struct ptp_clock_event ev;
1751 	u32 sec, nsec;
1752 
1753 	if (ext == ext->bp->pps) {
1754 		if (ext->bp->pps_req_map & OCP_REQ_PPS) {
1755 			ev.type = PTP_CLOCK_PPS;
1756 			ptp_clock_event(ext->bp->ptp, &ev);
1757 		}
1758 
1759 		if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
1760 			goto out;
1761 	}
1762 
1763 	/* XXX should fix API - this converts s/ns -> ts -> s/ns */
1764 	sec = ioread32(&reg->time_sec);
1765 	nsec = ioread32(&reg->time_ns);
1766 
1767 	ev.type = PTP_CLOCK_EXTTS;
1768 	ev.index = ext->info->index;
1769 	ev.timestamp = sec * NSEC_PER_SEC + nsec;
1770 
1771 	ptp_clock_event(ext->bp->ptp, &ev);
1772 
1773 out:
1774 	iowrite32(1, &reg->intr);	/* write 1 to ack */
1775 
1776 	return IRQ_HANDLED;
1777 }
1778 
1779 static int
1780 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
1781 {
1782 	struct ptp_ocp_ext_src *ext = priv;
1783 	struct ts_reg __iomem *reg = ext->mem;
1784 	struct ptp_ocp *bp = ext->bp;
1785 
1786 	if (ext == bp->pps) {
1787 		u32 old_map = bp->pps_req_map;
1788 
1789 		if (enable)
1790 			bp->pps_req_map |= req;
1791 		else
1792 			bp->pps_req_map &= ~req;
1793 
1794 		/* if no state change, just return */
1795 		if ((!!old_map ^ !!bp->pps_req_map) == 0)
1796 			return 0;
1797 	}
1798 
1799 	if (enable) {
1800 		iowrite32(1, &reg->enable);
1801 		iowrite32(1, &reg->intr_mask);
1802 		iowrite32(1, &reg->intr);
1803 	} else {
1804 		iowrite32(0, &reg->intr_mask);
1805 		iowrite32(0, &reg->enable);
1806 	}
1807 
1808 	return 0;
1809 }
1810 
1811 static void
1812 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
1813 {
1814 	ext->info->enable(ext, ~0, false);
1815 	pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
1816 	kfree(ext);
1817 }
1818 
1819 static int
1820 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
1821 {
1822 	struct pci_dev *pdev = bp->pdev;
1823 	struct ptp_ocp_ext_src *ext;
1824 	int err;
1825 
1826 	ext = kzalloc(sizeof(*ext), GFP_KERNEL);
1827 	if (!ext)
1828 		return -ENOMEM;
1829 
1830 	ext->mem = ptp_ocp_get_mem(bp, r);
1831 	if (IS_ERR(ext->mem)) {
1832 		err = PTR_ERR(ext->mem);
1833 		goto out;
1834 	}
1835 
1836 	ext->bp = bp;
1837 	ext->info = r->extra;
1838 	ext->irq_vec = r->irq_vec;
1839 
1840 	err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
1841 			      ext, "ocp%d.%s", bp->id, r->name);
1842 	if (err) {
1843 		dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
1844 		goto out;
1845 	}
1846 
1847 	bp_assign_entry(bp, r, ext);
1848 
1849 	return 0;
1850 
1851 out:
1852 	kfree(ext);
1853 	return err;
1854 }
1855 
1856 static int
1857 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
1858 {
1859 	struct pci_dev *pdev = bp->pdev;
1860 	struct uart_8250_port uart;
1861 
1862 	/* Setting UPF_IOREMAP and leaving port.membase unspecified lets
1863 	 * the serial port device claim and release the pci resource.
1864 	 */
1865 	memset(&uart, 0, sizeof(uart));
1866 	uart.port.dev = &pdev->dev;
1867 	uart.port.iotype = UPIO_MEM;
1868 	uart.port.regshift = 2;
1869 	uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
1870 	uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
1871 	uart.port.uartclk = 50000000;
1872 	uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
1873 	uart.port.type = PORT_16550A;
1874 
1875 	return serial8250_register_8250_port(&uart);
1876 }
1877 
1878 static int
1879 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
1880 {
1881 	int port;
1882 
1883 	port = ptp_ocp_serial_line(bp, r);
1884 	if (port < 0)
1885 		return port;
1886 
1887 	bp_assign_entry(bp, r, port);
1888 
1889 	return 0;
1890 }
1891 
1892 static int
1893 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1894 {
1895 	void __iomem *mem;
1896 
1897 	mem = ptp_ocp_get_mem(bp, r);
1898 	if (IS_ERR(mem))
1899 		return PTR_ERR(mem);
1900 
1901 	bp_assign_entry(bp, r, mem);
1902 
1903 	return 0;
1904 }
1905 
1906 static void
1907 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
1908 {
1909 	if (!bp->nmea_out)
1910 		return;
1911 
1912 	iowrite32(0, &bp->nmea_out->ctrl);		/* disable */
1913 	iowrite32(7, &bp->nmea_out->uart_baud);		/* 115200 */
1914 	iowrite32(1, &bp->nmea_out->ctrl);		/* enable */
1915 }
1916 
1917 static void
1918 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
1919 {
1920 	u32 val;
1921 
1922 	iowrite32(0, &reg->enable);		/* disable */
1923 
1924 	val = ioread32(&reg->polarity);
1925 	s->polarity = val ? true : false;
1926 	s->duty = 50;
1927 }
1928 
1929 static void
1930 ptp_ocp_signal_init(struct ptp_ocp *bp)
1931 {
1932 	int i;
1933 
1934 	for (i = 0; i < 4; i++)
1935 		if (bp->signal_out[i])
1936 			_ptp_ocp_signal_init(&bp->signal[i],
1937 					     bp->signal_out[i]->mem);
1938 }
1939 
1940 static void
1941 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
1942 {
1943 	sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
1944 	kfree(bp->attr_group);
1945 }
1946 
1947 static int
1948 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
1949 		       const struct ocp_attr_group *attr_tbl)
1950 {
1951 	int count, i;
1952 	int err;
1953 
1954 	count = 0;
1955 	for (i = 0; attr_tbl[i].cap; i++)
1956 		if (attr_tbl[i].cap & bp->fw_cap)
1957 			count++;
1958 
1959 	bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *),
1960 				 GFP_KERNEL);
1961 	if (!bp->attr_group)
1962 		return -ENOMEM;
1963 
1964 	count = 0;
1965 	for (i = 0; attr_tbl[i].cap; i++)
1966 		if (attr_tbl[i].cap & bp->fw_cap)
1967 			bp->attr_group[count++] = attr_tbl[i].group;
1968 
1969 	err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
1970 	if (err)
1971 		bp->attr_group[0] = NULL;
1972 
1973 	return err;
1974 }
1975 
1976 static void
1977 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
1978 {
1979 	u32 ctrl;
1980 	bool on;
1981 
1982 	ctrl = ioread32(reg);
1983 	on = ctrl & bit;
1984 	if (on ^ enable) {
1985 		ctrl &= ~bit;
1986 		ctrl |= enable ? bit : 0;
1987 		iowrite32(ctrl, reg);
1988 	}
1989 }
1990 
1991 static void
1992 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
1993 {
1994 	return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
1995 				   IRIG_M_CTRL_ENABLE, enable);
1996 }
1997 
1998 static void
1999 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2000 {
2001 	return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2002 				   IRIG_S_CTRL_ENABLE, enable);
2003 }
2004 
2005 static void
2006 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2007 {
2008 	return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2009 				   DCF_M_CTRL_ENABLE, enable);
2010 }
2011 
2012 static void
2013 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2014 {
2015 	return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2016 				   DCF_S_CTRL_ENABLE, enable);
2017 }
2018 
2019 static void
2020 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2021 {
2022 	ptp_ocp_irig_out(bp, val & 0x00100010);
2023 	ptp_ocp_dcf_out(bp, val & 0x00200020);
2024 }
2025 
2026 static void
2027 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2028 {
2029 	ptp_ocp_irig_in(bp, val & 0x00100010);
2030 	ptp_ocp_dcf_in(bp, val & 0x00200020);
2031 }
2032 
2033 static u32
2034 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2035 {
2036 	u32 __iomem *gpio;
2037 	u32 shift;
2038 
2039 	if (bp->sma[sma_nr - 1].fixed_fcn)
2040 		return (sma_nr - 1) & 1;
2041 
2042 	if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2043 		gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2044 	else
2045 		gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2046 	shift = sma_nr & 1 ? 0 : 16;
2047 
2048 	return (ioread32(gpio) >> shift) & 0xffff;
2049 }
2050 
2051 static int
2052 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2053 {
2054 	u32 reg, mask, shift;
2055 	unsigned long flags;
2056 	u32 __iomem *gpio;
2057 
2058 	gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2059 	shift = sma_nr & 1 ? 0 : 16;
2060 
2061 	mask = 0xffff << (16 - shift);
2062 
2063 	spin_lock_irqsave(&bp->lock, flags);
2064 
2065 	reg = ioread32(gpio);
2066 	reg = (reg & mask) | (val << shift);
2067 
2068 	__handle_signal_outputs(bp, reg);
2069 
2070 	iowrite32(reg, gpio);
2071 
2072 	spin_unlock_irqrestore(&bp->lock, flags);
2073 
2074 	return 0;
2075 }
2076 
2077 static int
2078 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2079 {
2080 	u32 reg, mask, shift;
2081 	unsigned long flags;
2082 	u32 __iomem *gpio;
2083 
2084 	gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2085 	shift = sma_nr & 1 ? 0 : 16;
2086 
2087 	mask = 0xffff << (16 - shift);
2088 
2089 	spin_lock_irqsave(&bp->lock, flags);
2090 
2091 	reg = ioread32(gpio);
2092 	reg = (reg & mask) | (val << shift);
2093 
2094 	__handle_signal_inputs(bp, reg);
2095 
2096 	iowrite32(reg, gpio);
2097 
2098 	spin_unlock_irqrestore(&bp->lock, flags);
2099 
2100 	return 0;
2101 }
2102 
2103 static void
2104 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2105 {
2106 	u32 reg;
2107 	int i;
2108 
2109 	/* defaults */
2110 	bp->sma[0].mode = SMA_MODE_IN;
2111 	bp->sma[1].mode = SMA_MODE_IN;
2112 	bp->sma[2].mode = SMA_MODE_OUT;
2113 	bp->sma[3].mode = SMA_MODE_OUT;
2114 	for (i = 0; i < 4; i++)
2115 		bp->sma[i].default_fcn = i & 1;
2116 
2117 	/* If no SMA1 map, the pin functions and directions are fixed. */
2118 	if (!bp->sma_map1) {
2119 		for (i = 0; i < 4; i++) {
2120 			bp->sma[i].fixed_fcn = true;
2121 			bp->sma[i].fixed_dir = true;
2122 		}
2123 		return;
2124 	}
2125 
2126 	/* If SMA2 GPIO output map is all 1, it is not present.
2127 	 * This indicates the firmware has fixed direction SMA pins.
2128 	 */
2129 	reg = ioread32(&bp->sma_map2->gpio2);
2130 	if (reg == 0xffffffff) {
2131 		for (i = 0; i < 4; i++)
2132 			bp->sma[i].fixed_dir = true;
2133 	} else {
2134 		reg = ioread32(&bp->sma_map1->gpio1);
2135 		bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2136 		bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2137 
2138 		reg = ioread32(&bp->sma_map1->gpio2);
2139 		bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2140 		bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2141 	}
2142 }
2143 
2144 static const struct ocp_sma_op ocp_fb_sma_op = {
2145 	.tbl		= { ptp_ocp_sma_in, ptp_ocp_sma_out },
2146 	.init		= ptp_ocp_sma_fb_init,
2147 	.get		= ptp_ocp_sma_fb_get,
2148 	.set_inputs	= ptp_ocp_sma_fb_set_inputs,
2149 	.set_output	= ptp_ocp_sma_fb_set_output,
2150 };
2151 
2152 static int
2153 ptp_ocp_fb_set_pins(struct ptp_ocp *bp)
2154 {
2155 	struct ptp_pin_desc *config;
2156 	int i;
2157 
2158 	config = kcalloc(4, sizeof(*config), GFP_KERNEL);
2159 	if (!config)
2160 		return -ENOMEM;
2161 
2162 	for (i = 0; i < 4; i++) {
2163 		sprintf(config[i].name, "sma%d", i + 1);
2164 		config[i].index = i;
2165 	}
2166 
2167 	bp->ptp_info.n_pins = 4;
2168 	bp->ptp_info.pin_config = config;
2169 
2170 	return 0;
2171 }
2172 
2173 static void
2174 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2175 {
2176 	u64 cap = OCP_CAP_BASIC;
2177 	u32 version;
2178 
2179 	version = ioread32(&bp->image->version);
2180 
2181 	/* if lower 16 bits are empty, this is the fw loader. */
2182 	if ((version & 0xffff) == 0) {
2183 		version = version >> 16;
2184 		bp->fw_loader = true;
2185 	}
2186 
2187 	bp->fw_tag = version >> 15;
2188 	bp->fw_version = version & 0x7fff;
2189 
2190 	if (bp->fw_tag) {
2191 		/* FPGA firmware */
2192 		if (version >= 5)
2193 			cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2194 	} else {
2195 		/* SOM firmware */
2196 		if (version >= 19)
2197 			cap |= OCP_CAP_SIGNAL;
2198 		if (version >= 20)
2199 			cap |= OCP_CAP_FREQ;
2200 	}
2201 
2202 	bp->fw_cap = cap;
2203 }
2204 
2205 /* FB specific board initializers; last "resource" registered. */
2206 static int
2207 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2208 {
2209 	int err;
2210 
2211 	bp->flash_start = 1024 * 4096;
2212 	bp->eeprom_map = fb_eeprom_map;
2213 	bp->fw_version = ioread32(&bp->image->version);
2214 	bp->sma_op = &ocp_fb_sma_op;
2215 
2216 	ptp_ocp_fb_set_version(bp);
2217 
2218 	ptp_ocp_tod_init(bp);
2219 	ptp_ocp_nmea_out_init(bp);
2220 	ptp_ocp_sma_init(bp);
2221 	ptp_ocp_signal_init(bp);
2222 
2223 	err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2224 	if (err)
2225 		return err;
2226 
2227 	err = ptp_ocp_fb_set_pins(bp);
2228 	if (err)
2229 		return err;
2230 
2231 	return ptp_ocp_init_clock(bp);
2232 }
2233 
2234 static bool
2235 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2236 {
2237 	bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2238 
2239 	if (!allow)
2240 		dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2241 			r->irq_vec, r->name);
2242 	return allow;
2243 }
2244 
2245 static int
2246 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2247 {
2248 	struct ocp_resource *r, *table;
2249 	int err = 0;
2250 
2251 	table = (struct ocp_resource *)driver_data;
2252 	for (r = table; r->setup; r++) {
2253 		if (!ptp_ocp_allow_irq(bp, r))
2254 			continue;
2255 		err = r->setup(bp, r);
2256 		if (err) {
2257 			dev_err(&bp->pdev->dev,
2258 				"Could not register %s: err %d\n",
2259 				r->name, err);
2260 			break;
2261 		}
2262 	}
2263 	return err;
2264 }
2265 
2266 static ssize_t
2267 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2268 		    int def_val)
2269 {
2270 	const char *name;
2271 	ssize_t count;
2272 
2273 	count = sysfs_emit(buf, "OUT: ");
2274 	name = ptp_ocp_select_name_from_val(tbl, val);
2275 	if (!name)
2276 		name = ptp_ocp_select_name_from_val(tbl, def_val);
2277 	count += sysfs_emit_at(buf, count, "%s\n", name);
2278 	return count;
2279 }
2280 
2281 static ssize_t
2282 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2283 		    int def_val)
2284 {
2285 	const char *name;
2286 	ssize_t count;
2287 	int i;
2288 
2289 	count = sysfs_emit(buf, "IN: ");
2290 	for (i = 0; tbl[i].name; i++) {
2291 		if (val & tbl[i].value) {
2292 			name = tbl[i].name;
2293 			count += sysfs_emit_at(buf, count, "%s ", name);
2294 		}
2295 	}
2296 	if (!val && def_val >= 0) {
2297 		name = ptp_ocp_select_name_from_val(tbl, def_val);
2298 		count += sysfs_emit_at(buf, count, "%s ", name);
2299 	}
2300 	if (count)
2301 		count--;
2302 	count += sysfs_emit_at(buf, count, "\n");
2303 	return count;
2304 }
2305 
2306 static int
2307 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2308 		 enum ptp_ocp_sma_mode *mode)
2309 {
2310 	int idx, count, dir;
2311 	char **argv;
2312 	int ret;
2313 
2314 	argv = argv_split(GFP_KERNEL, buf, &count);
2315 	if (!argv)
2316 		return -ENOMEM;
2317 
2318 	ret = -EINVAL;
2319 	if (!count)
2320 		goto out;
2321 
2322 	idx = 0;
2323 	dir = *mode == SMA_MODE_IN ? 0 : 1;
2324 	if (!strcasecmp("IN:", argv[0])) {
2325 		dir = 0;
2326 		idx++;
2327 	}
2328 	if (!strcasecmp("OUT:", argv[0])) {
2329 		dir = 1;
2330 		idx++;
2331 	}
2332 	*mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2333 
2334 	ret = 0;
2335 	for (; idx < count; idx++)
2336 		ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
2337 	if (ret < 0)
2338 		ret = -EINVAL;
2339 
2340 out:
2341 	argv_free(argv);
2342 	return ret;
2343 }
2344 
2345 static ssize_t
2346 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
2347 		 int default_in_val, int default_out_val)
2348 {
2349 	struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2350 	const struct ocp_selector * const *tbl;
2351 	u32 val;
2352 
2353 	tbl = bp->sma_op->tbl;
2354 	val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
2355 
2356 	if (sma->mode == SMA_MODE_IN) {
2357 		if (sma->disabled)
2358 			val = SMA_DISABLE;
2359 		return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
2360 	}
2361 
2362 	return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
2363 }
2364 
2365 static ssize_t
2366 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
2367 {
2368 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2369 
2370 	return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
2371 }
2372 
2373 static ssize_t
2374 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
2375 {
2376 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2377 
2378 	return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
2379 }
2380 
2381 static ssize_t
2382 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
2383 {
2384 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2385 
2386 	return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
2387 }
2388 
2389 static ssize_t
2390 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
2391 {
2392 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2393 
2394 	return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
2395 }
2396 
2397 static int
2398 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
2399 {
2400 	struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2401 	enum ptp_ocp_sma_mode mode;
2402 	int val;
2403 
2404 	mode = sma->mode;
2405 	val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
2406 	if (val < 0)
2407 		return val;
2408 
2409 	if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
2410 		return -EOPNOTSUPP;
2411 
2412 	if (sma->fixed_fcn) {
2413 		if (val != sma->default_fcn)
2414 			return -EOPNOTSUPP;
2415 		return 0;
2416 	}
2417 
2418 	sma->disabled = !!(val & SMA_DISABLE);
2419 
2420 	if (mode != sma->mode) {
2421 		if (mode == SMA_MODE_IN)
2422 			ptp_ocp_sma_set_output(bp, sma_nr, 0);
2423 		else
2424 			ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
2425 		sma->mode = mode;
2426 	}
2427 
2428 	if (!sma->fixed_dir)
2429 		val |= SMA_ENABLE;		/* add enable bit */
2430 
2431 	if (sma->disabled)
2432 		val = 0;
2433 
2434 	if (mode == SMA_MODE_IN)
2435 		val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
2436 	else
2437 		val = ptp_ocp_sma_set_output(bp, sma_nr, val);
2438 
2439 	return val;
2440 }
2441 
2442 static ssize_t
2443 sma1_store(struct device *dev, struct device_attribute *attr,
2444 	   const char *buf, size_t count)
2445 {
2446 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2447 	int err;
2448 
2449 	err = ptp_ocp_sma_store(bp, buf, 1);
2450 	return err ? err : count;
2451 }
2452 
2453 static ssize_t
2454 sma2_store(struct device *dev, struct device_attribute *attr,
2455 	   const char *buf, size_t count)
2456 {
2457 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2458 	int err;
2459 
2460 	err = ptp_ocp_sma_store(bp, buf, 2);
2461 	return err ? err : count;
2462 }
2463 
2464 static ssize_t
2465 sma3_store(struct device *dev, struct device_attribute *attr,
2466 	   const char *buf, size_t count)
2467 {
2468 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2469 	int err;
2470 
2471 	err = ptp_ocp_sma_store(bp, buf, 3);
2472 	return err ? err : count;
2473 }
2474 
2475 static ssize_t
2476 sma4_store(struct device *dev, struct device_attribute *attr,
2477 	   const char *buf, size_t count)
2478 {
2479 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2480 	int err;
2481 
2482 	err = ptp_ocp_sma_store(bp, buf, 4);
2483 	return err ? err : count;
2484 }
2485 static DEVICE_ATTR_RW(sma1);
2486 static DEVICE_ATTR_RW(sma2);
2487 static DEVICE_ATTR_RW(sma3);
2488 static DEVICE_ATTR_RW(sma4);
2489 
2490 static ssize_t
2491 available_sma_inputs_show(struct device *dev,
2492 			  struct device_attribute *attr, char *buf)
2493 {
2494 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2495 
2496 	return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
2497 }
2498 static DEVICE_ATTR_RO(available_sma_inputs);
2499 
2500 static ssize_t
2501 available_sma_outputs_show(struct device *dev,
2502 			   struct device_attribute *attr, char *buf)
2503 {
2504 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2505 
2506 	return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
2507 }
2508 static DEVICE_ATTR_RO(available_sma_outputs);
2509 
2510 #define EXT_ATTR_RO(_group, _name, _val)				\
2511 	struct dev_ext_attribute dev_attr_##_group##_val##_##_name =	\
2512 		{ __ATTR_RO(_name), (void *)_val }
2513 #define EXT_ATTR_RW(_group, _name, _val)				\
2514 	struct dev_ext_attribute dev_attr_##_group##_val##_##_name =	\
2515 		{ __ATTR_RW(_name), (void *)_val }
2516 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
2517 
2518 /* period [duty [phase [polarity]]] */
2519 static ssize_t
2520 signal_store(struct device *dev, struct device_attribute *attr,
2521 	     const char *buf, size_t count)
2522 {
2523 	struct dev_ext_attribute *ea = to_ext_attr(attr);
2524 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2525 	struct ptp_ocp_signal s = { };
2526 	int gen = (uintptr_t)ea->var;
2527 	int argc, err;
2528 	char **argv;
2529 
2530 	argv = argv_split(GFP_KERNEL, buf, &argc);
2531 	if (!argv)
2532 		return -ENOMEM;
2533 
2534 	err = -EINVAL;
2535 	s.duty = bp->signal[gen].duty;
2536 	s.phase = bp->signal[gen].phase;
2537 	s.period = bp->signal[gen].period;
2538 	s.polarity = bp->signal[gen].polarity;
2539 
2540 	switch (argc) {
2541 	case 4:
2542 		argc--;
2543 		err = kstrtobool(argv[argc], &s.polarity);
2544 		if (err)
2545 			goto out;
2546 		fallthrough;
2547 	case 3:
2548 		argc--;
2549 		err = kstrtou64(argv[argc], 0, &s.phase);
2550 		if (err)
2551 			goto out;
2552 		fallthrough;
2553 	case 2:
2554 		argc--;
2555 		err = kstrtoint(argv[argc], 0, &s.duty);
2556 		if (err)
2557 			goto out;
2558 		fallthrough;
2559 	case 1:
2560 		argc--;
2561 		err = kstrtou64(argv[argc], 0, &s.period);
2562 		if (err)
2563 			goto out;
2564 		break;
2565 	default:
2566 		goto out;
2567 	}
2568 
2569 	err = ptp_ocp_signal_set(bp, gen, &s);
2570 	if (err)
2571 		goto out;
2572 
2573 	err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
2574 
2575 out:
2576 	argv_free(argv);
2577 	return err ? err : count;
2578 }
2579 
2580 static ssize_t
2581 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
2582 {
2583 	struct dev_ext_attribute *ea = to_ext_attr(attr);
2584 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2585 	struct ptp_ocp_signal *signal;
2586 	struct timespec64 ts;
2587 	ssize_t count;
2588 	int i;
2589 
2590 	i = (uintptr_t)ea->var;
2591 	signal = &bp->signal[i];
2592 
2593 	count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,
2594 			   signal->duty, signal->phase, signal->polarity);
2595 
2596 	ts = ktime_to_timespec64(signal->start);
2597 	count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);
2598 
2599 	return count;
2600 }
2601 static EXT_ATTR_RW(signal, signal, 0);
2602 static EXT_ATTR_RW(signal, signal, 1);
2603 static EXT_ATTR_RW(signal, signal, 2);
2604 static EXT_ATTR_RW(signal, signal, 3);
2605 
2606 static ssize_t
2607 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
2608 {
2609 	struct dev_ext_attribute *ea = to_ext_attr(attr);
2610 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2611 	int i = (uintptr_t)ea->var;
2612 
2613 	return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
2614 }
2615 static EXT_ATTR_RO(signal, duty, 0);
2616 static EXT_ATTR_RO(signal, duty, 1);
2617 static EXT_ATTR_RO(signal, duty, 2);
2618 static EXT_ATTR_RO(signal, duty, 3);
2619 
2620 static ssize_t
2621 period_show(struct device *dev, struct device_attribute *attr, char *buf)
2622 {
2623 	struct dev_ext_attribute *ea = to_ext_attr(attr);
2624 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2625 	int i = (uintptr_t)ea->var;
2626 
2627 	return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
2628 }
2629 static EXT_ATTR_RO(signal, period, 0);
2630 static EXT_ATTR_RO(signal, period, 1);
2631 static EXT_ATTR_RO(signal, period, 2);
2632 static EXT_ATTR_RO(signal, period, 3);
2633 
2634 static ssize_t
2635 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
2636 {
2637 	struct dev_ext_attribute *ea = to_ext_attr(attr);
2638 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2639 	int i = (uintptr_t)ea->var;
2640 
2641 	return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
2642 }
2643 static EXT_ATTR_RO(signal, phase, 0);
2644 static EXT_ATTR_RO(signal, phase, 1);
2645 static EXT_ATTR_RO(signal, phase, 2);
2646 static EXT_ATTR_RO(signal, phase, 3);
2647 
2648 static ssize_t
2649 polarity_show(struct device *dev, struct device_attribute *attr,
2650 	      char *buf)
2651 {
2652 	struct dev_ext_attribute *ea = to_ext_attr(attr);
2653 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2654 	int i = (uintptr_t)ea->var;
2655 
2656 	return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
2657 }
2658 static EXT_ATTR_RO(signal, polarity, 0);
2659 static EXT_ATTR_RO(signal, polarity, 1);
2660 static EXT_ATTR_RO(signal, polarity, 2);
2661 static EXT_ATTR_RO(signal, polarity, 3);
2662 
2663 static ssize_t
2664 running_show(struct device *dev, struct device_attribute *attr, char *buf)
2665 {
2666 	struct dev_ext_attribute *ea = to_ext_attr(attr);
2667 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2668 	int i = (uintptr_t)ea->var;
2669 
2670 	return sysfs_emit(buf, "%d\n", bp->signal[i].running);
2671 }
2672 static EXT_ATTR_RO(signal, running, 0);
2673 static EXT_ATTR_RO(signal, running, 1);
2674 static EXT_ATTR_RO(signal, running, 2);
2675 static EXT_ATTR_RO(signal, running, 3);
2676 
2677 static ssize_t
2678 start_show(struct device *dev, struct device_attribute *attr, char *buf)
2679 {
2680 	struct dev_ext_attribute *ea = to_ext_attr(attr);
2681 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2682 	int i = (uintptr_t)ea->var;
2683 	struct timespec64 ts;
2684 
2685 	ts = ktime_to_timespec64(bp->signal[i].start);
2686 	return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
2687 }
2688 static EXT_ATTR_RO(signal, start, 0);
2689 static EXT_ATTR_RO(signal, start, 1);
2690 static EXT_ATTR_RO(signal, start, 2);
2691 static EXT_ATTR_RO(signal, start, 3);
2692 
2693 static ssize_t
2694 seconds_store(struct device *dev, struct device_attribute *attr,
2695 	      const char *buf, size_t count)
2696 {
2697 	struct dev_ext_attribute *ea = to_ext_attr(attr);
2698 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2699 	int idx = (uintptr_t)ea->var;
2700 	u32 val;
2701 	int err;
2702 
2703 	err = kstrtou32(buf, 0, &val);
2704 	if (err)
2705 		return err;
2706 	if (val > 0xff)
2707 		return -EINVAL;
2708 
2709 	if (val)
2710 		val = (val << 8) | 0x1;
2711 
2712 	iowrite32(val, &bp->freq_in[idx]->ctrl);
2713 
2714 	return count;
2715 }
2716 
2717 static ssize_t
2718 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
2719 {
2720 	struct dev_ext_attribute *ea = to_ext_attr(attr);
2721 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2722 	int idx = (uintptr_t)ea->var;
2723 	u32 val;
2724 
2725 	val = ioread32(&bp->freq_in[idx]->ctrl);
2726 	if (val & 1)
2727 		val = (val >> 8) & 0xff;
2728 	else
2729 		val = 0;
2730 
2731 	return sysfs_emit(buf, "%u\n", val);
2732 }
2733 static EXT_ATTR_RW(freq, seconds, 0);
2734 static EXT_ATTR_RW(freq, seconds, 1);
2735 static EXT_ATTR_RW(freq, seconds, 2);
2736 static EXT_ATTR_RW(freq, seconds, 3);
2737 
2738 static ssize_t
2739 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
2740 {
2741 	struct dev_ext_attribute *ea = to_ext_attr(attr);
2742 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2743 	int idx = (uintptr_t)ea->var;
2744 	u32 val;
2745 
2746 	val = ioread32(&bp->freq_in[idx]->status);
2747 	if (val & FREQ_STATUS_ERROR)
2748 		return sysfs_emit(buf, "error\n");
2749 	if (val & FREQ_STATUS_OVERRUN)
2750 		return sysfs_emit(buf, "overrun\n");
2751 	if (val & FREQ_STATUS_VALID)
2752 		return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
2753 	return 0;
2754 }
2755 static EXT_ATTR_RO(freq, frequency, 0);
2756 static EXT_ATTR_RO(freq, frequency, 1);
2757 static EXT_ATTR_RO(freq, frequency, 2);
2758 static EXT_ATTR_RO(freq, frequency, 3);
2759 
2760 static ssize_t
2761 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
2762 {
2763 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2764 
2765 	if (!bp->has_eeprom_data)
2766 		ptp_ocp_read_eeprom(bp);
2767 
2768 	return sysfs_emit(buf, "%pM\n", bp->serial);
2769 }
2770 static DEVICE_ATTR_RO(serialnum);
2771 
2772 static ssize_t
2773 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
2774 {
2775 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2776 	ssize_t ret;
2777 
2778 	if (bp->gnss_lost)
2779 		ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
2780 	else
2781 		ret = sysfs_emit(buf, "SYNC\n");
2782 
2783 	return ret;
2784 }
2785 static DEVICE_ATTR_RO(gnss_sync);
2786 
2787 static ssize_t
2788 utc_tai_offset_show(struct device *dev,
2789 		    struct device_attribute *attr, char *buf)
2790 {
2791 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2792 
2793 	return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
2794 }
2795 
2796 static ssize_t
2797 utc_tai_offset_store(struct device *dev,
2798 		     struct device_attribute *attr,
2799 		     const char *buf, size_t count)
2800 {
2801 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2802 	int err;
2803 	u32 val;
2804 
2805 	err = kstrtou32(buf, 0, &val);
2806 	if (err)
2807 		return err;
2808 
2809 	ptp_ocp_utc_distribute(bp, val);
2810 
2811 	return count;
2812 }
2813 static DEVICE_ATTR_RW(utc_tai_offset);
2814 
2815 static ssize_t
2816 ts_window_adjust_show(struct device *dev,
2817 		      struct device_attribute *attr, char *buf)
2818 {
2819 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2820 
2821 	return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
2822 }
2823 
2824 static ssize_t
2825 ts_window_adjust_store(struct device *dev,
2826 		       struct device_attribute *attr,
2827 		       const char *buf, size_t count)
2828 {
2829 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2830 	int err;
2831 	u32 val;
2832 
2833 	err = kstrtou32(buf, 0, &val);
2834 	if (err)
2835 		return err;
2836 
2837 	bp->ts_window_adjust = val;
2838 
2839 	return count;
2840 }
2841 static DEVICE_ATTR_RW(ts_window_adjust);
2842 
2843 static ssize_t
2844 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
2845 {
2846 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2847 	u32 val;
2848 
2849 	val = ioread32(&bp->irig_out->ctrl);
2850 	val = (val >> 16) & 0x07;
2851 	return sysfs_emit(buf, "%d\n", val);
2852 }
2853 
2854 static ssize_t
2855 irig_b_mode_store(struct device *dev,
2856 		  struct device_attribute *attr,
2857 		  const char *buf, size_t count)
2858 {
2859 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2860 	unsigned long flags;
2861 	int err;
2862 	u32 reg;
2863 	u8 val;
2864 
2865 	err = kstrtou8(buf, 0, &val);
2866 	if (err)
2867 		return err;
2868 	if (val > 7)
2869 		return -EINVAL;
2870 
2871 	reg = ((val & 0x7) << 16);
2872 
2873 	spin_lock_irqsave(&bp->lock, flags);
2874 	iowrite32(0, &bp->irig_out->ctrl);		/* disable */
2875 	iowrite32(reg, &bp->irig_out->ctrl);		/* change mode */
2876 	iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
2877 	spin_unlock_irqrestore(&bp->lock, flags);
2878 
2879 	return count;
2880 }
2881 static DEVICE_ATTR_RW(irig_b_mode);
2882 
2883 static ssize_t
2884 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
2885 {
2886 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2887 	const char *p;
2888 	u32 select;
2889 
2890 	select = ioread32(&bp->reg->select);
2891 	p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
2892 
2893 	return sysfs_emit(buf, "%s\n", p);
2894 }
2895 
2896 static ssize_t
2897 clock_source_store(struct device *dev, struct device_attribute *attr,
2898 		   const char *buf, size_t count)
2899 {
2900 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2901 	unsigned long flags;
2902 	int val;
2903 
2904 	val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
2905 	if (val < 0)
2906 		return val;
2907 
2908 	spin_lock_irqsave(&bp->lock, flags);
2909 	iowrite32(val, &bp->reg->select);
2910 	spin_unlock_irqrestore(&bp->lock, flags);
2911 
2912 	return count;
2913 }
2914 static DEVICE_ATTR_RW(clock_source);
2915 
2916 static ssize_t
2917 available_clock_sources_show(struct device *dev,
2918 			     struct device_attribute *attr, char *buf)
2919 {
2920 	return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
2921 }
2922 static DEVICE_ATTR_RO(available_clock_sources);
2923 
2924 static ssize_t
2925 clock_status_drift_show(struct device *dev,
2926 			struct device_attribute *attr, char *buf)
2927 {
2928 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2929 	u32 val;
2930 	int res;
2931 
2932 	val = ioread32(&bp->reg->status_drift);
2933 	res = (val & ~INT_MAX) ? -1 : 1;
2934 	res *= (val & INT_MAX);
2935 	return sysfs_emit(buf, "%d\n", res);
2936 }
2937 static DEVICE_ATTR_RO(clock_status_drift);
2938 
2939 static ssize_t
2940 clock_status_offset_show(struct device *dev,
2941 			 struct device_attribute *attr, char *buf)
2942 {
2943 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2944 	u32 val;
2945 	int res;
2946 
2947 	val = ioread32(&bp->reg->status_offset);
2948 	res = (val & ~INT_MAX) ? -1 : 1;
2949 	res *= (val & INT_MAX);
2950 	return sysfs_emit(buf, "%d\n", res);
2951 }
2952 static DEVICE_ATTR_RO(clock_status_offset);
2953 
2954 static ssize_t
2955 tod_correction_show(struct device *dev,
2956 		    struct device_attribute *attr, char *buf)
2957 {
2958 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2959 	u32 val;
2960 	int res;
2961 
2962 	val = ioread32(&bp->tod->adj_sec);
2963 	res = (val & ~INT_MAX) ? -1 : 1;
2964 	res *= (val & INT_MAX);
2965 	return sysfs_emit(buf, "%d\n", res);
2966 }
2967 
2968 static ssize_t
2969 tod_correction_store(struct device *dev, struct device_attribute *attr,
2970 		     const char *buf, size_t count)
2971 {
2972 	struct ptp_ocp *bp = dev_get_drvdata(dev);
2973 	unsigned long flags;
2974 	int err, res;
2975 	u32 val = 0;
2976 
2977 	err = kstrtos32(buf, 0, &res);
2978 	if (err)
2979 		return err;
2980 	if (res < 0) {
2981 		res *= -1;
2982 		val |= BIT(31);
2983 	}
2984 	val |= res;
2985 
2986 	spin_lock_irqsave(&bp->lock, flags);
2987 	iowrite32(val, &bp->tod->adj_sec);
2988 	spin_unlock_irqrestore(&bp->lock, flags);
2989 
2990 	return count;
2991 }
2992 static DEVICE_ATTR_RW(tod_correction);
2993 
2994 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr)					\
2995 	static struct attribute *fb_timecard_signal##_nr##_attrs[] = {	\
2996 		&dev_attr_signal##_nr##_signal.attr.attr,		\
2997 		&dev_attr_signal##_nr##_duty.attr.attr,			\
2998 		&dev_attr_signal##_nr##_phase.attr.attr,		\
2999 		&dev_attr_signal##_nr##_period.attr.attr,		\
3000 		&dev_attr_signal##_nr##_polarity.attr.attr,		\
3001 		&dev_attr_signal##_nr##_running.attr.attr,		\
3002 		&dev_attr_signal##_nr##_start.attr.attr,		\
3003 		NULL,							\
3004 	}
3005 
3006 #define DEVICE_SIGNAL_GROUP(_name, _nr)					\
3007 	_DEVICE_SIGNAL_GROUP_ATTRS(_nr);				\
3008 	static const struct attribute_group				\
3009 			fb_timecard_signal##_nr##_group = {		\
3010 		.name = #_name,						\
3011 		.attrs = fb_timecard_signal##_nr##_attrs,		\
3012 }
3013 
3014 DEVICE_SIGNAL_GROUP(gen1, 0);
3015 DEVICE_SIGNAL_GROUP(gen2, 1);
3016 DEVICE_SIGNAL_GROUP(gen3, 2);
3017 DEVICE_SIGNAL_GROUP(gen4, 3);
3018 
3019 #define _DEVICE_FREQ_GROUP_ATTRS(_nr)					\
3020 	static struct attribute *fb_timecard_freq##_nr##_attrs[] = {	\
3021 		&dev_attr_freq##_nr##_seconds.attr.attr,		\
3022 		&dev_attr_freq##_nr##_frequency.attr.attr,		\
3023 		NULL,							\
3024 	}
3025 
3026 #define DEVICE_FREQ_GROUP(_name, _nr)					\
3027 	_DEVICE_FREQ_GROUP_ATTRS(_nr);					\
3028 	static const struct attribute_group				\
3029 			fb_timecard_freq##_nr##_group = {		\
3030 		.name = #_name,						\
3031 		.attrs = fb_timecard_freq##_nr##_attrs,			\
3032 }
3033 
3034 DEVICE_FREQ_GROUP(freq1, 0);
3035 DEVICE_FREQ_GROUP(freq2, 1);
3036 DEVICE_FREQ_GROUP(freq3, 2);
3037 DEVICE_FREQ_GROUP(freq4, 3);
3038 
3039 static struct attribute *fb_timecard_attrs[] = {
3040 	&dev_attr_serialnum.attr,
3041 	&dev_attr_gnss_sync.attr,
3042 	&dev_attr_clock_source.attr,
3043 	&dev_attr_available_clock_sources.attr,
3044 	&dev_attr_sma1.attr,
3045 	&dev_attr_sma2.attr,
3046 	&dev_attr_sma3.attr,
3047 	&dev_attr_sma4.attr,
3048 	&dev_attr_available_sma_inputs.attr,
3049 	&dev_attr_available_sma_outputs.attr,
3050 	&dev_attr_clock_status_drift.attr,
3051 	&dev_attr_clock_status_offset.attr,
3052 	&dev_attr_irig_b_mode.attr,
3053 	&dev_attr_utc_tai_offset.attr,
3054 	&dev_attr_ts_window_adjust.attr,
3055 	&dev_attr_tod_correction.attr,
3056 	NULL,
3057 };
3058 static const struct attribute_group fb_timecard_group = {
3059 	.attrs = fb_timecard_attrs,
3060 };
3061 static const struct ocp_attr_group fb_timecard_groups[] = {
3062 	{ .cap = OCP_CAP_BASIC,	    .group = &fb_timecard_group },
3063 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal0_group },
3064 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal1_group },
3065 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal2_group },
3066 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal3_group },
3067 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq0_group },
3068 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq1_group },
3069 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq2_group },
3070 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq3_group },
3071 	{ },
3072 };
3073 
3074 static void
3075 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3076 	       const char *def)
3077 {
3078 	int i;
3079 
3080 	for (i = 0; i < 4; i++) {
3081 		if (bp->sma[i].mode != SMA_MODE_IN)
3082 			continue;
3083 		if (map[i][0] & (1 << bit)) {
3084 			sprintf(buf, "sma%d", i + 1);
3085 			return;
3086 		}
3087 	}
3088 	if (!def)
3089 		def = "----";
3090 	strcpy(buf, def);
3091 }
3092 
3093 static void
3094 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
3095 {
3096 	char *ans = buf;
3097 	int i;
3098 
3099 	strcpy(ans, "----");
3100 	for (i = 0; i < 4; i++) {
3101 		if (bp->sma[i].mode != SMA_MODE_OUT)
3102 			continue;
3103 		if (map[i][1] & (1 << bit))
3104 			ans += sprintf(ans, "sma%d ", i + 1);
3105 	}
3106 }
3107 
3108 static void
3109 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
3110 {
3111 	struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
3112 	struct ptp_ocp_signal *signal = &bp->signal[nr];
3113 	char label[8];
3114 	bool on;
3115 	u32 val;
3116 
3117 	if (!signal)
3118 		return;
3119 
3120 	on = signal->running;
3121 	sprintf(label, "GEN%d", nr + 1);
3122 	seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
3123 		   label, on ? " ON" : "OFF",
3124 		   signal->period, signal->duty, signal->phase,
3125 		   signal->polarity);
3126 
3127 	val = ioread32(&reg->enable);
3128 	seq_printf(s, " [%x", val);
3129 	val = ioread32(&reg->status);
3130 	seq_printf(s, " %x]", val);
3131 
3132 	seq_printf(s, " start:%llu\n", signal->start);
3133 }
3134 
3135 static void
3136 _frequency_summary_show(struct seq_file *s, int nr,
3137 			struct frequency_reg __iomem *reg)
3138 {
3139 	char label[8];
3140 	bool on;
3141 	u32 val;
3142 
3143 	if (!reg)
3144 		return;
3145 
3146 	sprintf(label, "FREQ%d", nr + 1);
3147 	val = ioread32(&reg->ctrl);
3148 	on = val & 1;
3149 	val = (val >> 8) & 0xff;
3150 	seq_printf(s, "%7s: %s, sec:%u",
3151 		   label,
3152 		   on ? " ON" : "OFF",
3153 		   val);
3154 
3155 	val = ioread32(&reg->status);
3156 	if (val & FREQ_STATUS_ERROR)
3157 		seq_printf(s, ", error");
3158 	if (val & FREQ_STATUS_OVERRUN)
3159 		seq_printf(s, ", overrun");
3160 	if (val & FREQ_STATUS_VALID)
3161 		seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
3162 	seq_printf(s, "  reg:%x\n", val);
3163 }
3164 
3165 static int
3166 ptp_ocp_summary_show(struct seq_file *s, void *data)
3167 {
3168 	struct device *dev = s->private;
3169 	struct ptp_system_timestamp sts;
3170 	struct ts_reg __iomem *ts_reg;
3171 	char *buf, *src, *mac_src;
3172 	struct timespec64 ts;
3173 	struct ptp_ocp *bp;
3174 	u16 sma_val[4][2];
3175 	u32 ctrl, val;
3176 	bool on, map;
3177 	int i;
3178 
3179 	buf = (char *)__get_free_page(GFP_KERNEL);
3180 	if (!buf)
3181 		return -ENOMEM;
3182 
3183 	bp = dev_get_drvdata(dev);
3184 
3185 	seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
3186 	if (bp->gnss_port != -1)
3187 		seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS1", bp->gnss_port);
3188 	if (bp->gnss2_port != -1)
3189 		seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS2", bp->gnss2_port);
3190 	if (bp->mac_port != -1)
3191 		seq_printf(s, "%7s: /dev/ttyS%d\n", "MAC", bp->mac_port);
3192 	if (bp->nmea_port != -1)
3193 		seq_printf(s, "%7s: /dev/ttyS%d\n", "NMEA", bp->nmea_port);
3194 
3195 	memset(sma_val, 0xff, sizeof(sma_val));
3196 	if (bp->sma_map1) {
3197 		u32 reg;
3198 
3199 		reg = ioread32(&bp->sma_map1->gpio1);
3200 		sma_val[0][0] = reg & 0xffff;
3201 		sma_val[1][0] = reg >> 16;
3202 
3203 		reg = ioread32(&bp->sma_map1->gpio2);
3204 		sma_val[2][1] = reg & 0xffff;
3205 		sma_val[3][1] = reg >> 16;
3206 
3207 		reg = ioread32(&bp->sma_map2->gpio1);
3208 		sma_val[2][0] = reg & 0xffff;
3209 		sma_val[3][0] = reg >> 16;
3210 
3211 		reg = ioread32(&bp->sma_map2->gpio2);
3212 		sma_val[0][1] = reg & 0xffff;
3213 		sma_val[1][1] = reg >> 16;
3214 	}
3215 
3216 	sma1_show(dev, NULL, buf);
3217 	seq_printf(s, "   sma1: %04x,%04x %s",
3218 		   sma_val[0][0], sma_val[0][1], buf);
3219 
3220 	sma2_show(dev, NULL, buf);
3221 	seq_printf(s, "   sma2: %04x,%04x %s",
3222 		   sma_val[1][0], sma_val[1][1], buf);
3223 
3224 	sma3_show(dev, NULL, buf);
3225 	seq_printf(s, "   sma3: %04x,%04x %s",
3226 		   sma_val[2][0], sma_val[2][1], buf);
3227 
3228 	sma4_show(dev, NULL, buf);
3229 	seq_printf(s, "   sma4: %04x,%04x %s",
3230 		   sma_val[3][0], sma_val[3][1], buf);
3231 
3232 	if (bp->ts0) {
3233 		ts_reg = bp->ts0->mem;
3234 		on = ioread32(&ts_reg->enable);
3235 		src = "GNSS1";
3236 		seq_printf(s, "%7s: %s, src: %s\n", "TS0",
3237 			   on ? " ON" : "OFF", src);
3238 	}
3239 
3240 	if (bp->ts1) {
3241 		ts_reg = bp->ts1->mem;
3242 		on = ioread32(&ts_reg->enable);
3243 		gpio_input_map(buf, bp, sma_val, 2, NULL);
3244 		seq_printf(s, "%7s: %s, src: %s\n", "TS1",
3245 			   on ? " ON" : "OFF", buf);
3246 	}
3247 
3248 	if (bp->ts2) {
3249 		ts_reg = bp->ts2->mem;
3250 		on = ioread32(&ts_reg->enable);
3251 		gpio_input_map(buf, bp, sma_val, 3, NULL);
3252 		seq_printf(s, "%7s: %s, src: %s\n", "TS2",
3253 			   on ? " ON" : "OFF", buf);
3254 	}
3255 
3256 	if (bp->ts3) {
3257 		ts_reg = bp->ts3->mem;
3258 		on = ioread32(&ts_reg->enable);
3259 		gpio_input_map(buf, bp, sma_val, 6, NULL);
3260 		seq_printf(s, "%7s: %s, src: %s\n", "TS3",
3261 			   on ? " ON" : "OFF", buf);
3262 	}
3263 
3264 	if (bp->ts4) {
3265 		ts_reg = bp->ts4->mem;
3266 		on = ioread32(&ts_reg->enable);
3267 		gpio_input_map(buf, bp, sma_val, 7, NULL);
3268 		seq_printf(s, "%7s: %s, src: %s\n", "TS4",
3269 			   on ? " ON" : "OFF", buf);
3270 	}
3271 
3272 	if (bp->pps) {
3273 		ts_reg = bp->pps->mem;
3274 		src = "PHC";
3275 		on = ioread32(&ts_reg->enable);
3276 		map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
3277 		seq_printf(s, "%7s: %s, src: %s\n", "TS5",
3278 			   on && map ? " ON" : "OFF", src);
3279 
3280 		map = !!(bp->pps_req_map & OCP_REQ_PPS);
3281 		seq_printf(s, "%7s: %s, src: %s\n", "PPS",
3282 			   on && map ? " ON" : "OFF", src);
3283 	}
3284 
3285 	if (bp->fw_cap & OCP_CAP_SIGNAL)
3286 		for (i = 0; i < 4; i++)
3287 			_signal_summary_show(s, bp, i);
3288 
3289 	if (bp->fw_cap & OCP_CAP_FREQ)
3290 		for (i = 0; i < 4; i++)
3291 			_frequency_summary_show(s, i, bp->freq_in[i]);
3292 
3293 	if (bp->irig_out) {
3294 		ctrl = ioread32(&bp->irig_out->ctrl);
3295 		on = ctrl & IRIG_M_CTRL_ENABLE;
3296 		val = ioread32(&bp->irig_out->status);
3297 		gpio_output_map(buf, bp, sma_val, 4);
3298 		seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
3299 			   on ? " ON" : "OFF", val, (ctrl >> 16), buf);
3300 	}
3301 
3302 	if (bp->irig_in) {
3303 		on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
3304 		val = ioread32(&bp->irig_in->status);
3305 		gpio_input_map(buf, bp, sma_val, 4, NULL);
3306 		seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
3307 			   on ? " ON" : "OFF", val, buf);
3308 	}
3309 
3310 	if (bp->dcf_out) {
3311 		on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
3312 		val = ioread32(&bp->dcf_out->status);
3313 		gpio_output_map(buf, bp, sma_val, 5);
3314 		seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
3315 			   on ? " ON" : "OFF", val, buf);
3316 	}
3317 
3318 	if (bp->dcf_in) {
3319 		on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
3320 		val = ioread32(&bp->dcf_in->status);
3321 		gpio_input_map(buf, bp, sma_val, 5, NULL);
3322 		seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
3323 			   on ? " ON" : "OFF", val, buf);
3324 	}
3325 
3326 	if (bp->nmea_out) {
3327 		on = ioread32(&bp->nmea_out->ctrl) & 1;
3328 		val = ioread32(&bp->nmea_out->status);
3329 		seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
3330 			   on ? " ON" : "OFF", val);
3331 	}
3332 
3333 	/* compute src for PPS1, used below. */
3334 	if (bp->pps_select) {
3335 		val = ioread32(&bp->pps_select->gpio1);
3336 		src = &buf[80];
3337 		mac_src = "GNSS1";
3338 		if (val & 0x01) {
3339 			gpio_input_map(src, bp, sma_val, 0, NULL);
3340 			mac_src = src;
3341 		} else if (val & 0x02) {
3342 			src = "MAC";
3343 		} else if (val & 0x04) {
3344 			src = "GNSS1";
3345 		} else {
3346 			src = "----";
3347 			mac_src = src;
3348 		}
3349 	} else {
3350 		src = "?";
3351 		mac_src = src;
3352 	}
3353 	seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
3354 
3355 	gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
3356 	seq_printf(s, "MAC PPS2 src: %s\n", buf);
3357 
3358 	/* assumes automatic switchover/selection */
3359 	val = ioread32(&bp->reg->select);
3360 	switch (val >> 16) {
3361 	case 0:
3362 		sprintf(buf, "----");
3363 		break;
3364 	case 2:
3365 		sprintf(buf, "IRIG");
3366 		break;
3367 	case 3:
3368 		sprintf(buf, "%s via PPS1", src);
3369 		break;
3370 	case 6:
3371 		sprintf(buf, "DCF");
3372 		break;
3373 	default:
3374 		strcpy(buf, "unknown");
3375 		break;
3376 	}
3377 	val = ioread32(&bp->reg->status);
3378 	seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
3379 		   val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced");
3380 
3381 	if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
3382 		struct timespec64 sys_ts;
3383 		s64 pre_ns, post_ns, ns;
3384 
3385 		pre_ns = timespec64_to_ns(&sts.pre_ts);
3386 		post_ns = timespec64_to_ns(&sts.post_ts);
3387 		ns = (pre_ns + post_ns) / 2;
3388 		ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
3389 		sys_ts = ns_to_timespec64(ns);
3390 
3391 		seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
3392 			   ts.tv_sec, ts.tv_nsec, &ts);
3393 		seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
3394 			   sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
3395 			   bp->utc_tai_offset);
3396 		seq_printf(s, "%7s: PHC:SYS offset: %lld  window: %lld\n", "",
3397 			   timespec64_to_ns(&ts) - ns,
3398 			   post_ns - pre_ns);
3399 	}
3400 
3401 	free_page((unsigned long)buf);
3402 	return 0;
3403 }
3404 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
3405 
3406 static int
3407 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
3408 {
3409 	struct device *dev = s->private;
3410 	struct ptp_ocp *bp;
3411 	u32 val;
3412 	int idx;
3413 
3414 	bp = dev_get_drvdata(dev);
3415 
3416 	val = ioread32(&bp->tod->ctrl);
3417 	if (!(val & TOD_CTRL_ENABLE)) {
3418 		seq_printf(s, "TOD Slave disabled\n");
3419 		return 0;
3420 	}
3421 	seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
3422 
3423 	idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
3424 	idx += (val >> 16) & 3;
3425 	seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
3426 
3427 	idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
3428 	seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
3429 
3430 	val = ioread32(&bp->tod->version);
3431 	seq_printf(s, "TOD Version %d.%d.%d\n",
3432 		val >> 24, (val >> 16) & 0xff, val & 0xffff);
3433 
3434 	val = ioread32(&bp->tod->status);
3435 	seq_printf(s, "Status register: 0x%08X\n", val);
3436 
3437 	val = ioread32(&bp->tod->adj_sec);
3438 	idx = (val & ~INT_MAX) ? -1 : 1;
3439 	idx *= (val & INT_MAX);
3440 	seq_printf(s, "Correction seconds: %d\n", idx);
3441 
3442 	val = ioread32(&bp->tod->utc_status);
3443 	seq_printf(s, "UTC status register: 0x%08X\n", val);
3444 	seq_printf(s, "UTC offset: %ld  valid:%d\n",
3445 		val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
3446 	seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
3447 		val & TOD_STATUS_LEAP_VALID ? 1 : 0,
3448 		val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
3449 
3450 	val = ioread32(&bp->tod->leap);
3451 	seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
3452 
3453 	return 0;
3454 }
3455 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
3456 
3457 static struct dentry *ptp_ocp_debugfs_root;
3458 
3459 static void
3460 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
3461 {
3462 	struct dentry *d;
3463 
3464 	d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
3465 	bp->debug_root = d;
3466 	debugfs_create_file("summary", 0444, bp->debug_root,
3467 			    &bp->dev, &ptp_ocp_summary_fops);
3468 	if (bp->tod)
3469 		debugfs_create_file("tod_status", 0444, bp->debug_root,
3470 				    &bp->dev, &ptp_ocp_tod_status_fops);
3471 }
3472 
3473 static void
3474 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
3475 {
3476 	debugfs_remove_recursive(bp->debug_root);
3477 }
3478 
3479 static void
3480 ptp_ocp_debugfs_init(void)
3481 {
3482 	ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
3483 }
3484 
3485 static void
3486 ptp_ocp_debugfs_fini(void)
3487 {
3488 	debugfs_remove_recursive(ptp_ocp_debugfs_root);
3489 }
3490 
3491 static void
3492 ptp_ocp_dev_release(struct device *dev)
3493 {
3494 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3495 
3496 	mutex_lock(&ptp_ocp_lock);
3497 	idr_remove(&ptp_ocp_idr, bp->id);
3498 	mutex_unlock(&ptp_ocp_lock);
3499 }
3500 
3501 static int
3502 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
3503 {
3504 	int err;
3505 
3506 	mutex_lock(&ptp_ocp_lock);
3507 	err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
3508 	mutex_unlock(&ptp_ocp_lock);
3509 	if (err < 0) {
3510 		dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
3511 		return err;
3512 	}
3513 	bp->id = err;
3514 
3515 	bp->ptp_info = ptp_ocp_clock_info;
3516 	spin_lock_init(&bp->lock);
3517 	bp->gnss_port = -1;
3518 	bp->gnss2_port = -1;
3519 	bp->mac_port = -1;
3520 	bp->nmea_port = -1;
3521 	bp->pdev = pdev;
3522 
3523 	device_initialize(&bp->dev);
3524 	dev_set_name(&bp->dev, "ocp%d", bp->id);
3525 	bp->dev.class = &timecard_class;
3526 	bp->dev.parent = &pdev->dev;
3527 	bp->dev.release = ptp_ocp_dev_release;
3528 	dev_set_drvdata(&bp->dev, bp);
3529 
3530 	err = device_add(&bp->dev);
3531 	if (err) {
3532 		dev_err(&bp->dev, "device add failed: %d\n", err);
3533 		goto out;
3534 	}
3535 
3536 	pci_set_drvdata(pdev, bp);
3537 
3538 	return 0;
3539 
3540 out:
3541 	ptp_ocp_dev_release(&bp->dev);
3542 	put_device(&bp->dev);
3543 	return err;
3544 }
3545 
3546 static void
3547 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
3548 {
3549 	struct device *dev = &bp->dev;
3550 
3551 	if (sysfs_create_link(&dev->kobj, &child->kobj, link))
3552 		dev_err(dev, "%s symlink failed\n", link);
3553 }
3554 
3555 static void
3556 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
3557 {
3558 	struct device *dev, *child;
3559 
3560 	dev = &bp->pdev->dev;
3561 
3562 	child = device_find_child_by_name(dev, name);
3563 	if (!child) {
3564 		dev_err(dev, "Could not find device %s\n", name);
3565 		return;
3566 	}
3567 
3568 	ptp_ocp_symlink(bp, child, link);
3569 	put_device(child);
3570 }
3571 
3572 static int
3573 ptp_ocp_complete(struct ptp_ocp *bp)
3574 {
3575 	struct pps_device *pps;
3576 	char buf[32];
3577 
3578 	if (bp->gnss_port != -1) {
3579 		sprintf(buf, "ttyS%d", bp->gnss_port);
3580 		ptp_ocp_link_child(bp, buf, "ttyGNSS");
3581 	}
3582 	if (bp->gnss2_port != -1) {
3583 		sprintf(buf, "ttyS%d", bp->gnss2_port);
3584 		ptp_ocp_link_child(bp, buf, "ttyGNSS2");
3585 	}
3586 	if (bp->mac_port != -1) {
3587 		sprintf(buf, "ttyS%d", bp->mac_port);
3588 		ptp_ocp_link_child(bp, buf, "ttyMAC");
3589 	}
3590 	if (bp->nmea_port != -1) {
3591 		sprintf(buf, "ttyS%d", bp->nmea_port);
3592 		ptp_ocp_link_child(bp, buf, "ttyNMEA");
3593 	}
3594 	sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
3595 	ptp_ocp_link_child(bp, buf, "ptp");
3596 
3597 	pps = pps_lookup_dev(bp->ptp);
3598 	if (pps)
3599 		ptp_ocp_symlink(bp, pps->dev, "pps");
3600 
3601 	ptp_ocp_debugfs_add_device(bp);
3602 
3603 	return 0;
3604 }
3605 
3606 static void
3607 ptp_ocp_phc_info(struct ptp_ocp *bp)
3608 {
3609 	struct timespec64 ts;
3610 	u32 version, select;
3611 	bool sync;
3612 
3613 	version = ioread32(&bp->reg->version);
3614 	select = ioread32(&bp->reg->select);
3615 	dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
3616 		 version >> 24, (version >> 16) & 0xff, version & 0xffff,
3617 		 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
3618 		 ptp_clock_index(bp->ptp));
3619 
3620 	sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
3621 	if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
3622 		dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
3623 			 ts.tv_sec, ts.tv_nsec,
3624 			 sync ? "in-sync" : "UNSYNCED");
3625 }
3626 
3627 static void
3628 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
3629 {
3630 	if (port != -1)
3631 		dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
3632 }
3633 
3634 static void
3635 ptp_ocp_info(struct ptp_ocp *bp)
3636 {
3637 	static int nmea_baud[] = {
3638 		1200, 2400, 4800, 9600, 19200, 38400,
3639 		57600, 115200, 230400, 460800, 921600,
3640 		1000000, 2000000
3641 	};
3642 	struct device *dev = &bp->pdev->dev;
3643 	u32 reg;
3644 
3645 	ptp_ocp_phc_info(bp);
3646 
3647 	ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port, 115200);
3648 	ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port, 115200);
3649 	ptp_ocp_serial_info(dev, "MAC", bp->mac_port, 57600);
3650 	if (bp->nmea_out && bp->nmea_port != -1) {
3651 		int baud = -1;
3652 
3653 		reg = ioread32(&bp->nmea_out->uart_baud);
3654 		if (reg < ARRAY_SIZE(nmea_baud))
3655 			baud = nmea_baud[reg];
3656 		ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port, baud);
3657 	}
3658 }
3659 
3660 static void
3661 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
3662 {
3663 	struct device *dev = &bp->dev;
3664 
3665 	sysfs_remove_link(&dev->kobj, "ttyGNSS");
3666 	sysfs_remove_link(&dev->kobj, "ttyMAC");
3667 	sysfs_remove_link(&dev->kobj, "ptp");
3668 	sysfs_remove_link(&dev->kobj, "pps");
3669 }
3670 
3671 static void
3672 ptp_ocp_detach(struct ptp_ocp *bp)
3673 {
3674 	int i;
3675 
3676 	ptp_ocp_debugfs_remove_device(bp);
3677 	ptp_ocp_detach_sysfs(bp);
3678 	ptp_ocp_attr_group_del(bp);
3679 	if (timer_pending(&bp->watchdog))
3680 		del_timer_sync(&bp->watchdog);
3681 	if (bp->ts0)
3682 		ptp_ocp_unregister_ext(bp->ts0);
3683 	if (bp->ts1)
3684 		ptp_ocp_unregister_ext(bp->ts1);
3685 	if (bp->ts2)
3686 		ptp_ocp_unregister_ext(bp->ts2);
3687 	if (bp->ts3)
3688 		ptp_ocp_unregister_ext(bp->ts3);
3689 	if (bp->ts4)
3690 		ptp_ocp_unregister_ext(bp->ts4);
3691 	if (bp->pps)
3692 		ptp_ocp_unregister_ext(bp->pps);
3693 	for (i = 0; i < 4; i++)
3694 		if (bp->signal_out[i])
3695 			ptp_ocp_unregister_ext(bp->signal_out[i]);
3696 	if (bp->gnss_port != -1)
3697 		serial8250_unregister_port(bp->gnss_port);
3698 	if (bp->gnss2_port != -1)
3699 		serial8250_unregister_port(bp->gnss2_port);
3700 	if (bp->mac_port != -1)
3701 		serial8250_unregister_port(bp->mac_port);
3702 	if (bp->nmea_port != -1)
3703 		serial8250_unregister_port(bp->nmea_port);
3704 	platform_device_unregister(bp->spi_flash);
3705 	platform_device_unregister(bp->i2c_ctrl);
3706 	if (bp->i2c_clk)
3707 		clk_hw_unregister_fixed_rate(bp->i2c_clk);
3708 	if (bp->n_irqs)
3709 		pci_free_irq_vectors(bp->pdev);
3710 	if (bp->ptp)
3711 		ptp_clock_unregister(bp->ptp);
3712 	kfree(bp->ptp_info.pin_config);
3713 	device_unregister(&bp->dev);
3714 }
3715 
3716 static int
3717 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3718 {
3719 	struct devlink *devlink;
3720 	struct ptp_ocp *bp;
3721 	int err;
3722 
3723 	devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
3724 	if (!devlink) {
3725 		dev_err(&pdev->dev, "devlink_alloc failed\n");
3726 		return -ENOMEM;
3727 	}
3728 
3729 	err = pci_enable_device(pdev);
3730 	if (err) {
3731 		dev_err(&pdev->dev, "pci_enable_device\n");
3732 		goto out_free;
3733 	}
3734 
3735 	bp = devlink_priv(devlink);
3736 	err = ptp_ocp_device_init(bp, pdev);
3737 	if (err)
3738 		goto out_disable;
3739 
3740 	/* compat mode.
3741 	 * Older FPGA firmware only returns 2 irq's.
3742 	 * allow this - if not all of the IRQ's are returned, skip the
3743 	 * extra devices and just register the clock.
3744 	 */
3745 	err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
3746 	if (err < 0) {
3747 		dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
3748 		goto out;
3749 	}
3750 	bp->n_irqs = err;
3751 	pci_set_master(pdev);
3752 
3753 	err = ptp_ocp_register_resources(bp, id->driver_data);
3754 	if (err)
3755 		goto out;
3756 
3757 	bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
3758 	if (IS_ERR(bp->ptp)) {
3759 		err = PTR_ERR(bp->ptp);
3760 		dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
3761 		bp->ptp = NULL;
3762 		goto out;
3763 	}
3764 
3765 	err = ptp_ocp_complete(bp);
3766 	if (err)
3767 		goto out;
3768 
3769 	ptp_ocp_info(bp);
3770 	devlink_register(devlink);
3771 	return 0;
3772 
3773 out:
3774 	ptp_ocp_detach(bp);
3775 out_disable:
3776 	pci_disable_device(pdev);
3777 out_free:
3778 	devlink_free(devlink);
3779 	return err;
3780 }
3781 
3782 static void
3783 ptp_ocp_remove(struct pci_dev *pdev)
3784 {
3785 	struct ptp_ocp *bp = pci_get_drvdata(pdev);
3786 	struct devlink *devlink = priv_to_devlink(bp);
3787 
3788 	devlink_unregister(devlink);
3789 	ptp_ocp_detach(bp);
3790 	pci_disable_device(pdev);
3791 
3792 	devlink_free(devlink);
3793 }
3794 
3795 static struct pci_driver ptp_ocp_driver = {
3796 	.name		= KBUILD_MODNAME,
3797 	.id_table	= ptp_ocp_pcidev_id,
3798 	.probe		= ptp_ocp_probe,
3799 	.remove		= ptp_ocp_remove,
3800 };
3801 
3802 static int
3803 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
3804 			  unsigned long action, void *data)
3805 {
3806 	struct device *dev, *child = data;
3807 	struct ptp_ocp *bp;
3808 	bool add;
3809 
3810 	switch (action) {
3811 	case BUS_NOTIFY_ADD_DEVICE:
3812 	case BUS_NOTIFY_DEL_DEVICE:
3813 		add = action == BUS_NOTIFY_ADD_DEVICE;
3814 		break;
3815 	default:
3816 		return 0;
3817 	}
3818 
3819 	if (!i2c_verify_adapter(child))
3820 		return 0;
3821 
3822 	dev = child;
3823 	while ((dev = dev->parent))
3824 		if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
3825 			goto found;
3826 	return 0;
3827 
3828 found:
3829 	bp = dev_get_drvdata(dev);
3830 	if (add)
3831 		ptp_ocp_symlink(bp, child, "i2c");
3832 	else
3833 		sysfs_remove_link(&bp->dev.kobj, "i2c");
3834 
3835 	return 0;
3836 }
3837 
3838 static struct notifier_block ptp_ocp_i2c_notifier = {
3839 	.notifier_call = ptp_ocp_i2c_notifier_call,
3840 };
3841 
3842 static int __init
3843 ptp_ocp_init(void)
3844 {
3845 	const char *what;
3846 	int err;
3847 
3848 	ptp_ocp_debugfs_init();
3849 
3850 	what = "timecard class";
3851 	err = class_register(&timecard_class);
3852 	if (err)
3853 		goto out;
3854 
3855 	what = "i2c notifier";
3856 	err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
3857 	if (err)
3858 		goto out_notifier;
3859 
3860 	what = "ptp_ocp driver";
3861 	err = pci_register_driver(&ptp_ocp_driver);
3862 	if (err)
3863 		goto out_register;
3864 
3865 	return 0;
3866 
3867 out_register:
3868 	bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
3869 out_notifier:
3870 	class_unregister(&timecard_class);
3871 out:
3872 	ptp_ocp_debugfs_fini();
3873 	pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
3874 	return err;
3875 }
3876 
3877 static void __exit
3878 ptp_ocp_fini(void)
3879 {
3880 	bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
3881 	pci_unregister_driver(&ptp_ocp_driver);
3882 	class_unregister(&timecard_class);
3883 	ptp_ocp_debugfs_fini();
3884 }
3885 
3886 module_init(ptp_ocp_init);
3887 module_exit(ptp_ocp_fini);
3888 
3889 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
3890 MODULE_LICENSE("GPL v2");
3891