1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2020 Facebook */ 3 4 #include <linux/bits.h> 5 #include <linux/err.h> 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/debugfs.h> 9 #include <linux/init.h> 10 #include <linux/pci.h> 11 #include <linux/serial_8250.h> 12 #include <linux/clkdev.h> 13 #include <linux/clk-provider.h> 14 #include <linux/platform_device.h> 15 #include <linux/platform_data/i2c-xiic.h> 16 #include <linux/platform_data/i2c-ocores.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/spi/spi.h> 19 #include <linux/spi/xilinx_spi.h> 20 #include <linux/spi/altera.h> 21 #include <net/devlink.h> 22 #include <linux/i2c.h> 23 #include <linux/mtd/mtd.h> 24 #include <linux/nvmem-consumer.h> 25 #include <linux/crc16.h> 26 27 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b 28 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400 29 30 #define PCI_VENDOR_ID_CELESTICA 0x18d4 31 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008 32 33 #define PCI_VENDOR_ID_OROLIA 0x1ad7 34 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000 35 36 static struct class timecard_class = { 37 .name = "timecard", 38 }; 39 40 struct ocp_reg { 41 u32 ctrl; 42 u32 status; 43 u32 select; 44 u32 version; 45 u32 time_ns; 46 u32 time_sec; 47 u32 __pad0[2]; 48 u32 adjust_ns; 49 u32 adjust_sec; 50 u32 __pad1[2]; 51 u32 offset_ns; 52 u32 offset_window_ns; 53 u32 __pad2[2]; 54 u32 drift_ns; 55 u32 drift_window_ns; 56 u32 __pad3[6]; 57 u32 servo_offset_p; 58 u32 servo_offset_i; 59 u32 servo_drift_p; 60 u32 servo_drift_i; 61 u32 status_offset; 62 u32 status_drift; 63 }; 64 65 #define OCP_CTRL_ENABLE BIT(0) 66 #define OCP_CTRL_ADJUST_TIME BIT(1) 67 #define OCP_CTRL_ADJUST_OFFSET BIT(2) 68 #define OCP_CTRL_ADJUST_DRIFT BIT(3) 69 #define OCP_CTRL_ADJUST_SERVO BIT(8) 70 #define OCP_CTRL_READ_TIME_REQ BIT(30) 71 #define OCP_CTRL_READ_TIME_DONE BIT(31) 72 73 #define OCP_STATUS_IN_SYNC BIT(0) 74 #define OCP_STATUS_IN_HOLDOVER BIT(1) 75 76 #define OCP_SELECT_CLK_NONE 0 77 #define OCP_SELECT_CLK_REG 0xfe 78 79 struct tod_reg { 80 u32 ctrl; 81 u32 status; 82 u32 uart_polarity; 83 u32 version; 84 u32 adj_sec; 85 u32 __pad0[3]; 86 u32 uart_baud; 87 u32 __pad1[3]; 88 u32 utc_status; 89 u32 leap; 90 }; 91 92 #define TOD_CTRL_PROTOCOL BIT(28) 93 #define TOD_CTRL_DISABLE_FMT_A BIT(17) 94 #define TOD_CTRL_DISABLE_FMT_B BIT(16) 95 #define TOD_CTRL_ENABLE BIT(0) 96 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0) 97 #define TOD_CTRL_GNSS_SHIFT 24 98 99 #define TOD_STATUS_UTC_MASK GENMASK(7, 0) 100 #define TOD_STATUS_UTC_VALID BIT(8) 101 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12) 102 #define TOD_STATUS_LEAP_VALID BIT(16) 103 104 struct ts_reg { 105 u32 enable; 106 u32 error; 107 u32 polarity; 108 u32 version; 109 u32 __pad0[4]; 110 u32 cable_delay; 111 u32 __pad1[3]; 112 u32 intr; 113 u32 intr_mask; 114 u32 event_count; 115 u32 __pad2[1]; 116 u32 ts_count; 117 u32 time_ns; 118 u32 time_sec; 119 u32 data_width; 120 u32 data; 121 }; 122 123 struct pps_reg { 124 u32 ctrl; 125 u32 status; 126 u32 __pad0[6]; 127 u32 cable_delay; 128 }; 129 130 #define PPS_STATUS_FILTER_ERR BIT(0) 131 #define PPS_STATUS_SUPERV_ERR BIT(1) 132 133 struct img_reg { 134 u32 version; 135 }; 136 137 struct gpio_reg { 138 u32 gpio1; 139 u32 __pad0; 140 u32 gpio2; 141 u32 __pad1; 142 }; 143 144 struct irig_master_reg { 145 u32 ctrl; 146 u32 status; 147 u32 __pad0; 148 u32 version; 149 u32 adj_sec; 150 u32 mode_ctrl; 151 }; 152 153 #define IRIG_M_CTRL_ENABLE BIT(0) 154 155 struct irig_slave_reg { 156 u32 ctrl; 157 u32 status; 158 u32 __pad0; 159 u32 version; 160 u32 adj_sec; 161 u32 mode_ctrl; 162 }; 163 164 #define IRIG_S_CTRL_ENABLE BIT(0) 165 166 struct dcf_master_reg { 167 u32 ctrl; 168 u32 status; 169 u32 __pad0; 170 u32 version; 171 u32 adj_sec; 172 }; 173 174 #define DCF_M_CTRL_ENABLE BIT(0) 175 176 struct dcf_slave_reg { 177 u32 ctrl; 178 u32 status; 179 u32 __pad0; 180 u32 version; 181 u32 adj_sec; 182 }; 183 184 #define DCF_S_CTRL_ENABLE BIT(0) 185 186 struct signal_reg { 187 u32 enable; 188 u32 status; 189 u32 polarity; 190 u32 version; 191 u32 __pad0[4]; 192 u32 cable_delay; 193 u32 __pad1[3]; 194 u32 intr; 195 u32 intr_mask; 196 u32 __pad2[2]; 197 u32 start_ns; 198 u32 start_sec; 199 u32 pulse_ns; 200 u32 pulse_sec; 201 u32 period_ns; 202 u32 period_sec; 203 u32 repeat_count; 204 }; 205 206 struct frequency_reg { 207 u32 ctrl; 208 u32 status; 209 }; 210 211 struct board_config_reg { 212 u32 mro50_serial_activate; 213 }; 214 215 #define FREQ_STATUS_VALID BIT(31) 216 #define FREQ_STATUS_ERROR BIT(30) 217 #define FREQ_STATUS_OVERRUN BIT(29) 218 #define FREQ_STATUS_MASK GENMASK(23, 0) 219 220 struct ptp_ocp_flash_info { 221 const char *name; 222 int pci_offset; 223 int data_size; 224 void *data; 225 }; 226 227 struct ptp_ocp_firmware_header { 228 char magic[4]; 229 __be16 pci_vendor_id; 230 __be16 pci_device_id; 231 __be32 image_size; 232 __be16 hw_revision; 233 __be16 crc; 234 }; 235 236 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC" 237 238 struct ptp_ocp_i2c_info { 239 const char *name; 240 unsigned long fixed_rate; 241 size_t data_size; 242 void *data; 243 }; 244 245 struct ptp_ocp_ext_info { 246 int index; 247 irqreturn_t (*irq_fcn)(int irq, void *priv); 248 int (*enable)(void *priv, u32 req, bool enable); 249 }; 250 251 struct ptp_ocp_ext_src { 252 void __iomem *mem; 253 struct ptp_ocp *bp; 254 struct ptp_ocp_ext_info *info; 255 int irq_vec; 256 }; 257 258 enum ptp_ocp_sma_mode { 259 SMA_MODE_IN, 260 SMA_MODE_OUT, 261 }; 262 263 struct ptp_ocp_sma_connector { 264 enum ptp_ocp_sma_mode mode; 265 bool fixed_fcn; 266 bool fixed_dir; 267 bool disabled; 268 u8 default_fcn; 269 }; 270 271 struct ocp_attr_group { 272 u64 cap; 273 const struct attribute_group *group; 274 }; 275 276 #define OCP_CAP_BASIC BIT(0) 277 #define OCP_CAP_SIGNAL BIT(1) 278 #define OCP_CAP_FREQ BIT(2) 279 280 struct ptp_ocp_signal { 281 ktime_t period; 282 ktime_t pulse; 283 ktime_t phase; 284 ktime_t start; 285 int duty; 286 bool polarity; 287 bool running; 288 }; 289 290 struct ptp_ocp_serial_port { 291 int line; 292 int baud; 293 }; 294 295 #define OCP_BOARD_ID_LEN 13 296 #define OCP_SERIAL_LEN 6 297 298 struct ptp_ocp { 299 struct pci_dev *pdev; 300 struct device dev; 301 spinlock_t lock; 302 struct ocp_reg __iomem *reg; 303 struct tod_reg __iomem *tod; 304 struct pps_reg __iomem *pps_to_ext; 305 struct pps_reg __iomem *pps_to_clk; 306 struct board_config_reg __iomem *board_config; 307 struct gpio_reg __iomem *pps_select; 308 struct gpio_reg __iomem *sma_map1; 309 struct gpio_reg __iomem *sma_map2; 310 struct irig_master_reg __iomem *irig_out; 311 struct irig_slave_reg __iomem *irig_in; 312 struct dcf_master_reg __iomem *dcf_out; 313 struct dcf_slave_reg __iomem *dcf_in; 314 struct tod_reg __iomem *nmea_out; 315 struct frequency_reg __iomem *freq_in[4]; 316 struct ptp_ocp_ext_src *signal_out[4]; 317 struct ptp_ocp_ext_src *pps; 318 struct ptp_ocp_ext_src *ts0; 319 struct ptp_ocp_ext_src *ts1; 320 struct ptp_ocp_ext_src *ts2; 321 struct ptp_ocp_ext_src *ts3; 322 struct ptp_ocp_ext_src *ts4; 323 struct ocp_art_gpio_reg __iomem *art_sma; 324 struct img_reg __iomem *image; 325 struct ptp_clock *ptp; 326 struct ptp_clock_info ptp_info; 327 struct platform_device *i2c_ctrl; 328 struct platform_device *spi_flash; 329 struct clk_hw *i2c_clk; 330 struct timer_list watchdog; 331 const struct attribute_group **attr_group; 332 const struct ptp_ocp_eeprom_map *eeprom_map; 333 struct dentry *debug_root; 334 time64_t gnss_lost; 335 int id; 336 int n_irqs; 337 struct ptp_ocp_serial_port gnss_port; 338 struct ptp_ocp_serial_port gnss2_port; 339 struct ptp_ocp_serial_port mac_port; /* miniature atomic clock */ 340 struct ptp_ocp_serial_port nmea_port; 341 bool fw_loader; 342 u8 fw_tag; 343 u16 fw_version; 344 u8 board_id[OCP_BOARD_ID_LEN]; 345 u8 serial[OCP_SERIAL_LEN]; 346 bool has_eeprom_data; 347 u32 pps_req_map; 348 int flash_start; 349 u32 utc_tai_offset; 350 u32 ts_window_adjust; 351 u64 fw_cap; 352 struct ptp_ocp_signal signal[4]; 353 struct ptp_ocp_sma_connector sma[4]; 354 const struct ocp_sma_op *sma_op; 355 }; 356 357 #define OCP_REQ_TIMESTAMP BIT(0) 358 #define OCP_REQ_PPS BIT(1) 359 360 struct ocp_resource { 361 unsigned long offset; 362 int size; 363 int irq_vec; 364 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r); 365 void *extra; 366 unsigned long bp_offset; 367 const char * const name; 368 }; 369 370 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r); 371 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r); 372 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r); 373 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r); 374 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r); 375 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r); 376 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv); 377 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv); 378 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable); 379 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen, 380 struct ptp_perout_request *req); 381 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable); 382 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr); 383 384 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r); 385 386 static const struct ocp_attr_group fb_timecard_groups[]; 387 388 static const struct ocp_attr_group art_timecard_groups[]; 389 390 struct ptp_ocp_eeprom_map { 391 u16 off; 392 u16 len; 393 u32 bp_offset; 394 const void * const tag; 395 }; 396 397 #define EEPROM_ENTRY(addr, member) \ 398 .off = addr, \ 399 .len = sizeof_field(struct ptp_ocp, member), \ 400 .bp_offset = offsetof(struct ptp_ocp, member) 401 402 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \ 403 (void *)((uintptr_t)(bp) + (map)->bp_offset); \ 404 }) 405 406 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = { 407 { EEPROM_ENTRY(0x43, board_id) }, 408 { EEPROM_ENTRY(0x00, serial), .tag = "mac" }, 409 { } 410 }; 411 412 static struct ptp_ocp_eeprom_map art_eeprom_map[] = { 413 { EEPROM_ENTRY(0x200 + 0x43, board_id) }, 414 { EEPROM_ENTRY(0x200 + 0x63, serial) }, 415 { } 416 }; 417 418 #define bp_assign_entry(bp, res, val) ({ \ 419 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \ 420 *(typeof(val) *)addr = val; \ 421 }) 422 423 #define OCP_RES_LOCATION(member) \ 424 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member) 425 426 #define OCP_MEM_RESOURCE(member) \ 427 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem 428 429 #define OCP_SERIAL_RESOURCE(member) \ 430 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial 431 432 #define OCP_I2C_RESOURCE(member) \ 433 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c 434 435 #define OCP_SPI_RESOURCE(member) \ 436 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi 437 438 #define OCP_EXT_RESOURCE(member) \ 439 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext 440 441 /* This is the MSI vector mapping used. 442 * 0: PPS (TS5) 443 * 1: TS0 444 * 2: TS1 445 * 3: GNSS1 446 * 4: GNSS2 447 * 5: MAC 448 * 6: TS2 449 * 7: I2C controller 450 * 8: HWICAP (notused) 451 * 9: SPI Flash 452 * 10: NMEA 453 * 11: Signal Generator 1 454 * 12: Signal Generator 2 455 * 13: Signal Generator 3 456 * 14: Signal Generator 4 457 * 15: TS3 458 * 16: TS4 459 -- 460 * 8: Orolia TS1 461 * 10: Orolia TS2 462 * 11: Orolia TS0 (GNSS) 463 * 12: Orolia PPS 464 * 14: Orolia TS3 465 * 15: Orolia TS4 466 */ 467 468 static struct ocp_resource ocp_fb_resource[] = { 469 { 470 OCP_MEM_RESOURCE(reg), 471 .offset = 0x01000000, .size = 0x10000, 472 }, 473 { 474 OCP_EXT_RESOURCE(ts0), 475 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1, 476 .extra = &(struct ptp_ocp_ext_info) { 477 .index = 0, 478 .irq_fcn = ptp_ocp_ts_irq, 479 .enable = ptp_ocp_ts_enable, 480 }, 481 }, 482 { 483 OCP_EXT_RESOURCE(ts1), 484 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2, 485 .extra = &(struct ptp_ocp_ext_info) { 486 .index = 1, 487 .irq_fcn = ptp_ocp_ts_irq, 488 .enable = ptp_ocp_ts_enable, 489 }, 490 }, 491 { 492 OCP_EXT_RESOURCE(ts2), 493 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6, 494 .extra = &(struct ptp_ocp_ext_info) { 495 .index = 2, 496 .irq_fcn = ptp_ocp_ts_irq, 497 .enable = ptp_ocp_ts_enable, 498 }, 499 }, 500 { 501 OCP_EXT_RESOURCE(ts3), 502 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15, 503 .extra = &(struct ptp_ocp_ext_info) { 504 .index = 3, 505 .irq_fcn = ptp_ocp_ts_irq, 506 .enable = ptp_ocp_ts_enable, 507 }, 508 }, 509 { 510 OCP_EXT_RESOURCE(ts4), 511 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16, 512 .extra = &(struct ptp_ocp_ext_info) { 513 .index = 4, 514 .irq_fcn = ptp_ocp_ts_irq, 515 .enable = ptp_ocp_ts_enable, 516 }, 517 }, 518 /* Timestamp for PHC and/or PPS generator */ 519 { 520 OCP_EXT_RESOURCE(pps), 521 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0, 522 .extra = &(struct ptp_ocp_ext_info) { 523 .index = 5, 524 .irq_fcn = ptp_ocp_ts_irq, 525 .enable = ptp_ocp_ts_enable, 526 }, 527 }, 528 { 529 OCP_EXT_RESOURCE(signal_out[0]), 530 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11, 531 .extra = &(struct ptp_ocp_ext_info) { 532 .index = 1, 533 .irq_fcn = ptp_ocp_signal_irq, 534 .enable = ptp_ocp_signal_enable, 535 }, 536 }, 537 { 538 OCP_EXT_RESOURCE(signal_out[1]), 539 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12, 540 .extra = &(struct ptp_ocp_ext_info) { 541 .index = 2, 542 .irq_fcn = ptp_ocp_signal_irq, 543 .enable = ptp_ocp_signal_enable, 544 }, 545 }, 546 { 547 OCP_EXT_RESOURCE(signal_out[2]), 548 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13, 549 .extra = &(struct ptp_ocp_ext_info) { 550 .index = 3, 551 .irq_fcn = ptp_ocp_signal_irq, 552 .enable = ptp_ocp_signal_enable, 553 }, 554 }, 555 { 556 OCP_EXT_RESOURCE(signal_out[3]), 557 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14, 558 .extra = &(struct ptp_ocp_ext_info) { 559 .index = 4, 560 .irq_fcn = ptp_ocp_signal_irq, 561 .enable = ptp_ocp_signal_enable, 562 }, 563 }, 564 { 565 OCP_MEM_RESOURCE(pps_to_ext), 566 .offset = 0x01030000, .size = 0x10000, 567 }, 568 { 569 OCP_MEM_RESOURCE(pps_to_clk), 570 .offset = 0x01040000, .size = 0x10000, 571 }, 572 { 573 OCP_MEM_RESOURCE(tod), 574 .offset = 0x01050000, .size = 0x10000, 575 }, 576 { 577 OCP_MEM_RESOURCE(irig_in), 578 .offset = 0x01070000, .size = 0x10000, 579 }, 580 { 581 OCP_MEM_RESOURCE(irig_out), 582 .offset = 0x01080000, .size = 0x10000, 583 }, 584 { 585 OCP_MEM_RESOURCE(dcf_in), 586 .offset = 0x01090000, .size = 0x10000, 587 }, 588 { 589 OCP_MEM_RESOURCE(dcf_out), 590 .offset = 0x010A0000, .size = 0x10000, 591 }, 592 { 593 OCP_MEM_RESOURCE(nmea_out), 594 .offset = 0x010B0000, .size = 0x10000, 595 }, 596 { 597 OCP_MEM_RESOURCE(image), 598 .offset = 0x00020000, .size = 0x1000, 599 }, 600 { 601 OCP_MEM_RESOURCE(pps_select), 602 .offset = 0x00130000, .size = 0x1000, 603 }, 604 { 605 OCP_MEM_RESOURCE(sma_map1), 606 .offset = 0x00140000, .size = 0x1000, 607 }, 608 { 609 OCP_MEM_RESOURCE(sma_map2), 610 .offset = 0x00220000, .size = 0x1000, 611 }, 612 { 613 OCP_I2C_RESOURCE(i2c_ctrl), 614 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7, 615 .extra = &(struct ptp_ocp_i2c_info) { 616 .name = "xiic-i2c", 617 .fixed_rate = 50000000, 618 .data_size = sizeof(struct xiic_i2c_platform_data), 619 .data = &(struct xiic_i2c_platform_data) { 620 .num_devices = 2, 621 .devices = (struct i2c_board_info[]) { 622 { I2C_BOARD_INFO("24c02", 0x50) }, 623 { I2C_BOARD_INFO("24mac402", 0x58), 624 .platform_data = "mac" }, 625 }, 626 }, 627 }, 628 }, 629 { 630 OCP_SERIAL_RESOURCE(gnss_port), 631 .offset = 0x00160000 + 0x1000, .irq_vec = 3, 632 .extra = &(struct ptp_ocp_serial_port) { 633 .baud = 115200, 634 }, 635 }, 636 { 637 OCP_SERIAL_RESOURCE(gnss2_port), 638 .offset = 0x00170000 + 0x1000, .irq_vec = 4, 639 .extra = &(struct ptp_ocp_serial_port) { 640 .baud = 115200, 641 }, 642 }, 643 { 644 OCP_SERIAL_RESOURCE(mac_port), 645 .offset = 0x00180000 + 0x1000, .irq_vec = 5, 646 .extra = &(struct ptp_ocp_serial_port) { 647 .baud = 57600, 648 }, 649 }, 650 { 651 OCP_SERIAL_RESOURCE(nmea_port), 652 .offset = 0x00190000 + 0x1000, .irq_vec = 10, 653 }, 654 { 655 OCP_SPI_RESOURCE(spi_flash), 656 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9, 657 .extra = &(struct ptp_ocp_flash_info) { 658 .name = "xilinx_spi", .pci_offset = 0, 659 .data_size = sizeof(struct xspi_platform_data), 660 .data = &(struct xspi_platform_data) { 661 .num_chipselect = 1, 662 .bits_per_word = 8, 663 .num_devices = 1, 664 .devices = &(struct spi_board_info) { 665 .modalias = "spi-nor", 666 }, 667 }, 668 }, 669 }, 670 { 671 OCP_MEM_RESOURCE(freq_in[0]), 672 .offset = 0x01200000, .size = 0x10000, 673 }, 674 { 675 OCP_MEM_RESOURCE(freq_in[1]), 676 .offset = 0x01210000, .size = 0x10000, 677 }, 678 { 679 OCP_MEM_RESOURCE(freq_in[2]), 680 .offset = 0x01220000, .size = 0x10000, 681 }, 682 { 683 OCP_MEM_RESOURCE(freq_in[3]), 684 .offset = 0x01230000, .size = 0x10000, 685 }, 686 { 687 .setup = ptp_ocp_fb_board_init, 688 }, 689 { } 690 }; 691 692 #define OCP_ART_CONFIG_SIZE 144 693 #define OCP_ART_TEMP_TABLE_SIZE 368 694 695 struct ocp_art_gpio_reg { 696 struct { 697 u32 gpio; 698 u32 __pad[3]; 699 } map[4]; 700 }; 701 702 static struct ocp_resource ocp_art_resource[] = { 703 { 704 OCP_MEM_RESOURCE(reg), 705 .offset = 0x01000000, .size = 0x10000, 706 }, 707 { 708 OCP_SERIAL_RESOURCE(gnss_port), 709 .offset = 0x00160000 + 0x1000, .irq_vec = 3, 710 .extra = &(struct ptp_ocp_serial_port) { 711 .baud = 115200, 712 }, 713 }, 714 { 715 OCP_MEM_RESOURCE(art_sma), 716 .offset = 0x003C0000, .size = 0x1000, 717 }, 718 /* Timestamp associated with GNSS1 receiver PPS */ 719 { 720 OCP_EXT_RESOURCE(ts0), 721 .offset = 0x360000, .size = 0x20, .irq_vec = 12, 722 .extra = &(struct ptp_ocp_ext_info) { 723 .index = 0, 724 .irq_fcn = ptp_ocp_ts_irq, 725 .enable = ptp_ocp_ts_enable, 726 }, 727 }, 728 { 729 OCP_EXT_RESOURCE(ts1), 730 .offset = 0x380000, .size = 0x20, .irq_vec = 8, 731 .extra = &(struct ptp_ocp_ext_info) { 732 .index = 1, 733 .irq_fcn = ptp_ocp_ts_irq, 734 .enable = ptp_ocp_ts_enable, 735 }, 736 }, 737 { 738 OCP_EXT_RESOURCE(ts2), 739 .offset = 0x390000, .size = 0x20, .irq_vec = 10, 740 .extra = &(struct ptp_ocp_ext_info) { 741 .index = 2, 742 .irq_fcn = ptp_ocp_ts_irq, 743 .enable = ptp_ocp_ts_enable, 744 }, 745 }, 746 { 747 OCP_EXT_RESOURCE(ts3), 748 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14, 749 .extra = &(struct ptp_ocp_ext_info) { 750 .index = 3, 751 .irq_fcn = ptp_ocp_ts_irq, 752 .enable = ptp_ocp_ts_enable, 753 }, 754 }, 755 { 756 OCP_EXT_RESOURCE(ts4), 757 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15, 758 .extra = &(struct ptp_ocp_ext_info) { 759 .index = 4, 760 .irq_fcn = ptp_ocp_ts_irq, 761 .enable = ptp_ocp_ts_enable, 762 }, 763 }, 764 /* Timestamp associated with Internal PPS of the card */ 765 { 766 OCP_EXT_RESOURCE(pps), 767 .offset = 0x00330000, .size = 0x20, .irq_vec = 11, 768 .extra = &(struct ptp_ocp_ext_info) { 769 .index = 5, 770 .irq_fcn = ptp_ocp_ts_irq, 771 .enable = ptp_ocp_ts_enable, 772 }, 773 }, 774 { 775 OCP_SPI_RESOURCE(spi_flash), 776 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9, 777 .extra = &(struct ptp_ocp_flash_info) { 778 .name = "spi_altera", .pci_offset = 0, 779 .data_size = sizeof(struct altera_spi_platform_data), 780 .data = &(struct altera_spi_platform_data) { 781 .num_chipselect = 1, 782 .num_devices = 1, 783 .devices = &(struct spi_board_info) { 784 .modalias = "spi-nor", 785 }, 786 }, 787 }, 788 }, 789 { 790 OCP_I2C_RESOURCE(i2c_ctrl), 791 .offset = 0x350000, .size = 0x100, .irq_vec = 4, 792 .extra = &(struct ptp_ocp_i2c_info) { 793 .name = "ocores-i2c", 794 .fixed_rate = 400000, 795 .data_size = sizeof(struct ocores_i2c_platform_data), 796 .data = &(struct ocores_i2c_platform_data) { 797 .clock_khz = 125000, 798 .bus_khz = 400, 799 .num_devices = 1, 800 .devices = &(struct i2c_board_info) { 801 I2C_BOARD_INFO("24c08", 0x50), 802 }, 803 }, 804 }, 805 }, 806 { 807 OCP_SERIAL_RESOURCE(mac_port), 808 .offset = 0x00190000, .irq_vec = 7, 809 .extra = &(struct ptp_ocp_serial_port) { 810 .baud = 9600, 811 }, 812 }, 813 { 814 OCP_MEM_RESOURCE(board_config), 815 .offset = 0x210000, .size = 0x1000, 816 }, 817 { 818 .setup = ptp_ocp_art_board_init, 819 }, 820 { } 821 }; 822 823 static const struct pci_device_id ptp_ocp_pcidev_id[] = { 824 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) }, 825 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) }, 826 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) }, 827 { } 828 }; 829 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id); 830 831 static DEFINE_MUTEX(ptp_ocp_lock); 832 static DEFINE_IDR(ptp_ocp_idr); 833 834 struct ocp_selector { 835 const char *name; 836 int value; 837 }; 838 839 static const struct ocp_selector ptp_ocp_clock[] = { 840 { .name = "NONE", .value = 0 }, 841 { .name = "TOD", .value = 1 }, 842 { .name = "IRIG", .value = 2 }, 843 { .name = "PPS", .value = 3 }, 844 { .name = "PTP", .value = 4 }, 845 { .name = "RTC", .value = 5 }, 846 { .name = "DCF", .value = 6 }, 847 { .name = "REGS", .value = 0xfe }, 848 { .name = "EXT", .value = 0xff }, 849 { } 850 }; 851 852 #define SMA_DISABLE BIT(16) 853 #define SMA_ENABLE BIT(15) 854 #define SMA_SELECT_MASK GENMASK(14, 0) 855 856 static const struct ocp_selector ptp_ocp_sma_in[] = { 857 { .name = "10Mhz", .value = 0x0000 }, 858 { .name = "PPS1", .value = 0x0001 }, 859 { .name = "PPS2", .value = 0x0002 }, 860 { .name = "TS1", .value = 0x0004 }, 861 { .name = "TS2", .value = 0x0008 }, 862 { .name = "IRIG", .value = 0x0010 }, 863 { .name = "DCF", .value = 0x0020 }, 864 { .name = "TS3", .value = 0x0040 }, 865 { .name = "TS4", .value = 0x0080 }, 866 { .name = "FREQ1", .value = 0x0100 }, 867 { .name = "FREQ2", .value = 0x0200 }, 868 { .name = "FREQ3", .value = 0x0400 }, 869 { .name = "FREQ4", .value = 0x0800 }, 870 { .name = "None", .value = SMA_DISABLE }, 871 { } 872 }; 873 874 static const struct ocp_selector ptp_ocp_sma_out[] = { 875 { .name = "10Mhz", .value = 0x0000 }, 876 { .name = "PHC", .value = 0x0001 }, 877 { .name = "MAC", .value = 0x0002 }, 878 { .name = "GNSS1", .value = 0x0004 }, 879 { .name = "GNSS2", .value = 0x0008 }, 880 { .name = "IRIG", .value = 0x0010 }, 881 { .name = "DCF", .value = 0x0020 }, 882 { .name = "GEN1", .value = 0x0040 }, 883 { .name = "GEN2", .value = 0x0080 }, 884 { .name = "GEN3", .value = 0x0100 }, 885 { .name = "GEN4", .value = 0x0200 }, 886 { .name = "GND", .value = 0x2000 }, 887 { .name = "VCC", .value = 0x4000 }, 888 { } 889 }; 890 891 static const struct ocp_selector ptp_ocp_art_sma_in[] = { 892 { .name = "PPS1", .value = 0x0001 }, 893 { .name = "10Mhz", .value = 0x0008 }, 894 { } 895 }; 896 897 static const struct ocp_selector ptp_ocp_art_sma_out[] = { 898 { .name = "PHC", .value = 0x0002 }, 899 { .name = "GNSS", .value = 0x0004 }, 900 { .name = "10Mhz", .value = 0x0010 }, 901 { } 902 }; 903 904 struct ocp_sma_op { 905 const struct ocp_selector *tbl[2]; 906 void (*init)(struct ptp_ocp *bp); 907 u32 (*get)(struct ptp_ocp *bp, int sma_nr); 908 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val); 909 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val); 910 }; 911 912 static void 913 ptp_ocp_sma_init(struct ptp_ocp *bp) 914 { 915 return bp->sma_op->init(bp); 916 } 917 918 static u32 919 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr) 920 { 921 return bp->sma_op->get(bp, sma_nr); 922 } 923 924 static int 925 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val) 926 { 927 return bp->sma_op->set_inputs(bp, sma_nr, val); 928 } 929 930 static int 931 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val) 932 { 933 return bp->sma_op->set_output(bp, sma_nr, val); 934 } 935 936 static const char * 937 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val) 938 { 939 int i; 940 941 for (i = 0; tbl[i].name; i++) 942 if (tbl[i].value == val) 943 return tbl[i].name; 944 return NULL; 945 } 946 947 static int 948 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name) 949 { 950 const char *select; 951 int i; 952 953 for (i = 0; tbl[i].name; i++) { 954 select = tbl[i].name; 955 if (!strncasecmp(name, select, strlen(select))) 956 return tbl[i].value; 957 } 958 return -EINVAL; 959 } 960 961 static ssize_t 962 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf) 963 { 964 ssize_t count; 965 int i; 966 967 count = 0; 968 for (i = 0; tbl[i].name; i++) 969 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name); 970 if (count) 971 count--; 972 count += sysfs_emit_at(buf, count, "\n"); 973 return count; 974 } 975 976 static int 977 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts, 978 struct ptp_system_timestamp *sts) 979 { 980 u32 ctrl, time_sec, time_ns; 981 int i; 982 983 ptp_read_system_prets(sts); 984 985 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE; 986 iowrite32(ctrl, &bp->reg->ctrl); 987 988 for (i = 0; i < 100; i++) { 989 ctrl = ioread32(&bp->reg->ctrl); 990 if (ctrl & OCP_CTRL_READ_TIME_DONE) 991 break; 992 } 993 ptp_read_system_postts(sts); 994 995 if (sts && bp->ts_window_adjust) { 996 s64 ns = timespec64_to_ns(&sts->post_ts); 997 998 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust); 999 } 1000 1001 time_ns = ioread32(&bp->reg->time_ns); 1002 time_sec = ioread32(&bp->reg->time_sec); 1003 1004 ts->tv_sec = time_sec; 1005 ts->tv_nsec = time_ns; 1006 1007 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT; 1008 } 1009 1010 static int 1011 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts, 1012 struct ptp_system_timestamp *sts) 1013 { 1014 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 1015 unsigned long flags; 1016 int err; 1017 1018 spin_lock_irqsave(&bp->lock, flags); 1019 err = __ptp_ocp_gettime_locked(bp, ts, sts); 1020 spin_unlock_irqrestore(&bp->lock, flags); 1021 1022 return err; 1023 } 1024 1025 static void 1026 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts) 1027 { 1028 u32 ctrl, time_sec, time_ns; 1029 u32 select; 1030 1031 time_ns = ts->tv_nsec; 1032 time_sec = ts->tv_sec; 1033 1034 select = ioread32(&bp->reg->select); 1035 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 1036 1037 iowrite32(time_ns, &bp->reg->adjust_ns); 1038 iowrite32(time_sec, &bp->reg->adjust_sec); 1039 1040 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE; 1041 iowrite32(ctrl, &bp->reg->ctrl); 1042 1043 /* restore clock selection */ 1044 iowrite32(select >> 16, &bp->reg->select); 1045 } 1046 1047 static int 1048 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts) 1049 { 1050 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 1051 unsigned long flags; 1052 1053 spin_lock_irqsave(&bp->lock, flags); 1054 __ptp_ocp_settime_locked(bp, ts); 1055 spin_unlock_irqrestore(&bp->lock, flags); 1056 1057 return 0; 1058 } 1059 1060 static void 1061 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val) 1062 { 1063 u32 select, ctrl; 1064 1065 select = ioread32(&bp->reg->select); 1066 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 1067 1068 iowrite32(adj_val, &bp->reg->offset_ns); 1069 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns); 1070 1071 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE; 1072 iowrite32(ctrl, &bp->reg->ctrl); 1073 1074 /* restore clock selection */ 1075 iowrite32(select >> 16, &bp->reg->select); 1076 } 1077 1078 static void 1079 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns) 1080 { 1081 struct timespec64 ts; 1082 unsigned long flags; 1083 int err; 1084 1085 spin_lock_irqsave(&bp->lock, flags); 1086 err = __ptp_ocp_gettime_locked(bp, &ts, NULL); 1087 if (likely(!err)) { 1088 set_normalized_timespec64(&ts, ts.tv_sec, 1089 ts.tv_nsec + delta_ns); 1090 __ptp_ocp_settime_locked(bp, &ts); 1091 } 1092 spin_unlock_irqrestore(&bp->lock, flags); 1093 } 1094 1095 static int 1096 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns) 1097 { 1098 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 1099 unsigned long flags; 1100 u32 adj_ns, sign; 1101 1102 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) { 1103 ptp_ocp_adjtime_coarse(bp, delta_ns); 1104 return 0; 1105 } 1106 1107 sign = delta_ns < 0 ? BIT(31) : 0; 1108 adj_ns = sign ? -delta_ns : delta_ns; 1109 1110 spin_lock_irqsave(&bp->lock, flags); 1111 __ptp_ocp_adjtime_locked(bp, sign | adj_ns); 1112 spin_unlock_irqrestore(&bp->lock, flags); 1113 1114 return 0; 1115 } 1116 1117 static int 1118 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm) 1119 { 1120 if (scaled_ppm == 0) 1121 return 0; 1122 1123 return -EOPNOTSUPP; 1124 } 1125 1126 static int 1127 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns) 1128 { 1129 return -EOPNOTSUPP; 1130 } 1131 1132 static int 1133 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq, 1134 int on) 1135 { 1136 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 1137 struct ptp_ocp_ext_src *ext = NULL; 1138 u32 req; 1139 int err; 1140 1141 switch (rq->type) { 1142 case PTP_CLK_REQ_EXTTS: 1143 req = OCP_REQ_TIMESTAMP; 1144 switch (rq->extts.index) { 1145 case 0: 1146 ext = bp->ts0; 1147 break; 1148 case 1: 1149 ext = bp->ts1; 1150 break; 1151 case 2: 1152 ext = bp->ts2; 1153 break; 1154 case 3: 1155 ext = bp->ts3; 1156 break; 1157 case 4: 1158 ext = bp->ts4; 1159 break; 1160 case 5: 1161 ext = bp->pps; 1162 break; 1163 } 1164 break; 1165 case PTP_CLK_REQ_PPS: 1166 req = OCP_REQ_PPS; 1167 ext = bp->pps; 1168 break; 1169 case PTP_CLK_REQ_PEROUT: 1170 switch (rq->perout.index) { 1171 case 0: 1172 /* This is a request for 1PPS on an output SMA. 1173 * Allow, but assume manual configuration. 1174 */ 1175 if (on && (rq->perout.period.sec != 1 || 1176 rq->perout.period.nsec != 0)) 1177 return -EINVAL; 1178 return 0; 1179 case 1: 1180 case 2: 1181 case 3: 1182 case 4: 1183 req = rq->perout.index - 1; 1184 ext = bp->signal_out[req]; 1185 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout); 1186 if (err) 1187 return err; 1188 break; 1189 } 1190 break; 1191 default: 1192 return -EOPNOTSUPP; 1193 } 1194 1195 err = -ENXIO; 1196 if (ext) 1197 err = ext->info->enable(ext, req, on); 1198 1199 return err; 1200 } 1201 1202 static int 1203 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin, 1204 enum ptp_pin_function func, unsigned chan) 1205 { 1206 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 1207 char buf[16]; 1208 1209 switch (func) { 1210 case PTP_PF_NONE: 1211 snprintf(buf, sizeof(buf), "IN: None"); 1212 break; 1213 case PTP_PF_EXTTS: 1214 /* Allow timestamps, but require sysfs configuration. */ 1215 return 0; 1216 case PTP_PF_PEROUT: 1217 /* channel 0 is 1PPS from PHC. 1218 * channels 1..4 are the frequency generators. 1219 */ 1220 if (chan) 1221 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan); 1222 else 1223 snprintf(buf, sizeof(buf), "OUT: PHC"); 1224 break; 1225 default: 1226 return -EOPNOTSUPP; 1227 } 1228 1229 return ptp_ocp_sma_store(bp, buf, pin + 1); 1230 } 1231 1232 static const struct ptp_clock_info ptp_ocp_clock_info = { 1233 .owner = THIS_MODULE, 1234 .name = KBUILD_MODNAME, 1235 .max_adj = 100000000, 1236 .gettimex64 = ptp_ocp_gettimex, 1237 .settime64 = ptp_ocp_settime, 1238 .adjtime = ptp_ocp_adjtime, 1239 .adjfine = ptp_ocp_null_adjfine, 1240 .adjphase = ptp_ocp_null_adjphase, 1241 .enable = ptp_ocp_enable, 1242 .verify = ptp_ocp_verify, 1243 .pps = true, 1244 .n_ext_ts = 6, 1245 .n_per_out = 5, 1246 }; 1247 1248 static void 1249 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp) 1250 { 1251 u32 ctrl, select; 1252 1253 select = ioread32(&bp->reg->select); 1254 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 1255 1256 iowrite32(0, &bp->reg->drift_ns); 1257 1258 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE; 1259 iowrite32(ctrl, &bp->reg->ctrl); 1260 1261 /* restore clock selection */ 1262 iowrite32(select >> 16, &bp->reg->select); 1263 } 1264 1265 static void 1266 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val) 1267 { 1268 unsigned long flags; 1269 1270 spin_lock_irqsave(&bp->lock, flags); 1271 1272 bp->utc_tai_offset = val; 1273 1274 if (bp->irig_out) 1275 iowrite32(val, &bp->irig_out->adj_sec); 1276 if (bp->dcf_out) 1277 iowrite32(val, &bp->dcf_out->adj_sec); 1278 if (bp->nmea_out) 1279 iowrite32(val, &bp->nmea_out->adj_sec); 1280 1281 spin_unlock_irqrestore(&bp->lock, flags); 1282 } 1283 1284 static void 1285 ptp_ocp_watchdog(struct timer_list *t) 1286 { 1287 struct ptp_ocp *bp = from_timer(bp, t, watchdog); 1288 unsigned long flags; 1289 u32 status, utc_offset; 1290 1291 status = ioread32(&bp->pps_to_clk->status); 1292 1293 if (status & PPS_STATUS_SUPERV_ERR) { 1294 iowrite32(status, &bp->pps_to_clk->status); 1295 if (!bp->gnss_lost) { 1296 spin_lock_irqsave(&bp->lock, flags); 1297 __ptp_ocp_clear_drift_locked(bp); 1298 spin_unlock_irqrestore(&bp->lock, flags); 1299 bp->gnss_lost = ktime_get_real_seconds(); 1300 } 1301 1302 } else if (bp->gnss_lost) { 1303 bp->gnss_lost = 0; 1304 } 1305 1306 /* if GNSS provides correct data we can rely on 1307 * it to get leap second information 1308 */ 1309 if (bp->tod) { 1310 status = ioread32(&bp->tod->utc_status); 1311 utc_offset = status & TOD_STATUS_UTC_MASK; 1312 if (status & TOD_STATUS_UTC_VALID && 1313 utc_offset != bp->utc_tai_offset) 1314 ptp_ocp_utc_distribute(bp, utc_offset); 1315 } 1316 1317 mod_timer(&bp->watchdog, jiffies + HZ); 1318 } 1319 1320 static void 1321 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp) 1322 { 1323 ktime_t start, end; 1324 ktime_t delay; 1325 u32 ctrl; 1326 1327 ctrl = ioread32(&bp->reg->ctrl); 1328 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE; 1329 1330 iowrite32(ctrl, &bp->reg->ctrl); 1331 1332 start = ktime_get_ns(); 1333 1334 ctrl = ioread32(&bp->reg->ctrl); 1335 1336 end = ktime_get_ns(); 1337 1338 delay = end - start; 1339 bp->ts_window_adjust = (delay >> 5) * 3; 1340 } 1341 1342 static int 1343 ptp_ocp_init_clock(struct ptp_ocp *bp) 1344 { 1345 struct timespec64 ts; 1346 bool sync; 1347 u32 ctrl; 1348 1349 ctrl = OCP_CTRL_ENABLE; 1350 iowrite32(ctrl, &bp->reg->ctrl); 1351 1352 /* NO DRIFT Correction */ 1353 /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */ 1354 iowrite32(0x2000, &bp->reg->servo_offset_p); 1355 iowrite32(0x1000, &bp->reg->servo_offset_i); 1356 iowrite32(0, &bp->reg->servo_drift_p); 1357 iowrite32(0, &bp->reg->servo_drift_i); 1358 1359 /* latch servo values */ 1360 ctrl |= OCP_CTRL_ADJUST_SERVO; 1361 iowrite32(ctrl, &bp->reg->ctrl); 1362 1363 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) { 1364 dev_err(&bp->pdev->dev, "clock not enabled\n"); 1365 return -ENODEV; 1366 } 1367 1368 ptp_ocp_estimate_pci_timing(bp); 1369 1370 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC; 1371 if (!sync) { 1372 ktime_get_clocktai_ts64(&ts); 1373 ptp_ocp_settime(&bp->ptp_info, &ts); 1374 } 1375 1376 /* If there is a clock supervisor, then enable the watchdog */ 1377 if (bp->pps_to_clk) { 1378 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0); 1379 mod_timer(&bp->watchdog, jiffies + HZ); 1380 } 1381 1382 return 0; 1383 } 1384 1385 static void 1386 ptp_ocp_tod_init(struct ptp_ocp *bp) 1387 { 1388 u32 ctrl, reg; 1389 1390 ctrl = ioread32(&bp->tod->ctrl); 1391 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE; 1392 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B); 1393 iowrite32(ctrl, &bp->tod->ctrl); 1394 1395 reg = ioread32(&bp->tod->utc_status); 1396 if (reg & TOD_STATUS_UTC_VALID) 1397 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK); 1398 } 1399 1400 static const char * 1401 ptp_ocp_tod_proto_name(const int idx) 1402 { 1403 static const char * const proto_name[] = { 1404 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none", 1405 "UBX", "UBX_UTC", "UBX_LS", "UBX_none" 1406 }; 1407 return proto_name[idx]; 1408 } 1409 1410 static const char * 1411 ptp_ocp_tod_gnss_name(int idx) 1412 { 1413 static const char * const gnss_name[] = { 1414 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU", 1415 "Unknown" 1416 }; 1417 if (idx >= ARRAY_SIZE(gnss_name)) 1418 idx = ARRAY_SIZE(gnss_name) - 1; 1419 return gnss_name[idx]; 1420 } 1421 1422 struct ptp_ocp_nvmem_match_info { 1423 struct ptp_ocp *bp; 1424 const void * const tag; 1425 }; 1426 1427 static int 1428 ptp_ocp_nvmem_match(struct device *dev, const void *data) 1429 { 1430 const struct ptp_ocp_nvmem_match_info *info = data; 1431 1432 dev = dev->parent; 1433 if (!i2c_verify_client(dev) || info->tag != dev->platform_data) 1434 return 0; 1435 1436 while ((dev = dev->parent)) 1437 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME)) 1438 return info->bp == dev_get_drvdata(dev); 1439 return 0; 1440 } 1441 1442 static inline struct nvmem_device * 1443 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag) 1444 { 1445 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag }; 1446 1447 return nvmem_device_find(&info, ptp_ocp_nvmem_match); 1448 } 1449 1450 static inline void 1451 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp) 1452 { 1453 if (!IS_ERR_OR_NULL(*nvmemp)) 1454 nvmem_device_put(*nvmemp); 1455 *nvmemp = NULL; 1456 } 1457 1458 static void 1459 ptp_ocp_read_eeprom(struct ptp_ocp *bp) 1460 { 1461 const struct ptp_ocp_eeprom_map *map; 1462 struct nvmem_device *nvmem; 1463 const void *tag; 1464 int ret; 1465 1466 if (!bp->i2c_ctrl) 1467 return; 1468 1469 tag = NULL; 1470 nvmem = NULL; 1471 1472 for (map = bp->eeprom_map; map->len; map++) { 1473 if (map->tag != tag) { 1474 tag = map->tag; 1475 ptp_ocp_nvmem_device_put(&nvmem); 1476 } 1477 if (!nvmem) { 1478 nvmem = ptp_ocp_nvmem_device_get(bp, tag); 1479 if (IS_ERR(nvmem)) { 1480 ret = PTR_ERR(nvmem); 1481 goto fail; 1482 } 1483 } 1484 ret = nvmem_device_read(nvmem, map->off, map->len, 1485 BP_MAP_ENTRY_ADDR(bp, map)); 1486 if (ret != map->len) 1487 goto fail; 1488 } 1489 1490 bp->has_eeprom_data = true; 1491 1492 out: 1493 ptp_ocp_nvmem_device_put(&nvmem); 1494 return; 1495 1496 fail: 1497 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret); 1498 goto out; 1499 } 1500 1501 static struct device * 1502 ptp_ocp_find_flash(struct ptp_ocp *bp) 1503 { 1504 struct device *dev, *last; 1505 1506 last = NULL; 1507 dev = &bp->spi_flash->dev; 1508 1509 while ((dev = device_find_any_child(dev))) { 1510 if (!strcmp("mtd", dev_bus_name(dev))) 1511 break; 1512 put_device(last); 1513 last = dev; 1514 } 1515 put_device(last); 1516 1517 return dev; 1518 } 1519 1520 static int 1521 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw, 1522 const u8 **data, size_t *size) 1523 { 1524 struct ptp_ocp *bp = devlink_priv(devlink); 1525 const struct ptp_ocp_firmware_header *hdr; 1526 size_t offset, length; 1527 u16 crc; 1528 1529 hdr = (const struct ptp_ocp_firmware_header *)fw->data; 1530 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) { 1531 devlink_flash_update_status_notify(devlink, 1532 "No firmware header found, cancel firmware upgrade", 1533 NULL, 0, 0); 1534 return -EINVAL; 1535 } 1536 1537 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor || 1538 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) { 1539 devlink_flash_update_status_notify(devlink, 1540 "Firmware image compatibility check failed", 1541 NULL, 0, 0); 1542 return -EINVAL; 1543 } 1544 1545 offset = sizeof(*hdr); 1546 length = be32_to_cpu(hdr->image_size); 1547 if (length != (fw->size - offset)) { 1548 devlink_flash_update_status_notify(devlink, 1549 "Firmware image size check failed", 1550 NULL, 0, 0); 1551 return -EINVAL; 1552 } 1553 1554 crc = crc16(0xffff, &fw->data[offset], length); 1555 if (be16_to_cpu(hdr->crc) != crc) { 1556 devlink_flash_update_status_notify(devlink, 1557 "Firmware image CRC check failed", 1558 NULL, 0, 0); 1559 return -EINVAL; 1560 } 1561 1562 *data = &fw->data[offset]; 1563 *size = length; 1564 1565 return 0; 1566 } 1567 1568 static int 1569 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev, 1570 const struct firmware *fw) 1571 { 1572 struct mtd_info *mtd = dev_get_drvdata(dev); 1573 struct ptp_ocp *bp = devlink_priv(devlink); 1574 size_t off, len, size, resid, wrote; 1575 struct erase_info erase; 1576 size_t base, blksz; 1577 const u8 *data; 1578 int err; 1579 1580 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size); 1581 if (err) 1582 goto out; 1583 1584 off = 0; 1585 base = bp->flash_start; 1586 blksz = 4096; 1587 resid = size; 1588 1589 while (resid) { 1590 devlink_flash_update_status_notify(devlink, "Flashing", 1591 NULL, off, size); 1592 1593 len = min_t(size_t, resid, blksz); 1594 erase.addr = base + off; 1595 erase.len = blksz; 1596 1597 err = mtd_erase(mtd, &erase); 1598 if (err) 1599 goto out; 1600 1601 err = mtd_write(mtd, base + off, len, &wrote, data + off); 1602 if (err) 1603 goto out; 1604 1605 off += blksz; 1606 resid -= len; 1607 } 1608 out: 1609 return err; 1610 } 1611 1612 static int 1613 ptp_ocp_devlink_flash_update(struct devlink *devlink, 1614 struct devlink_flash_update_params *params, 1615 struct netlink_ext_ack *extack) 1616 { 1617 struct ptp_ocp *bp = devlink_priv(devlink); 1618 struct device *dev; 1619 const char *msg; 1620 int err; 1621 1622 dev = ptp_ocp_find_flash(bp); 1623 if (!dev) { 1624 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n"); 1625 return -ENODEV; 1626 } 1627 1628 devlink_flash_update_status_notify(devlink, "Preparing to flash", 1629 NULL, 0, 0); 1630 1631 err = ptp_ocp_devlink_flash(devlink, dev, params->fw); 1632 1633 msg = err ? "Flash error" : "Flash complete"; 1634 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0); 1635 1636 put_device(dev); 1637 return err; 1638 } 1639 1640 static int 1641 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, 1642 struct netlink_ext_ack *extack) 1643 { 1644 struct ptp_ocp *bp = devlink_priv(devlink); 1645 const char *fw_image; 1646 char buf[32]; 1647 int err; 1648 1649 fw_image = bp->fw_loader ? "loader" : "fw"; 1650 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version); 1651 err = devlink_info_version_running_put(req, fw_image, buf); 1652 if (err) 1653 return err; 1654 1655 if (!bp->has_eeprom_data) { 1656 ptp_ocp_read_eeprom(bp); 1657 if (!bp->has_eeprom_data) 1658 return 0; 1659 } 1660 1661 sprintf(buf, "%pM", bp->serial); 1662 err = devlink_info_serial_number_put(req, buf); 1663 if (err) 1664 return err; 1665 1666 err = devlink_info_version_fixed_put(req, 1667 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID, 1668 bp->board_id); 1669 if (err) 1670 return err; 1671 1672 return 0; 1673 } 1674 1675 static const struct devlink_ops ptp_ocp_devlink_ops = { 1676 .flash_update = ptp_ocp_devlink_flash_update, 1677 .info_get = ptp_ocp_devlink_info_get, 1678 }; 1679 1680 static void __iomem * 1681 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size) 1682 { 1683 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp"); 1684 1685 return devm_ioremap_resource(&bp->pdev->dev, &res); 1686 } 1687 1688 static void __iomem * 1689 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r) 1690 { 1691 resource_size_t start; 1692 1693 start = pci_resource_start(bp->pdev, 0) + r->offset; 1694 return __ptp_ocp_get_mem(bp, start, r->size); 1695 } 1696 1697 static void 1698 ptp_ocp_set_irq_resource(struct resource *res, int irq) 1699 { 1700 struct resource r = DEFINE_RES_IRQ(irq); 1701 *res = r; 1702 } 1703 1704 static void 1705 ptp_ocp_set_mem_resource(struct resource *res, resource_size_t start, int size) 1706 { 1707 struct resource r = DEFINE_RES_MEM(start, size); 1708 *res = r; 1709 } 1710 1711 static int 1712 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r) 1713 { 1714 struct ptp_ocp_flash_info *info; 1715 struct pci_dev *pdev = bp->pdev; 1716 struct platform_device *p; 1717 struct resource res[2]; 1718 resource_size_t start; 1719 int id; 1720 1721 start = pci_resource_start(pdev, 0) + r->offset; 1722 ptp_ocp_set_mem_resource(&res[0], start, r->size); 1723 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec)); 1724 1725 info = r->extra; 1726 id = pci_dev_id(pdev) << 1; 1727 id += info->pci_offset; 1728 1729 p = platform_device_register_resndata(&pdev->dev, info->name, id, 1730 res, 2, info->data, 1731 info->data_size); 1732 if (IS_ERR(p)) 1733 return PTR_ERR(p); 1734 1735 bp_assign_entry(bp, r, p); 1736 1737 return 0; 1738 } 1739 1740 static struct platform_device * 1741 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id) 1742 { 1743 struct ptp_ocp_i2c_info *info; 1744 struct resource res[2]; 1745 resource_size_t start; 1746 1747 info = r->extra; 1748 start = pci_resource_start(pdev, 0) + r->offset; 1749 ptp_ocp_set_mem_resource(&res[0], start, r->size); 1750 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec)); 1751 1752 return platform_device_register_resndata(&pdev->dev, info->name, 1753 id, res, 2, 1754 info->data, info->data_size); 1755 } 1756 1757 static int 1758 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r) 1759 { 1760 struct pci_dev *pdev = bp->pdev; 1761 struct ptp_ocp_i2c_info *info; 1762 struct platform_device *p; 1763 struct clk_hw *clk; 1764 char buf[32]; 1765 int id; 1766 1767 info = r->extra; 1768 id = pci_dev_id(bp->pdev); 1769 1770 sprintf(buf, "AXI.%d", id); 1771 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0, 1772 info->fixed_rate); 1773 if (IS_ERR(clk)) 1774 return PTR_ERR(clk); 1775 bp->i2c_clk = clk; 1776 1777 sprintf(buf, "%s.%d", info->name, id); 1778 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf); 1779 p = ptp_ocp_i2c_bus(bp->pdev, r, id); 1780 if (IS_ERR(p)) 1781 return PTR_ERR(p); 1782 1783 bp_assign_entry(bp, r, p); 1784 1785 return 0; 1786 } 1787 1788 /* The expectation is that this is triggered only on error. */ 1789 static irqreturn_t 1790 ptp_ocp_signal_irq(int irq, void *priv) 1791 { 1792 struct ptp_ocp_ext_src *ext = priv; 1793 struct signal_reg __iomem *reg = ext->mem; 1794 struct ptp_ocp *bp = ext->bp; 1795 u32 enable, status; 1796 int gen; 1797 1798 gen = ext->info->index - 1; 1799 1800 enable = ioread32(®->enable); 1801 status = ioread32(®->status); 1802 1803 /* disable generator on error */ 1804 if (status || !enable) { 1805 iowrite32(0, ®->intr_mask); 1806 iowrite32(0, ®->enable); 1807 bp->signal[gen].running = false; 1808 } 1809 1810 iowrite32(0, ®->intr); /* ack interrupt */ 1811 1812 return IRQ_HANDLED; 1813 } 1814 1815 static int 1816 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s) 1817 { 1818 struct ptp_system_timestamp sts; 1819 struct timespec64 ts; 1820 ktime_t start_ns; 1821 int err; 1822 1823 if (!s->period) 1824 return 0; 1825 1826 if (!s->pulse) 1827 s->pulse = ktime_divns(s->period * s->duty, 100); 1828 1829 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts); 1830 if (err) 1831 return err; 1832 1833 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC; 1834 if (!s->start) { 1835 /* roundup() does not work on 32-bit systems */ 1836 s->start = DIV64_U64_ROUND_UP(start_ns, s->period); 1837 s->start = ktime_add(s->start, s->phase); 1838 } 1839 1840 if (s->duty < 1 || s->duty > 99) 1841 return -EINVAL; 1842 1843 if (s->pulse < 1 || s->pulse > s->period) 1844 return -EINVAL; 1845 1846 if (s->start < start_ns) 1847 return -EINVAL; 1848 1849 bp->signal[gen] = *s; 1850 1851 return 0; 1852 } 1853 1854 static int 1855 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen, 1856 struct ptp_perout_request *req) 1857 { 1858 struct ptp_ocp_signal s = { }; 1859 1860 s.polarity = bp->signal[gen].polarity; 1861 s.period = ktime_set(req->period.sec, req->period.nsec); 1862 if (!s.period) 1863 return 0; 1864 1865 if (req->flags & PTP_PEROUT_DUTY_CYCLE) { 1866 s.pulse = ktime_set(req->on.sec, req->on.nsec); 1867 s.duty = ktime_divns(s.pulse * 100, s.period); 1868 } 1869 1870 if (req->flags & PTP_PEROUT_PHASE) 1871 s.phase = ktime_set(req->phase.sec, req->phase.nsec); 1872 else 1873 s.start = ktime_set(req->start.sec, req->start.nsec); 1874 1875 return ptp_ocp_signal_set(bp, gen, &s); 1876 } 1877 1878 static int 1879 ptp_ocp_signal_enable(void *priv, u32 req, bool enable) 1880 { 1881 struct ptp_ocp_ext_src *ext = priv; 1882 struct signal_reg __iomem *reg = ext->mem; 1883 struct ptp_ocp *bp = ext->bp; 1884 struct timespec64 ts; 1885 int gen; 1886 1887 gen = ext->info->index - 1; 1888 1889 iowrite32(0, ®->intr_mask); 1890 iowrite32(0, ®->enable); 1891 bp->signal[gen].running = false; 1892 if (!enable) 1893 return 0; 1894 1895 ts = ktime_to_timespec64(bp->signal[gen].start); 1896 iowrite32(ts.tv_sec, ®->start_sec); 1897 iowrite32(ts.tv_nsec, ®->start_ns); 1898 1899 ts = ktime_to_timespec64(bp->signal[gen].period); 1900 iowrite32(ts.tv_sec, ®->period_sec); 1901 iowrite32(ts.tv_nsec, ®->period_ns); 1902 1903 ts = ktime_to_timespec64(bp->signal[gen].pulse); 1904 iowrite32(ts.tv_sec, ®->pulse_sec); 1905 iowrite32(ts.tv_nsec, ®->pulse_ns); 1906 1907 iowrite32(bp->signal[gen].polarity, ®->polarity); 1908 iowrite32(0, ®->repeat_count); 1909 1910 iowrite32(0, ®->intr); /* clear interrupt state */ 1911 iowrite32(1, ®->intr_mask); /* enable interrupt */ 1912 iowrite32(3, ®->enable); /* valid & enable */ 1913 1914 bp->signal[gen].running = true; 1915 1916 return 0; 1917 } 1918 1919 static irqreturn_t 1920 ptp_ocp_ts_irq(int irq, void *priv) 1921 { 1922 struct ptp_ocp_ext_src *ext = priv; 1923 struct ts_reg __iomem *reg = ext->mem; 1924 struct ptp_clock_event ev; 1925 u32 sec, nsec; 1926 1927 if (ext == ext->bp->pps) { 1928 if (ext->bp->pps_req_map & OCP_REQ_PPS) { 1929 ev.type = PTP_CLOCK_PPS; 1930 ptp_clock_event(ext->bp->ptp, &ev); 1931 } 1932 1933 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0) 1934 goto out; 1935 } 1936 1937 /* XXX should fix API - this converts s/ns -> ts -> s/ns */ 1938 sec = ioread32(®->time_sec); 1939 nsec = ioread32(®->time_ns); 1940 1941 ev.type = PTP_CLOCK_EXTTS; 1942 ev.index = ext->info->index; 1943 ev.timestamp = sec * NSEC_PER_SEC + nsec; 1944 1945 ptp_clock_event(ext->bp->ptp, &ev); 1946 1947 out: 1948 iowrite32(1, ®->intr); /* write 1 to ack */ 1949 1950 return IRQ_HANDLED; 1951 } 1952 1953 static int 1954 ptp_ocp_ts_enable(void *priv, u32 req, bool enable) 1955 { 1956 struct ptp_ocp_ext_src *ext = priv; 1957 struct ts_reg __iomem *reg = ext->mem; 1958 struct ptp_ocp *bp = ext->bp; 1959 1960 if (ext == bp->pps) { 1961 u32 old_map = bp->pps_req_map; 1962 1963 if (enable) 1964 bp->pps_req_map |= req; 1965 else 1966 bp->pps_req_map &= ~req; 1967 1968 /* if no state change, just return */ 1969 if ((!!old_map ^ !!bp->pps_req_map) == 0) 1970 return 0; 1971 } 1972 1973 if (enable) { 1974 iowrite32(1, ®->enable); 1975 iowrite32(1, ®->intr_mask); 1976 iowrite32(1, ®->intr); 1977 } else { 1978 iowrite32(0, ®->intr_mask); 1979 iowrite32(0, ®->enable); 1980 } 1981 1982 return 0; 1983 } 1984 1985 static void 1986 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext) 1987 { 1988 ext->info->enable(ext, ~0, false); 1989 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext); 1990 kfree(ext); 1991 } 1992 1993 static int 1994 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r) 1995 { 1996 struct pci_dev *pdev = bp->pdev; 1997 struct ptp_ocp_ext_src *ext; 1998 int err; 1999 2000 ext = kzalloc(sizeof(*ext), GFP_KERNEL); 2001 if (!ext) 2002 return -ENOMEM; 2003 2004 ext->mem = ptp_ocp_get_mem(bp, r); 2005 if (IS_ERR(ext->mem)) { 2006 err = PTR_ERR(ext->mem); 2007 goto out; 2008 } 2009 2010 ext->bp = bp; 2011 ext->info = r->extra; 2012 ext->irq_vec = r->irq_vec; 2013 2014 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL, 2015 ext, "ocp%d.%s", bp->id, r->name); 2016 if (err) { 2017 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec); 2018 goto out; 2019 } 2020 2021 bp_assign_entry(bp, r, ext); 2022 2023 return 0; 2024 2025 out: 2026 kfree(ext); 2027 return err; 2028 } 2029 2030 static int 2031 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r) 2032 { 2033 struct pci_dev *pdev = bp->pdev; 2034 struct uart_8250_port uart; 2035 2036 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets 2037 * the serial port device claim and release the pci resource. 2038 */ 2039 memset(&uart, 0, sizeof(uart)); 2040 uart.port.dev = &pdev->dev; 2041 uart.port.iotype = UPIO_MEM; 2042 uart.port.regshift = 2; 2043 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset; 2044 uart.port.irq = pci_irq_vector(pdev, r->irq_vec); 2045 uart.port.uartclk = 50000000; 2046 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST; 2047 uart.port.type = PORT_16550A; 2048 2049 return serial8250_register_8250_port(&uart); 2050 } 2051 2052 static int 2053 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r) 2054 { 2055 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra; 2056 struct ptp_ocp_serial_port port = {}; 2057 2058 port.line = ptp_ocp_serial_line(bp, r); 2059 if (port.line < 0) 2060 return port.line; 2061 2062 if (p) 2063 port.baud = p->baud; 2064 2065 bp_assign_entry(bp, r, port); 2066 2067 return 0; 2068 } 2069 2070 static int 2071 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r) 2072 { 2073 void __iomem *mem; 2074 2075 mem = ptp_ocp_get_mem(bp, r); 2076 if (IS_ERR(mem)) 2077 return PTR_ERR(mem); 2078 2079 bp_assign_entry(bp, r, mem); 2080 2081 return 0; 2082 } 2083 2084 static void 2085 ptp_ocp_nmea_out_init(struct ptp_ocp *bp) 2086 { 2087 if (!bp->nmea_out) 2088 return; 2089 2090 iowrite32(0, &bp->nmea_out->ctrl); /* disable */ 2091 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */ 2092 iowrite32(1, &bp->nmea_out->ctrl); /* enable */ 2093 } 2094 2095 static void 2096 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg) 2097 { 2098 u32 val; 2099 2100 iowrite32(0, ®->enable); /* disable */ 2101 2102 val = ioread32(®->polarity); 2103 s->polarity = val ? true : false; 2104 s->duty = 50; 2105 } 2106 2107 static void 2108 ptp_ocp_signal_init(struct ptp_ocp *bp) 2109 { 2110 int i; 2111 2112 for (i = 0; i < 4; i++) 2113 if (bp->signal_out[i]) 2114 _ptp_ocp_signal_init(&bp->signal[i], 2115 bp->signal_out[i]->mem); 2116 } 2117 2118 static void 2119 ptp_ocp_attr_group_del(struct ptp_ocp *bp) 2120 { 2121 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group); 2122 kfree(bp->attr_group); 2123 } 2124 2125 static int 2126 ptp_ocp_attr_group_add(struct ptp_ocp *bp, 2127 const struct ocp_attr_group *attr_tbl) 2128 { 2129 int count, i; 2130 int err; 2131 2132 count = 0; 2133 for (i = 0; attr_tbl[i].cap; i++) 2134 if (attr_tbl[i].cap & bp->fw_cap) 2135 count++; 2136 2137 bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *), 2138 GFP_KERNEL); 2139 if (!bp->attr_group) 2140 return -ENOMEM; 2141 2142 count = 0; 2143 for (i = 0; attr_tbl[i].cap; i++) 2144 if (attr_tbl[i].cap & bp->fw_cap) 2145 bp->attr_group[count++] = attr_tbl[i].group; 2146 2147 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group); 2148 if (err) 2149 bp->attr_group[0] = NULL; 2150 2151 return err; 2152 } 2153 2154 static void 2155 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable) 2156 { 2157 u32 ctrl; 2158 bool on; 2159 2160 ctrl = ioread32(reg); 2161 on = ctrl & bit; 2162 if (on ^ enable) { 2163 ctrl &= ~bit; 2164 ctrl |= enable ? bit : 0; 2165 iowrite32(ctrl, reg); 2166 } 2167 } 2168 2169 static void 2170 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable) 2171 { 2172 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl, 2173 IRIG_M_CTRL_ENABLE, enable); 2174 } 2175 2176 static void 2177 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable) 2178 { 2179 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl, 2180 IRIG_S_CTRL_ENABLE, enable); 2181 } 2182 2183 static void 2184 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable) 2185 { 2186 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl, 2187 DCF_M_CTRL_ENABLE, enable); 2188 } 2189 2190 static void 2191 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable) 2192 { 2193 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl, 2194 DCF_S_CTRL_ENABLE, enable); 2195 } 2196 2197 static void 2198 __handle_signal_outputs(struct ptp_ocp *bp, u32 val) 2199 { 2200 ptp_ocp_irig_out(bp, val & 0x00100010); 2201 ptp_ocp_dcf_out(bp, val & 0x00200020); 2202 } 2203 2204 static void 2205 __handle_signal_inputs(struct ptp_ocp *bp, u32 val) 2206 { 2207 ptp_ocp_irig_in(bp, val & 0x00100010); 2208 ptp_ocp_dcf_in(bp, val & 0x00200020); 2209 } 2210 2211 static u32 2212 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr) 2213 { 2214 u32 __iomem *gpio; 2215 u32 shift; 2216 2217 if (bp->sma[sma_nr - 1].fixed_fcn) 2218 return (sma_nr - 1) & 1; 2219 2220 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN) 2221 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1; 2222 else 2223 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2; 2224 shift = sma_nr & 1 ? 0 : 16; 2225 2226 return (ioread32(gpio) >> shift) & 0xffff; 2227 } 2228 2229 static int 2230 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val) 2231 { 2232 u32 reg, mask, shift; 2233 unsigned long flags; 2234 u32 __iomem *gpio; 2235 2236 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2; 2237 shift = sma_nr & 1 ? 0 : 16; 2238 2239 mask = 0xffff << (16 - shift); 2240 2241 spin_lock_irqsave(&bp->lock, flags); 2242 2243 reg = ioread32(gpio); 2244 reg = (reg & mask) | (val << shift); 2245 2246 __handle_signal_outputs(bp, reg); 2247 2248 iowrite32(reg, gpio); 2249 2250 spin_unlock_irqrestore(&bp->lock, flags); 2251 2252 return 0; 2253 } 2254 2255 static int 2256 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val) 2257 { 2258 u32 reg, mask, shift; 2259 unsigned long flags; 2260 u32 __iomem *gpio; 2261 2262 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1; 2263 shift = sma_nr & 1 ? 0 : 16; 2264 2265 mask = 0xffff << (16 - shift); 2266 2267 spin_lock_irqsave(&bp->lock, flags); 2268 2269 reg = ioread32(gpio); 2270 reg = (reg & mask) | (val << shift); 2271 2272 __handle_signal_inputs(bp, reg); 2273 2274 iowrite32(reg, gpio); 2275 2276 spin_unlock_irqrestore(&bp->lock, flags); 2277 2278 return 0; 2279 } 2280 2281 static void 2282 ptp_ocp_sma_fb_init(struct ptp_ocp *bp) 2283 { 2284 u32 reg; 2285 int i; 2286 2287 /* defaults */ 2288 bp->sma[0].mode = SMA_MODE_IN; 2289 bp->sma[1].mode = SMA_MODE_IN; 2290 bp->sma[2].mode = SMA_MODE_OUT; 2291 bp->sma[3].mode = SMA_MODE_OUT; 2292 for (i = 0; i < 4; i++) 2293 bp->sma[i].default_fcn = i & 1; 2294 2295 /* If no SMA1 map, the pin functions and directions are fixed. */ 2296 if (!bp->sma_map1) { 2297 for (i = 0; i < 4; i++) { 2298 bp->sma[i].fixed_fcn = true; 2299 bp->sma[i].fixed_dir = true; 2300 } 2301 return; 2302 } 2303 2304 /* If SMA2 GPIO output map is all 1, it is not present. 2305 * This indicates the firmware has fixed direction SMA pins. 2306 */ 2307 reg = ioread32(&bp->sma_map2->gpio2); 2308 if (reg == 0xffffffff) { 2309 for (i = 0; i < 4; i++) 2310 bp->sma[i].fixed_dir = true; 2311 } else { 2312 reg = ioread32(&bp->sma_map1->gpio1); 2313 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT; 2314 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT; 2315 2316 reg = ioread32(&bp->sma_map1->gpio2); 2317 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN; 2318 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN; 2319 } 2320 } 2321 2322 static const struct ocp_sma_op ocp_fb_sma_op = { 2323 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out }, 2324 .init = ptp_ocp_sma_fb_init, 2325 .get = ptp_ocp_sma_fb_get, 2326 .set_inputs = ptp_ocp_sma_fb_set_inputs, 2327 .set_output = ptp_ocp_sma_fb_set_output, 2328 }; 2329 2330 static int 2331 ptp_ocp_fb_set_pins(struct ptp_ocp *bp) 2332 { 2333 struct ptp_pin_desc *config; 2334 int i; 2335 2336 config = kcalloc(4, sizeof(*config), GFP_KERNEL); 2337 if (!config) 2338 return -ENOMEM; 2339 2340 for (i = 0; i < 4; i++) { 2341 sprintf(config[i].name, "sma%d", i + 1); 2342 config[i].index = i; 2343 } 2344 2345 bp->ptp_info.n_pins = 4; 2346 bp->ptp_info.pin_config = config; 2347 2348 return 0; 2349 } 2350 2351 static void 2352 ptp_ocp_fb_set_version(struct ptp_ocp *bp) 2353 { 2354 u64 cap = OCP_CAP_BASIC; 2355 u32 version; 2356 2357 version = ioread32(&bp->image->version); 2358 2359 /* if lower 16 bits are empty, this is the fw loader. */ 2360 if ((version & 0xffff) == 0) { 2361 version = version >> 16; 2362 bp->fw_loader = true; 2363 } 2364 2365 bp->fw_tag = version >> 15; 2366 bp->fw_version = version & 0x7fff; 2367 2368 if (bp->fw_tag) { 2369 /* FPGA firmware */ 2370 if (version >= 5) 2371 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ; 2372 } else { 2373 /* SOM firmware */ 2374 if (version >= 19) 2375 cap |= OCP_CAP_SIGNAL; 2376 if (version >= 20) 2377 cap |= OCP_CAP_FREQ; 2378 } 2379 2380 bp->fw_cap = cap; 2381 } 2382 2383 /* FB specific board initializers; last "resource" registered. */ 2384 static int 2385 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r) 2386 { 2387 int err; 2388 2389 bp->flash_start = 1024 * 4096; 2390 bp->eeprom_map = fb_eeprom_map; 2391 bp->fw_version = ioread32(&bp->image->version); 2392 bp->sma_op = &ocp_fb_sma_op; 2393 2394 ptp_ocp_fb_set_version(bp); 2395 2396 ptp_ocp_tod_init(bp); 2397 ptp_ocp_nmea_out_init(bp); 2398 ptp_ocp_sma_init(bp); 2399 ptp_ocp_signal_init(bp); 2400 2401 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups); 2402 if (err) 2403 return err; 2404 2405 err = ptp_ocp_fb_set_pins(bp); 2406 if (err) 2407 return err; 2408 2409 return ptp_ocp_init_clock(bp); 2410 } 2411 2412 static bool 2413 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r) 2414 { 2415 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs; 2416 2417 if (!allow) 2418 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n", 2419 r->irq_vec, r->name); 2420 return allow; 2421 } 2422 2423 static int 2424 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data) 2425 { 2426 struct ocp_resource *r, *table; 2427 int err = 0; 2428 2429 table = (struct ocp_resource *)driver_data; 2430 for (r = table; r->setup; r++) { 2431 if (!ptp_ocp_allow_irq(bp, r)) 2432 continue; 2433 err = r->setup(bp, r); 2434 if (err) { 2435 dev_err(&bp->pdev->dev, 2436 "Could not register %s: err %d\n", 2437 r->name, err); 2438 break; 2439 } 2440 } 2441 return err; 2442 } 2443 2444 static void 2445 ptp_ocp_art_sma_init(struct ptp_ocp *bp) 2446 { 2447 u32 reg; 2448 int i; 2449 2450 /* defaults */ 2451 bp->sma[0].mode = SMA_MODE_IN; 2452 bp->sma[1].mode = SMA_MODE_IN; 2453 bp->sma[2].mode = SMA_MODE_OUT; 2454 bp->sma[3].mode = SMA_MODE_OUT; 2455 2456 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */ 2457 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */ 2458 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */ 2459 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */ 2460 2461 /* If no SMA map, the pin functions and directions are fixed. */ 2462 if (!bp->art_sma) { 2463 for (i = 0; i < 4; i++) { 2464 bp->sma[i].fixed_fcn = true; 2465 bp->sma[i].fixed_dir = true; 2466 } 2467 return; 2468 } 2469 2470 for (i = 0; i < 4; i++) { 2471 reg = ioread32(&bp->art_sma->map[i].gpio); 2472 2473 switch (reg & 0xff) { 2474 case 0: 2475 bp->sma[i].fixed_fcn = true; 2476 bp->sma[i].fixed_dir = true; 2477 break; 2478 case 1: 2479 case 8: 2480 bp->sma[i].mode = SMA_MODE_IN; 2481 break; 2482 default: 2483 bp->sma[i].mode = SMA_MODE_OUT; 2484 break; 2485 } 2486 } 2487 } 2488 2489 static u32 2490 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr) 2491 { 2492 if (bp->sma[sma_nr - 1].fixed_fcn) 2493 return bp->sma[sma_nr - 1].default_fcn; 2494 2495 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff; 2496 } 2497 2498 /* note: store 0 is considered invalid. */ 2499 static int 2500 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val) 2501 { 2502 unsigned long flags; 2503 u32 __iomem *gpio; 2504 int err = 0; 2505 u32 reg; 2506 2507 val &= SMA_SELECT_MASK; 2508 if (hweight32(val) > 1) 2509 return -EINVAL; 2510 2511 gpio = &bp->art_sma->map[sma_nr - 1].gpio; 2512 2513 spin_lock_irqsave(&bp->lock, flags); 2514 reg = ioread32(gpio); 2515 if (((reg >> 16) & val) == 0) { 2516 err = -EOPNOTSUPP; 2517 } else { 2518 reg = (reg & 0xff00) | (val & 0xff); 2519 iowrite32(reg, gpio); 2520 } 2521 spin_unlock_irqrestore(&bp->lock, flags); 2522 2523 return err; 2524 } 2525 2526 static const struct ocp_sma_op ocp_art_sma_op = { 2527 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out }, 2528 .init = ptp_ocp_art_sma_init, 2529 .get = ptp_ocp_art_sma_get, 2530 .set_inputs = ptp_ocp_art_sma_set, 2531 .set_output = ptp_ocp_art_sma_set, 2532 }; 2533 2534 /* ART specific board initializers; last "resource" registered. */ 2535 static int 2536 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r) 2537 { 2538 int err; 2539 2540 bp->flash_start = 0x1000000; 2541 bp->eeprom_map = art_eeprom_map; 2542 bp->fw_cap = OCP_CAP_BASIC; 2543 bp->fw_version = ioread32(&bp->reg->version); 2544 bp->fw_tag = 2; 2545 bp->sma_op = &ocp_art_sma_op; 2546 2547 /* Enable MAC serial port during initialisation */ 2548 iowrite32(1, &bp->board_config->mro50_serial_activate); 2549 2550 ptp_ocp_sma_init(bp); 2551 2552 err = ptp_ocp_attr_group_add(bp, art_timecard_groups); 2553 if (err) 2554 return err; 2555 2556 return ptp_ocp_init_clock(bp); 2557 } 2558 2559 static ssize_t 2560 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf, 2561 int def_val) 2562 { 2563 const char *name; 2564 ssize_t count; 2565 2566 count = sysfs_emit(buf, "OUT: "); 2567 name = ptp_ocp_select_name_from_val(tbl, val); 2568 if (!name) 2569 name = ptp_ocp_select_name_from_val(tbl, def_val); 2570 count += sysfs_emit_at(buf, count, "%s\n", name); 2571 return count; 2572 } 2573 2574 static ssize_t 2575 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf, 2576 int def_val) 2577 { 2578 const char *name; 2579 ssize_t count; 2580 int i; 2581 2582 count = sysfs_emit(buf, "IN: "); 2583 for (i = 0; tbl[i].name; i++) { 2584 if (val & tbl[i].value) { 2585 name = tbl[i].name; 2586 count += sysfs_emit_at(buf, count, "%s ", name); 2587 } 2588 } 2589 if (!val && def_val >= 0) { 2590 name = ptp_ocp_select_name_from_val(tbl, def_val); 2591 count += sysfs_emit_at(buf, count, "%s ", name); 2592 } 2593 if (count) 2594 count--; 2595 count += sysfs_emit_at(buf, count, "\n"); 2596 return count; 2597 } 2598 2599 static int 2600 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf, 2601 enum ptp_ocp_sma_mode *mode) 2602 { 2603 int idx, count, dir; 2604 char **argv; 2605 int ret; 2606 2607 argv = argv_split(GFP_KERNEL, buf, &count); 2608 if (!argv) 2609 return -ENOMEM; 2610 2611 ret = -EINVAL; 2612 if (!count) 2613 goto out; 2614 2615 idx = 0; 2616 dir = *mode == SMA_MODE_IN ? 0 : 1; 2617 if (!strcasecmp("IN:", argv[0])) { 2618 dir = 0; 2619 idx++; 2620 } 2621 if (!strcasecmp("OUT:", argv[0])) { 2622 dir = 1; 2623 idx++; 2624 } 2625 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT; 2626 2627 ret = 0; 2628 for (; idx < count; idx++) 2629 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]); 2630 if (ret < 0) 2631 ret = -EINVAL; 2632 2633 out: 2634 argv_free(argv); 2635 return ret; 2636 } 2637 2638 static ssize_t 2639 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf, 2640 int default_in_val, int default_out_val) 2641 { 2642 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1]; 2643 const struct ocp_selector * const *tbl; 2644 u32 val; 2645 2646 tbl = bp->sma_op->tbl; 2647 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK; 2648 2649 if (sma->mode == SMA_MODE_IN) { 2650 if (sma->disabled) 2651 val = SMA_DISABLE; 2652 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val); 2653 } 2654 2655 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val); 2656 } 2657 2658 static ssize_t 2659 sma1_show(struct device *dev, struct device_attribute *attr, char *buf) 2660 { 2661 struct ptp_ocp *bp = dev_get_drvdata(dev); 2662 2663 return ptp_ocp_sma_show(bp, 1, buf, 0, 1); 2664 } 2665 2666 static ssize_t 2667 sma2_show(struct device *dev, struct device_attribute *attr, char *buf) 2668 { 2669 struct ptp_ocp *bp = dev_get_drvdata(dev); 2670 2671 return ptp_ocp_sma_show(bp, 2, buf, -1, 1); 2672 } 2673 2674 static ssize_t 2675 sma3_show(struct device *dev, struct device_attribute *attr, char *buf) 2676 { 2677 struct ptp_ocp *bp = dev_get_drvdata(dev); 2678 2679 return ptp_ocp_sma_show(bp, 3, buf, -1, 0); 2680 } 2681 2682 static ssize_t 2683 sma4_show(struct device *dev, struct device_attribute *attr, char *buf) 2684 { 2685 struct ptp_ocp *bp = dev_get_drvdata(dev); 2686 2687 return ptp_ocp_sma_show(bp, 4, buf, -1, 1); 2688 } 2689 2690 static int 2691 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr) 2692 { 2693 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1]; 2694 enum ptp_ocp_sma_mode mode; 2695 int val; 2696 2697 mode = sma->mode; 2698 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode); 2699 if (val < 0) 2700 return val; 2701 2702 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE)) 2703 return -EOPNOTSUPP; 2704 2705 if (sma->fixed_fcn) { 2706 if (val != sma->default_fcn) 2707 return -EOPNOTSUPP; 2708 return 0; 2709 } 2710 2711 sma->disabled = !!(val & SMA_DISABLE); 2712 2713 if (mode != sma->mode) { 2714 if (mode == SMA_MODE_IN) 2715 ptp_ocp_sma_set_output(bp, sma_nr, 0); 2716 else 2717 ptp_ocp_sma_set_inputs(bp, sma_nr, 0); 2718 sma->mode = mode; 2719 } 2720 2721 if (!sma->fixed_dir) 2722 val |= SMA_ENABLE; /* add enable bit */ 2723 2724 if (sma->disabled) 2725 val = 0; 2726 2727 if (mode == SMA_MODE_IN) 2728 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val); 2729 else 2730 val = ptp_ocp_sma_set_output(bp, sma_nr, val); 2731 2732 return val; 2733 } 2734 2735 static ssize_t 2736 sma1_store(struct device *dev, struct device_attribute *attr, 2737 const char *buf, size_t count) 2738 { 2739 struct ptp_ocp *bp = dev_get_drvdata(dev); 2740 int err; 2741 2742 err = ptp_ocp_sma_store(bp, buf, 1); 2743 return err ? err : count; 2744 } 2745 2746 static ssize_t 2747 sma2_store(struct device *dev, struct device_attribute *attr, 2748 const char *buf, size_t count) 2749 { 2750 struct ptp_ocp *bp = dev_get_drvdata(dev); 2751 int err; 2752 2753 err = ptp_ocp_sma_store(bp, buf, 2); 2754 return err ? err : count; 2755 } 2756 2757 static ssize_t 2758 sma3_store(struct device *dev, struct device_attribute *attr, 2759 const char *buf, size_t count) 2760 { 2761 struct ptp_ocp *bp = dev_get_drvdata(dev); 2762 int err; 2763 2764 err = ptp_ocp_sma_store(bp, buf, 3); 2765 return err ? err : count; 2766 } 2767 2768 static ssize_t 2769 sma4_store(struct device *dev, struct device_attribute *attr, 2770 const char *buf, size_t count) 2771 { 2772 struct ptp_ocp *bp = dev_get_drvdata(dev); 2773 int err; 2774 2775 err = ptp_ocp_sma_store(bp, buf, 4); 2776 return err ? err : count; 2777 } 2778 static DEVICE_ATTR_RW(sma1); 2779 static DEVICE_ATTR_RW(sma2); 2780 static DEVICE_ATTR_RW(sma3); 2781 static DEVICE_ATTR_RW(sma4); 2782 2783 static ssize_t 2784 available_sma_inputs_show(struct device *dev, 2785 struct device_attribute *attr, char *buf) 2786 { 2787 struct ptp_ocp *bp = dev_get_drvdata(dev); 2788 2789 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf); 2790 } 2791 static DEVICE_ATTR_RO(available_sma_inputs); 2792 2793 static ssize_t 2794 available_sma_outputs_show(struct device *dev, 2795 struct device_attribute *attr, char *buf) 2796 { 2797 struct ptp_ocp *bp = dev_get_drvdata(dev); 2798 2799 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf); 2800 } 2801 static DEVICE_ATTR_RO(available_sma_outputs); 2802 2803 #define EXT_ATTR_RO(_group, _name, _val) \ 2804 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \ 2805 { __ATTR_RO(_name), (void *)_val } 2806 #define EXT_ATTR_RW(_group, _name, _val) \ 2807 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \ 2808 { __ATTR_RW(_name), (void *)_val } 2809 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr) 2810 2811 /* period [duty [phase [polarity]]] */ 2812 static ssize_t 2813 signal_store(struct device *dev, struct device_attribute *attr, 2814 const char *buf, size_t count) 2815 { 2816 struct dev_ext_attribute *ea = to_ext_attr(attr); 2817 struct ptp_ocp *bp = dev_get_drvdata(dev); 2818 struct ptp_ocp_signal s = { }; 2819 int gen = (uintptr_t)ea->var; 2820 int argc, err; 2821 char **argv; 2822 2823 argv = argv_split(GFP_KERNEL, buf, &argc); 2824 if (!argv) 2825 return -ENOMEM; 2826 2827 err = -EINVAL; 2828 s.duty = bp->signal[gen].duty; 2829 s.phase = bp->signal[gen].phase; 2830 s.period = bp->signal[gen].period; 2831 s.polarity = bp->signal[gen].polarity; 2832 2833 switch (argc) { 2834 case 4: 2835 argc--; 2836 err = kstrtobool(argv[argc], &s.polarity); 2837 if (err) 2838 goto out; 2839 fallthrough; 2840 case 3: 2841 argc--; 2842 err = kstrtou64(argv[argc], 0, &s.phase); 2843 if (err) 2844 goto out; 2845 fallthrough; 2846 case 2: 2847 argc--; 2848 err = kstrtoint(argv[argc], 0, &s.duty); 2849 if (err) 2850 goto out; 2851 fallthrough; 2852 case 1: 2853 argc--; 2854 err = kstrtou64(argv[argc], 0, &s.period); 2855 if (err) 2856 goto out; 2857 break; 2858 default: 2859 goto out; 2860 } 2861 2862 err = ptp_ocp_signal_set(bp, gen, &s); 2863 if (err) 2864 goto out; 2865 2866 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0); 2867 2868 out: 2869 argv_free(argv); 2870 return err ? err : count; 2871 } 2872 2873 static ssize_t 2874 signal_show(struct device *dev, struct device_attribute *attr, char *buf) 2875 { 2876 struct dev_ext_attribute *ea = to_ext_attr(attr); 2877 struct ptp_ocp *bp = dev_get_drvdata(dev); 2878 struct ptp_ocp_signal *signal; 2879 struct timespec64 ts; 2880 ssize_t count; 2881 int i; 2882 2883 i = (uintptr_t)ea->var; 2884 signal = &bp->signal[i]; 2885 2886 count = sysfs_emit(buf, "%llu %d %llu %d", signal->period, 2887 signal->duty, signal->phase, signal->polarity); 2888 2889 ts = ktime_to_timespec64(signal->start); 2890 count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts); 2891 2892 return count; 2893 } 2894 static EXT_ATTR_RW(signal, signal, 0); 2895 static EXT_ATTR_RW(signal, signal, 1); 2896 static EXT_ATTR_RW(signal, signal, 2); 2897 static EXT_ATTR_RW(signal, signal, 3); 2898 2899 static ssize_t 2900 duty_show(struct device *dev, struct device_attribute *attr, char *buf) 2901 { 2902 struct dev_ext_attribute *ea = to_ext_attr(attr); 2903 struct ptp_ocp *bp = dev_get_drvdata(dev); 2904 int i = (uintptr_t)ea->var; 2905 2906 return sysfs_emit(buf, "%d\n", bp->signal[i].duty); 2907 } 2908 static EXT_ATTR_RO(signal, duty, 0); 2909 static EXT_ATTR_RO(signal, duty, 1); 2910 static EXT_ATTR_RO(signal, duty, 2); 2911 static EXT_ATTR_RO(signal, duty, 3); 2912 2913 static ssize_t 2914 period_show(struct device *dev, struct device_attribute *attr, char *buf) 2915 { 2916 struct dev_ext_attribute *ea = to_ext_attr(attr); 2917 struct ptp_ocp *bp = dev_get_drvdata(dev); 2918 int i = (uintptr_t)ea->var; 2919 2920 return sysfs_emit(buf, "%llu\n", bp->signal[i].period); 2921 } 2922 static EXT_ATTR_RO(signal, period, 0); 2923 static EXT_ATTR_RO(signal, period, 1); 2924 static EXT_ATTR_RO(signal, period, 2); 2925 static EXT_ATTR_RO(signal, period, 3); 2926 2927 static ssize_t 2928 phase_show(struct device *dev, struct device_attribute *attr, char *buf) 2929 { 2930 struct dev_ext_attribute *ea = to_ext_attr(attr); 2931 struct ptp_ocp *bp = dev_get_drvdata(dev); 2932 int i = (uintptr_t)ea->var; 2933 2934 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase); 2935 } 2936 static EXT_ATTR_RO(signal, phase, 0); 2937 static EXT_ATTR_RO(signal, phase, 1); 2938 static EXT_ATTR_RO(signal, phase, 2); 2939 static EXT_ATTR_RO(signal, phase, 3); 2940 2941 static ssize_t 2942 polarity_show(struct device *dev, struct device_attribute *attr, 2943 char *buf) 2944 { 2945 struct dev_ext_attribute *ea = to_ext_attr(attr); 2946 struct ptp_ocp *bp = dev_get_drvdata(dev); 2947 int i = (uintptr_t)ea->var; 2948 2949 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity); 2950 } 2951 static EXT_ATTR_RO(signal, polarity, 0); 2952 static EXT_ATTR_RO(signal, polarity, 1); 2953 static EXT_ATTR_RO(signal, polarity, 2); 2954 static EXT_ATTR_RO(signal, polarity, 3); 2955 2956 static ssize_t 2957 running_show(struct device *dev, struct device_attribute *attr, char *buf) 2958 { 2959 struct dev_ext_attribute *ea = to_ext_attr(attr); 2960 struct ptp_ocp *bp = dev_get_drvdata(dev); 2961 int i = (uintptr_t)ea->var; 2962 2963 return sysfs_emit(buf, "%d\n", bp->signal[i].running); 2964 } 2965 static EXT_ATTR_RO(signal, running, 0); 2966 static EXT_ATTR_RO(signal, running, 1); 2967 static EXT_ATTR_RO(signal, running, 2); 2968 static EXT_ATTR_RO(signal, running, 3); 2969 2970 static ssize_t 2971 start_show(struct device *dev, struct device_attribute *attr, char *buf) 2972 { 2973 struct dev_ext_attribute *ea = to_ext_attr(attr); 2974 struct ptp_ocp *bp = dev_get_drvdata(dev); 2975 int i = (uintptr_t)ea->var; 2976 struct timespec64 ts; 2977 2978 ts = ktime_to_timespec64(bp->signal[i].start); 2979 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec); 2980 } 2981 static EXT_ATTR_RO(signal, start, 0); 2982 static EXT_ATTR_RO(signal, start, 1); 2983 static EXT_ATTR_RO(signal, start, 2); 2984 static EXT_ATTR_RO(signal, start, 3); 2985 2986 static ssize_t 2987 seconds_store(struct device *dev, struct device_attribute *attr, 2988 const char *buf, size_t count) 2989 { 2990 struct dev_ext_attribute *ea = to_ext_attr(attr); 2991 struct ptp_ocp *bp = dev_get_drvdata(dev); 2992 int idx = (uintptr_t)ea->var; 2993 u32 val; 2994 int err; 2995 2996 err = kstrtou32(buf, 0, &val); 2997 if (err) 2998 return err; 2999 if (val > 0xff) 3000 return -EINVAL; 3001 3002 if (val) 3003 val = (val << 8) | 0x1; 3004 3005 iowrite32(val, &bp->freq_in[idx]->ctrl); 3006 3007 return count; 3008 } 3009 3010 static ssize_t 3011 seconds_show(struct device *dev, struct device_attribute *attr, char *buf) 3012 { 3013 struct dev_ext_attribute *ea = to_ext_attr(attr); 3014 struct ptp_ocp *bp = dev_get_drvdata(dev); 3015 int idx = (uintptr_t)ea->var; 3016 u32 val; 3017 3018 val = ioread32(&bp->freq_in[idx]->ctrl); 3019 if (val & 1) 3020 val = (val >> 8) & 0xff; 3021 else 3022 val = 0; 3023 3024 return sysfs_emit(buf, "%u\n", val); 3025 } 3026 static EXT_ATTR_RW(freq, seconds, 0); 3027 static EXT_ATTR_RW(freq, seconds, 1); 3028 static EXT_ATTR_RW(freq, seconds, 2); 3029 static EXT_ATTR_RW(freq, seconds, 3); 3030 3031 static ssize_t 3032 frequency_show(struct device *dev, struct device_attribute *attr, char *buf) 3033 { 3034 struct dev_ext_attribute *ea = to_ext_attr(attr); 3035 struct ptp_ocp *bp = dev_get_drvdata(dev); 3036 int idx = (uintptr_t)ea->var; 3037 u32 val; 3038 3039 val = ioread32(&bp->freq_in[idx]->status); 3040 if (val & FREQ_STATUS_ERROR) 3041 return sysfs_emit(buf, "error\n"); 3042 if (val & FREQ_STATUS_OVERRUN) 3043 return sysfs_emit(buf, "overrun\n"); 3044 if (val & FREQ_STATUS_VALID) 3045 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK); 3046 return 0; 3047 } 3048 static EXT_ATTR_RO(freq, frequency, 0); 3049 static EXT_ATTR_RO(freq, frequency, 1); 3050 static EXT_ATTR_RO(freq, frequency, 2); 3051 static EXT_ATTR_RO(freq, frequency, 3); 3052 3053 static ssize_t 3054 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf) 3055 { 3056 struct ptp_ocp *bp = dev_get_drvdata(dev); 3057 3058 if (!bp->has_eeprom_data) 3059 ptp_ocp_read_eeprom(bp); 3060 3061 return sysfs_emit(buf, "%pM\n", bp->serial); 3062 } 3063 static DEVICE_ATTR_RO(serialnum); 3064 3065 static ssize_t 3066 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf) 3067 { 3068 struct ptp_ocp *bp = dev_get_drvdata(dev); 3069 ssize_t ret; 3070 3071 if (bp->gnss_lost) 3072 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost); 3073 else 3074 ret = sysfs_emit(buf, "SYNC\n"); 3075 3076 return ret; 3077 } 3078 static DEVICE_ATTR_RO(gnss_sync); 3079 3080 static ssize_t 3081 utc_tai_offset_show(struct device *dev, 3082 struct device_attribute *attr, char *buf) 3083 { 3084 struct ptp_ocp *bp = dev_get_drvdata(dev); 3085 3086 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset); 3087 } 3088 3089 static ssize_t 3090 utc_tai_offset_store(struct device *dev, 3091 struct device_attribute *attr, 3092 const char *buf, size_t count) 3093 { 3094 struct ptp_ocp *bp = dev_get_drvdata(dev); 3095 int err; 3096 u32 val; 3097 3098 err = kstrtou32(buf, 0, &val); 3099 if (err) 3100 return err; 3101 3102 ptp_ocp_utc_distribute(bp, val); 3103 3104 return count; 3105 } 3106 static DEVICE_ATTR_RW(utc_tai_offset); 3107 3108 static ssize_t 3109 ts_window_adjust_show(struct device *dev, 3110 struct device_attribute *attr, char *buf) 3111 { 3112 struct ptp_ocp *bp = dev_get_drvdata(dev); 3113 3114 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust); 3115 } 3116 3117 static ssize_t 3118 ts_window_adjust_store(struct device *dev, 3119 struct device_attribute *attr, 3120 const char *buf, size_t count) 3121 { 3122 struct ptp_ocp *bp = dev_get_drvdata(dev); 3123 int err; 3124 u32 val; 3125 3126 err = kstrtou32(buf, 0, &val); 3127 if (err) 3128 return err; 3129 3130 bp->ts_window_adjust = val; 3131 3132 return count; 3133 } 3134 static DEVICE_ATTR_RW(ts_window_adjust); 3135 3136 static ssize_t 3137 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 3138 { 3139 struct ptp_ocp *bp = dev_get_drvdata(dev); 3140 u32 val; 3141 3142 val = ioread32(&bp->irig_out->ctrl); 3143 val = (val >> 16) & 0x07; 3144 return sysfs_emit(buf, "%d\n", val); 3145 } 3146 3147 static ssize_t 3148 irig_b_mode_store(struct device *dev, 3149 struct device_attribute *attr, 3150 const char *buf, size_t count) 3151 { 3152 struct ptp_ocp *bp = dev_get_drvdata(dev); 3153 unsigned long flags; 3154 int err; 3155 u32 reg; 3156 u8 val; 3157 3158 err = kstrtou8(buf, 0, &val); 3159 if (err) 3160 return err; 3161 if (val > 7) 3162 return -EINVAL; 3163 3164 reg = ((val & 0x7) << 16); 3165 3166 spin_lock_irqsave(&bp->lock, flags); 3167 iowrite32(0, &bp->irig_out->ctrl); /* disable */ 3168 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */ 3169 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl); 3170 spin_unlock_irqrestore(&bp->lock, flags); 3171 3172 return count; 3173 } 3174 static DEVICE_ATTR_RW(irig_b_mode); 3175 3176 static ssize_t 3177 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf) 3178 { 3179 struct ptp_ocp *bp = dev_get_drvdata(dev); 3180 const char *p; 3181 u32 select; 3182 3183 select = ioread32(&bp->reg->select); 3184 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16); 3185 3186 return sysfs_emit(buf, "%s\n", p); 3187 } 3188 3189 static ssize_t 3190 clock_source_store(struct device *dev, struct device_attribute *attr, 3191 const char *buf, size_t count) 3192 { 3193 struct ptp_ocp *bp = dev_get_drvdata(dev); 3194 unsigned long flags; 3195 int val; 3196 3197 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf); 3198 if (val < 0) 3199 return val; 3200 3201 spin_lock_irqsave(&bp->lock, flags); 3202 iowrite32(val, &bp->reg->select); 3203 spin_unlock_irqrestore(&bp->lock, flags); 3204 3205 return count; 3206 } 3207 static DEVICE_ATTR_RW(clock_source); 3208 3209 static ssize_t 3210 available_clock_sources_show(struct device *dev, 3211 struct device_attribute *attr, char *buf) 3212 { 3213 return ptp_ocp_select_table_show(ptp_ocp_clock, buf); 3214 } 3215 static DEVICE_ATTR_RO(available_clock_sources); 3216 3217 static ssize_t 3218 clock_status_drift_show(struct device *dev, 3219 struct device_attribute *attr, char *buf) 3220 { 3221 struct ptp_ocp *bp = dev_get_drvdata(dev); 3222 u32 val; 3223 int res; 3224 3225 val = ioread32(&bp->reg->status_drift); 3226 res = (val & ~INT_MAX) ? -1 : 1; 3227 res *= (val & INT_MAX); 3228 return sysfs_emit(buf, "%d\n", res); 3229 } 3230 static DEVICE_ATTR_RO(clock_status_drift); 3231 3232 static ssize_t 3233 clock_status_offset_show(struct device *dev, 3234 struct device_attribute *attr, char *buf) 3235 { 3236 struct ptp_ocp *bp = dev_get_drvdata(dev); 3237 u32 val; 3238 int res; 3239 3240 val = ioread32(&bp->reg->status_offset); 3241 res = (val & ~INT_MAX) ? -1 : 1; 3242 res *= (val & INT_MAX); 3243 return sysfs_emit(buf, "%d\n", res); 3244 } 3245 static DEVICE_ATTR_RO(clock_status_offset); 3246 3247 static ssize_t 3248 tod_correction_show(struct device *dev, 3249 struct device_attribute *attr, char *buf) 3250 { 3251 struct ptp_ocp *bp = dev_get_drvdata(dev); 3252 u32 val; 3253 int res; 3254 3255 val = ioread32(&bp->tod->adj_sec); 3256 res = (val & ~INT_MAX) ? -1 : 1; 3257 res *= (val & INT_MAX); 3258 return sysfs_emit(buf, "%d\n", res); 3259 } 3260 3261 static ssize_t 3262 tod_correction_store(struct device *dev, struct device_attribute *attr, 3263 const char *buf, size_t count) 3264 { 3265 struct ptp_ocp *bp = dev_get_drvdata(dev); 3266 unsigned long flags; 3267 int err, res; 3268 u32 val = 0; 3269 3270 err = kstrtos32(buf, 0, &res); 3271 if (err) 3272 return err; 3273 if (res < 0) { 3274 res *= -1; 3275 val |= BIT(31); 3276 } 3277 val |= res; 3278 3279 spin_lock_irqsave(&bp->lock, flags); 3280 iowrite32(val, &bp->tod->adj_sec); 3281 spin_unlock_irqrestore(&bp->lock, flags); 3282 3283 return count; 3284 } 3285 static DEVICE_ATTR_RW(tod_correction); 3286 3287 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \ 3288 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \ 3289 &dev_attr_signal##_nr##_signal.attr.attr, \ 3290 &dev_attr_signal##_nr##_duty.attr.attr, \ 3291 &dev_attr_signal##_nr##_phase.attr.attr, \ 3292 &dev_attr_signal##_nr##_period.attr.attr, \ 3293 &dev_attr_signal##_nr##_polarity.attr.attr, \ 3294 &dev_attr_signal##_nr##_running.attr.attr, \ 3295 &dev_attr_signal##_nr##_start.attr.attr, \ 3296 NULL, \ 3297 } 3298 3299 #define DEVICE_SIGNAL_GROUP(_name, _nr) \ 3300 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \ 3301 static const struct attribute_group \ 3302 fb_timecard_signal##_nr##_group = { \ 3303 .name = #_name, \ 3304 .attrs = fb_timecard_signal##_nr##_attrs, \ 3305 } 3306 3307 DEVICE_SIGNAL_GROUP(gen1, 0); 3308 DEVICE_SIGNAL_GROUP(gen2, 1); 3309 DEVICE_SIGNAL_GROUP(gen3, 2); 3310 DEVICE_SIGNAL_GROUP(gen4, 3); 3311 3312 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \ 3313 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \ 3314 &dev_attr_freq##_nr##_seconds.attr.attr, \ 3315 &dev_attr_freq##_nr##_frequency.attr.attr, \ 3316 NULL, \ 3317 } 3318 3319 #define DEVICE_FREQ_GROUP(_name, _nr) \ 3320 _DEVICE_FREQ_GROUP_ATTRS(_nr); \ 3321 static const struct attribute_group \ 3322 fb_timecard_freq##_nr##_group = { \ 3323 .name = #_name, \ 3324 .attrs = fb_timecard_freq##_nr##_attrs, \ 3325 } 3326 3327 DEVICE_FREQ_GROUP(freq1, 0); 3328 DEVICE_FREQ_GROUP(freq2, 1); 3329 DEVICE_FREQ_GROUP(freq3, 2); 3330 DEVICE_FREQ_GROUP(freq4, 3); 3331 3332 static ssize_t 3333 disciplining_config_read(struct file *filp, struct kobject *kobj, 3334 struct bin_attribute *bin_attr, char *buf, 3335 loff_t off, size_t count) 3336 { 3337 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj)); 3338 size_t size = OCP_ART_CONFIG_SIZE; 3339 struct nvmem_device *nvmem; 3340 ssize_t err; 3341 3342 nvmem = ptp_ocp_nvmem_device_get(bp, NULL); 3343 if (IS_ERR(nvmem)) 3344 return PTR_ERR(nvmem); 3345 3346 if (off > size) { 3347 err = 0; 3348 goto out; 3349 } 3350 3351 if (off + count > size) 3352 count = size - off; 3353 3354 // the configuration is in the very beginning of the EEPROM 3355 err = nvmem_device_read(nvmem, off, count, buf); 3356 if (err != count) { 3357 err = -EFAULT; 3358 goto out; 3359 } 3360 3361 out: 3362 ptp_ocp_nvmem_device_put(&nvmem); 3363 3364 return err; 3365 } 3366 3367 static ssize_t 3368 disciplining_config_write(struct file *filp, struct kobject *kobj, 3369 struct bin_attribute *bin_attr, char *buf, 3370 loff_t off, size_t count) 3371 { 3372 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj)); 3373 struct nvmem_device *nvmem; 3374 ssize_t err; 3375 3376 /* Allow write of the whole area only */ 3377 if (off || count != OCP_ART_CONFIG_SIZE) 3378 return -EFAULT; 3379 3380 nvmem = ptp_ocp_nvmem_device_get(bp, NULL); 3381 if (IS_ERR(nvmem)) 3382 return PTR_ERR(nvmem); 3383 3384 err = nvmem_device_write(nvmem, 0x00, count, buf); 3385 if (err != count) 3386 err = -EFAULT; 3387 3388 ptp_ocp_nvmem_device_put(&nvmem); 3389 3390 return err; 3391 } 3392 static BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE); 3393 3394 static ssize_t 3395 temperature_table_read(struct file *filp, struct kobject *kobj, 3396 struct bin_attribute *bin_attr, char *buf, 3397 loff_t off, size_t count) 3398 { 3399 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj)); 3400 size_t size = OCP_ART_TEMP_TABLE_SIZE; 3401 struct nvmem_device *nvmem; 3402 ssize_t err; 3403 3404 nvmem = ptp_ocp_nvmem_device_get(bp, NULL); 3405 if (IS_ERR(nvmem)) 3406 return PTR_ERR(nvmem); 3407 3408 if (off > size) { 3409 err = 0; 3410 goto out; 3411 } 3412 3413 if (off + count > size) 3414 count = size - off; 3415 3416 // the configuration is in the very beginning of the EEPROM 3417 err = nvmem_device_read(nvmem, 0x90 + off, count, buf); 3418 if (err != count) { 3419 err = -EFAULT; 3420 goto out; 3421 } 3422 3423 out: 3424 ptp_ocp_nvmem_device_put(&nvmem); 3425 3426 return err; 3427 } 3428 3429 static ssize_t 3430 temperature_table_write(struct file *filp, struct kobject *kobj, 3431 struct bin_attribute *bin_attr, char *buf, 3432 loff_t off, size_t count) 3433 { 3434 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj)); 3435 struct nvmem_device *nvmem; 3436 ssize_t err; 3437 3438 /* Allow write of the whole area only */ 3439 if (off || count != OCP_ART_TEMP_TABLE_SIZE) 3440 return -EFAULT; 3441 3442 nvmem = ptp_ocp_nvmem_device_get(bp, NULL); 3443 if (IS_ERR(nvmem)) 3444 return PTR_ERR(nvmem); 3445 3446 err = nvmem_device_write(nvmem, 0x90, count, buf); 3447 if (err != count) 3448 err = -EFAULT; 3449 3450 ptp_ocp_nvmem_device_put(&nvmem); 3451 3452 return err; 3453 } 3454 static BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE); 3455 3456 static struct attribute *fb_timecard_attrs[] = { 3457 &dev_attr_serialnum.attr, 3458 &dev_attr_gnss_sync.attr, 3459 &dev_attr_clock_source.attr, 3460 &dev_attr_available_clock_sources.attr, 3461 &dev_attr_sma1.attr, 3462 &dev_attr_sma2.attr, 3463 &dev_attr_sma3.attr, 3464 &dev_attr_sma4.attr, 3465 &dev_attr_available_sma_inputs.attr, 3466 &dev_attr_available_sma_outputs.attr, 3467 &dev_attr_clock_status_drift.attr, 3468 &dev_attr_clock_status_offset.attr, 3469 &dev_attr_irig_b_mode.attr, 3470 &dev_attr_utc_tai_offset.attr, 3471 &dev_attr_ts_window_adjust.attr, 3472 &dev_attr_tod_correction.attr, 3473 NULL, 3474 }; 3475 3476 static const struct attribute_group fb_timecard_group = { 3477 .attrs = fb_timecard_attrs, 3478 }; 3479 3480 static const struct ocp_attr_group fb_timecard_groups[] = { 3481 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group }, 3482 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group }, 3483 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group }, 3484 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group }, 3485 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group }, 3486 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group }, 3487 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group }, 3488 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group }, 3489 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group }, 3490 { }, 3491 }; 3492 3493 static struct attribute *art_timecard_attrs[] = { 3494 &dev_attr_serialnum.attr, 3495 &dev_attr_clock_source.attr, 3496 &dev_attr_available_clock_sources.attr, 3497 &dev_attr_utc_tai_offset.attr, 3498 &dev_attr_ts_window_adjust.attr, 3499 &dev_attr_sma1.attr, 3500 &dev_attr_sma2.attr, 3501 &dev_attr_sma3.attr, 3502 &dev_attr_sma4.attr, 3503 &dev_attr_available_sma_inputs.attr, 3504 &dev_attr_available_sma_outputs.attr, 3505 NULL, 3506 }; 3507 3508 static struct bin_attribute *bin_art_timecard_attrs[] = { 3509 &bin_attr_disciplining_config, 3510 &bin_attr_temperature_table, 3511 NULL, 3512 }; 3513 3514 static const struct attribute_group art_timecard_group = { 3515 .attrs = art_timecard_attrs, 3516 .bin_attrs = bin_art_timecard_attrs, 3517 }; 3518 3519 static const struct ocp_attr_group art_timecard_groups[] = { 3520 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group }, 3521 { }, 3522 }; 3523 3524 static void 3525 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit, 3526 const char *def) 3527 { 3528 int i; 3529 3530 for (i = 0; i < 4; i++) { 3531 if (bp->sma[i].mode != SMA_MODE_IN) 3532 continue; 3533 if (map[i][0] & (1 << bit)) { 3534 sprintf(buf, "sma%d", i + 1); 3535 return; 3536 } 3537 } 3538 if (!def) 3539 def = "----"; 3540 strcpy(buf, def); 3541 } 3542 3543 static void 3544 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit) 3545 { 3546 char *ans = buf; 3547 int i; 3548 3549 strcpy(ans, "----"); 3550 for (i = 0; i < 4; i++) { 3551 if (bp->sma[i].mode != SMA_MODE_OUT) 3552 continue; 3553 if (map[i][1] & (1 << bit)) 3554 ans += sprintf(ans, "sma%d ", i + 1); 3555 } 3556 } 3557 3558 static void 3559 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr) 3560 { 3561 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem; 3562 struct ptp_ocp_signal *signal = &bp->signal[nr]; 3563 char label[8]; 3564 bool on; 3565 u32 val; 3566 3567 if (!signal) 3568 return; 3569 3570 on = signal->running; 3571 sprintf(label, "GEN%d", nr + 1); 3572 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d", 3573 label, on ? " ON" : "OFF", 3574 signal->period, signal->duty, signal->phase, 3575 signal->polarity); 3576 3577 val = ioread32(®->enable); 3578 seq_printf(s, " [%x", val); 3579 val = ioread32(®->status); 3580 seq_printf(s, " %x]", val); 3581 3582 seq_printf(s, " start:%llu\n", signal->start); 3583 } 3584 3585 static void 3586 _frequency_summary_show(struct seq_file *s, int nr, 3587 struct frequency_reg __iomem *reg) 3588 { 3589 char label[8]; 3590 bool on; 3591 u32 val; 3592 3593 if (!reg) 3594 return; 3595 3596 sprintf(label, "FREQ%d", nr + 1); 3597 val = ioread32(®->ctrl); 3598 on = val & 1; 3599 val = (val >> 8) & 0xff; 3600 seq_printf(s, "%7s: %s, sec:%u", 3601 label, 3602 on ? " ON" : "OFF", 3603 val); 3604 3605 val = ioread32(®->status); 3606 if (val & FREQ_STATUS_ERROR) 3607 seq_printf(s, ", error"); 3608 if (val & FREQ_STATUS_OVERRUN) 3609 seq_printf(s, ", overrun"); 3610 if (val & FREQ_STATUS_VALID) 3611 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK); 3612 seq_printf(s, " reg:%x\n", val); 3613 } 3614 3615 static int 3616 ptp_ocp_summary_show(struct seq_file *s, void *data) 3617 { 3618 struct device *dev = s->private; 3619 struct ptp_system_timestamp sts; 3620 struct ts_reg __iomem *ts_reg; 3621 char *buf, *src, *mac_src; 3622 struct timespec64 ts; 3623 struct ptp_ocp *bp; 3624 u16 sma_val[4][2]; 3625 u32 ctrl, val; 3626 bool on, map; 3627 int i; 3628 3629 buf = (char *)__get_free_page(GFP_KERNEL); 3630 if (!buf) 3631 return -ENOMEM; 3632 3633 bp = dev_get_drvdata(dev); 3634 3635 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp)); 3636 if (bp->gnss_port.line != -1) 3637 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS1", 3638 bp->gnss_port.line); 3639 if (bp->gnss2_port.line != -1) 3640 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS2", 3641 bp->gnss2_port.line); 3642 if (bp->mac_port.line != -1) 3643 seq_printf(s, "%7s: /dev/ttyS%d\n", "MAC", bp->mac_port.line); 3644 if (bp->nmea_port.line != -1) 3645 seq_printf(s, "%7s: /dev/ttyS%d\n", "NMEA", bp->nmea_port.line); 3646 3647 memset(sma_val, 0xff, sizeof(sma_val)); 3648 if (bp->sma_map1) { 3649 u32 reg; 3650 3651 reg = ioread32(&bp->sma_map1->gpio1); 3652 sma_val[0][0] = reg & 0xffff; 3653 sma_val[1][0] = reg >> 16; 3654 3655 reg = ioread32(&bp->sma_map1->gpio2); 3656 sma_val[2][1] = reg & 0xffff; 3657 sma_val[3][1] = reg >> 16; 3658 3659 reg = ioread32(&bp->sma_map2->gpio1); 3660 sma_val[2][0] = reg & 0xffff; 3661 sma_val[3][0] = reg >> 16; 3662 3663 reg = ioread32(&bp->sma_map2->gpio2); 3664 sma_val[0][1] = reg & 0xffff; 3665 sma_val[1][1] = reg >> 16; 3666 } 3667 3668 sma1_show(dev, NULL, buf); 3669 seq_printf(s, " sma1: %04x,%04x %s", 3670 sma_val[0][0], sma_val[0][1], buf); 3671 3672 sma2_show(dev, NULL, buf); 3673 seq_printf(s, " sma2: %04x,%04x %s", 3674 sma_val[1][0], sma_val[1][1], buf); 3675 3676 sma3_show(dev, NULL, buf); 3677 seq_printf(s, " sma3: %04x,%04x %s", 3678 sma_val[2][0], sma_val[2][1], buf); 3679 3680 sma4_show(dev, NULL, buf); 3681 seq_printf(s, " sma4: %04x,%04x %s", 3682 sma_val[3][0], sma_val[3][1], buf); 3683 3684 if (bp->ts0) { 3685 ts_reg = bp->ts0->mem; 3686 on = ioread32(&ts_reg->enable); 3687 src = "GNSS1"; 3688 seq_printf(s, "%7s: %s, src: %s\n", "TS0", 3689 on ? " ON" : "OFF", src); 3690 } 3691 3692 if (bp->ts1) { 3693 ts_reg = bp->ts1->mem; 3694 on = ioread32(&ts_reg->enable); 3695 gpio_input_map(buf, bp, sma_val, 2, NULL); 3696 seq_printf(s, "%7s: %s, src: %s\n", "TS1", 3697 on ? " ON" : "OFF", buf); 3698 } 3699 3700 if (bp->ts2) { 3701 ts_reg = bp->ts2->mem; 3702 on = ioread32(&ts_reg->enable); 3703 gpio_input_map(buf, bp, sma_val, 3, NULL); 3704 seq_printf(s, "%7s: %s, src: %s\n", "TS2", 3705 on ? " ON" : "OFF", buf); 3706 } 3707 3708 if (bp->ts3) { 3709 ts_reg = bp->ts3->mem; 3710 on = ioread32(&ts_reg->enable); 3711 gpio_input_map(buf, bp, sma_val, 6, NULL); 3712 seq_printf(s, "%7s: %s, src: %s\n", "TS3", 3713 on ? " ON" : "OFF", buf); 3714 } 3715 3716 if (bp->ts4) { 3717 ts_reg = bp->ts4->mem; 3718 on = ioread32(&ts_reg->enable); 3719 gpio_input_map(buf, bp, sma_val, 7, NULL); 3720 seq_printf(s, "%7s: %s, src: %s\n", "TS4", 3721 on ? " ON" : "OFF", buf); 3722 } 3723 3724 if (bp->pps) { 3725 ts_reg = bp->pps->mem; 3726 src = "PHC"; 3727 on = ioread32(&ts_reg->enable); 3728 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP); 3729 seq_printf(s, "%7s: %s, src: %s\n", "TS5", 3730 on && map ? " ON" : "OFF", src); 3731 3732 map = !!(bp->pps_req_map & OCP_REQ_PPS); 3733 seq_printf(s, "%7s: %s, src: %s\n", "PPS", 3734 on && map ? " ON" : "OFF", src); 3735 } 3736 3737 if (bp->fw_cap & OCP_CAP_SIGNAL) 3738 for (i = 0; i < 4; i++) 3739 _signal_summary_show(s, bp, i); 3740 3741 if (bp->fw_cap & OCP_CAP_FREQ) 3742 for (i = 0; i < 4; i++) 3743 _frequency_summary_show(s, i, bp->freq_in[i]); 3744 3745 if (bp->irig_out) { 3746 ctrl = ioread32(&bp->irig_out->ctrl); 3747 on = ctrl & IRIG_M_CTRL_ENABLE; 3748 val = ioread32(&bp->irig_out->status); 3749 gpio_output_map(buf, bp, sma_val, 4); 3750 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG", 3751 on ? " ON" : "OFF", val, (ctrl >> 16), buf); 3752 } 3753 3754 if (bp->irig_in) { 3755 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE; 3756 val = ioread32(&bp->irig_in->status); 3757 gpio_input_map(buf, bp, sma_val, 4, NULL); 3758 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in", 3759 on ? " ON" : "OFF", val, buf); 3760 } 3761 3762 if (bp->dcf_out) { 3763 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE; 3764 val = ioread32(&bp->dcf_out->status); 3765 gpio_output_map(buf, bp, sma_val, 5); 3766 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF", 3767 on ? " ON" : "OFF", val, buf); 3768 } 3769 3770 if (bp->dcf_in) { 3771 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE; 3772 val = ioread32(&bp->dcf_in->status); 3773 gpio_input_map(buf, bp, sma_val, 5, NULL); 3774 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in", 3775 on ? " ON" : "OFF", val, buf); 3776 } 3777 3778 if (bp->nmea_out) { 3779 on = ioread32(&bp->nmea_out->ctrl) & 1; 3780 val = ioread32(&bp->nmea_out->status); 3781 seq_printf(s, "%7s: %s, error: %d\n", "NMEA", 3782 on ? " ON" : "OFF", val); 3783 } 3784 3785 /* compute src for PPS1, used below. */ 3786 if (bp->pps_select) { 3787 val = ioread32(&bp->pps_select->gpio1); 3788 src = &buf[80]; 3789 mac_src = "GNSS1"; 3790 if (val & 0x01) { 3791 gpio_input_map(src, bp, sma_val, 0, NULL); 3792 mac_src = src; 3793 } else if (val & 0x02) { 3794 src = "MAC"; 3795 } else if (val & 0x04) { 3796 src = "GNSS1"; 3797 } else { 3798 src = "----"; 3799 mac_src = src; 3800 } 3801 } else { 3802 src = "?"; 3803 mac_src = src; 3804 } 3805 seq_printf(s, "MAC PPS1 src: %s\n", mac_src); 3806 3807 gpio_input_map(buf, bp, sma_val, 1, "GNSS2"); 3808 seq_printf(s, "MAC PPS2 src: %s\n", buf); 3809 3810 /* assumes automatic switchover/selection */ 3811 val = ioread32(&bp->reg->select); 3812 switch (val >> 16) { 3813 case 0: 3814 sprintf(buf, "----"); 3815 break; 3816 case 2: 3817 sprintf(buf, "IRIG"); 3818 break; 3819 case 3: 3820 sprintf(buf, "%s via PPS1", src); 3821 break; 3822 case 6: 3823 sprintf(buf, "DCF"); 3824 break; 3825 default: 3826 strcpy(buf, "unknown"); 3827 break; 3828 } 3829 val = ioread32(&bp->reg->status); 3830 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf, 3831 val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced"); 3832 3833 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) { 3834 struct timespec64 sys_ts; 3835 s64 pre_ns, post_ns, ns; 3836 3837 pre_ns = timespec64_to_ns(&sts.pre_ts); 3838 post_ns = timespec64_to_ns(&sts.post_ts); 3839 ns = (pre_ns + post_ns) / 2; 3840 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC; 3841 sys_ts = ns_to_timespec64(ns); 3842 3843 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC", 3844 ts.tv_sec, ts.tv_nsec, &ts); 3845 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS", 3846 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts, 3847 bp->utc_tai_offset); 3848 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "", 3849 timespec64_to_ns(&ts) - ns, 3850 post_ns - pre_ns); 3851 } 3852 3853 free_page((unsigned long)buf); 3854 return 0; 3855 } 3856 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary); 3857 3858 static int 3859 ptp_ocp_tod_status_show(struct seq_file *s, void *data) 3860 { 3861 struct device *dev = s->private; 3862 struct ptp_ocp *bp; 3863 u32 val; 3864 int idx; 3865 3866 bp = dev_get_drvdata(dev); 3867 3868 val = ioread32(&bp->tod->ctrl); 3869 if (!(val & TOD_CTRL_ENABLE)) { 3870 seq_printf(s, "TOD Slave disabled\n"); 3871 return 0; 3872 } 3873 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val); 3874 3875 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0; 3876 idx += (val >> 16) & 3; 3877 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx)); 3878 3879 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK; 3880 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx)); 3881 3882 val = ioread32(&bp->tod->version); 3883 seq_printf(s, "TOD Version %d.%d.%d\n", 3884 val >> 24, (val >> 16) & 0xff, val & 0xffff); 3885 3886 val = ioread32(&bp->tod->status); 3887 seq_printf(s, "Status register: 0x%08X\n", val); 3888 3889 val = ioread32(&bp->tod->adj_sec); 3890 idx = (val & ~INT_MAX) ? -1 : 1; 3891 idx *= (val & INT_MAX); 3892 seq_printf(s, "Correction seconds: %d\n", idx); 3893 3894 val = ioread32(&bp->tod->utc_status); 3895 seq_printf(s, "UTC status register: 0x%08X\n", val); 3896 seq_printf(s, "UTC offset: %ld valid:%d\n", 3897 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0); 3898 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n", 3899 val & TOD_STATUS_LEAP_VALID ? 1 : 0, 3900 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0); 3901 3902 val = ioread32(&bp->tod->leap); 3903 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val); 3904 3905 return 0; 3906 } 3907 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status); 3908 3909 static struct dentry *ptp_ocp_debugfs_root; 3910 3911 static void 3912 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp) 3913 { 3914 struct dentry *d; 3915 3916 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root); 3917 bp->debug_root = d; 3918 debugfs_create_file("summary", 0444, bp->debug_root, 3919 &bp->dev, &ptp_ocp_summary_fops); 3920 if (bp->tod) 3921 debugfs_create_file("tod_status", 0444, bp->debug_root, 3922 &bp->dev, &ptp_ocp_tod_status_fops); 3923 } 3924 3925 static void 3926 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp) 3927 { 3928 debugfs_remove_recursive(bp->debug_root); 3929 } 3930 3931 static void 3932 ptp_ocp_debugfs_init(void) 3933 { 3934 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL); 3935 } 3936 3937 static void 3938 ptp_ocp_debugfs_fini(void) 3939 { 3940 debugfs_remove_recursive(ptp_ocp_debugfs_root); 3941 } 3942 3943 static void 3944 ptp_ocp_dev_release(struct device *dev) 3945 { 3946 struct ptp_ocp *bp = dev_get_drvdata(dev); 3947 3948 mutex_lock(&ptp_ocp_lock); 3949 idr_remove(&ptp_ocp_idr, bp->id); 3950 mutex_unlock(&ptp_ocp_lock); 3951 } 3952 3953 static int 3954 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev) 3955 { 3956 int err; 3957 3958 mutex_lock(&ptp_ocp_lock); 3959 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL); 3960 mutex_unlock(&ptp_ocp_lock); 3961 if (err < 0) { 3962 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err); 3963 return err; 3964 } 3965 bp->id = err; 3966 3967 bp->ptp_info = ptp_ocp_clock_info; 3968 spin_lock_init(&bp->lock); 3969 bp->gnss_port.line = -1; 3970 bp->gnss2_port.line = -1; 3971 bp->mac_port.line = -1; 3972 bp->nmea_port.line = -1; 3973 bp->pdev = pdev; 3974 3975 device_initialize(&bp->dev); 3976 dev_set_name(&bp->dev, "ocp%d", bp->id); 3977 bp->dev.class = &timecard_class; 3978 bp->dev.parent = &pdev->dev; 3979 bp->dev.release = ptp_ocp_dev_release; 3980 dev_set_drvdata(&bp->dev, bp); 3981 3982 err = device_add(&bp->dev); 3983 if (err) { 3984 dev_err(&bp->dev, "device add failed: %d\n", err); 3985 goto out; 3986 } 3987 3988 pci_set_drvdata(pdev, bp); 3989 3990 return 0; 3991 3992 out: 3993 ptp_ocp_dev_release(&bp->dev); 3994 put_device(&bp->dev); 3995 return err; 3996 } 3997 3998 static void 3999 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link) 4000 { 4001 struct device *dev = &bp->dev; 4002 4003 if (sysfs_create_link(&dev->kobj, &child->kobj, link)) 4004 dev_err(dev, "%s symlink failed\n", link); 4005 } 4006 4007 static void 4008 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link) 4009 { 4010 struct device *dev, *child; 4011 4012 dev = &bp->pdev->dev; 4013 4014 child = device_find_child_by_name(dev, name); 4015 if (!child) { 4016 dev_err(dev, "Could not find device %s\n", name); 4017 return; 4018 } 4019 4020 ptp_ocp_symlink(bp, child, link); 4021 put_device(child); 4022 } 4023 4024 static int 4025 ptp_ocp_complete(struct ptp_ocp *bp) 4026 { 4027 struct pps_device *pps; 4028 char buf[32]; 4029 4030 if (bp->gnss_port.line != -1) { 4031 sprintf(buf, "ttyS%d", bp->gnss_port.line); 4032 ptp_ocp_link_child(bp, buf, "ttyGNSS"); 4033 } 4034 if (bp->gnss2_port.line != -1) { 4035 sprintf(buf, "ttyS%d", bp->gnss2_port.line); 4036 ptp_ocp_link_child(bp, buf, "ttyGNSS2"); 4037 } 4038 if (bp->mac_port.line != -1) { 4039 sprintf(buf, "ttyS%d", bp->mac_port.line); 4040 ptp_ocp_link_child(bp, buf, "ttyMAC"); 4041 } 4042 if (bp->nmea_port.line != -1) { 4043 sprintf(buf, "ttyS%d", bp->nmea_port.line); 4044 ptp_ocp_link_child(bp, buf, "ttyNMEA"); 4045 } 4046 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp)); 4047 ptp_ocp_link_child(bp, buf, "ptp"); 4048 4049 pps = pps_lookup_dev(bp->ptp); 4050 if (pps) 4051 ptp_ocp_symlink(bp, pps->dev, "pps"); 4052 4053 ptp_ocp_debugfs_add_device(bp); 4054 4055 return 0; 4056 } 4057 4058 static void 4059 ptp_ocp_phc_info(struct ptp_ocp *bp) 4060 { 4061 struct timespec64 ts; 4062 u32 version, select; 4063 bool sync; 4064 4065 version = ioread32(&bp->reg->version); 4066 select = ioread32(&bp->reg->select); 4067 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n", 4068 version >> 24, (version >> 16) & 0xff, version & 0xffff, 4069 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16), 4070 ptp_clock_index(bp->ptp)); 4071 4072 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC; 4073 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL)) 4074 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n", 4075 ts.tv_sec, ts.tv_nsec, 4076 sync ? "in-sync" : "UNSYNCED"); 4077 } 4078 4079 static void 4080 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud) 4081 { 4082 if (port != -1) 4083 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud); 4084 } 4085 4086 static void 4087 ptp_ocp_info(struct ptp_ocp *bp) 4088 { 4089 static int nmea_baud[] = { 4090 1200, 2400, 4800, 9600, 19200, 38400, 4091 57600, 115200, 230400, 460800, 921600, 4092 1000000, 2000000 4093 }; 4094 struct device *dev = &bp->pdev->dev; 4095 u32 reg; 4096 4097 ptp_ocp_phc_info(bp); 4098 4099 ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port.line, 4100 bp->gnss_port.baud); 4101 ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port.line, 4102 bp->gnss2_port.baud); 4103 ptp_ocp_serial_info(dev, "MAC", bp->mac_port.line, bp->mac_port.baud); 4104 if (bp->nmea_out && bp->nmea_port.line != -1) { 4105 bp->nmea_port.baud = -1; 4106 4107 reg = ioread32(&bp->nmea_out->uart_baud); 4108 if (reg < ARRAY_SIZE(nmea_baud)) 4109 bp->nmea_port.baud = nmea_baud[reg]; 4110 4111 ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port.line, 4112 bp->nmea_port.baud); 4113 } 4114 } 4115 4116 static void 4117 ptp_ocp_detach_sysfs(struct ptp_ocp *bp) 4118 { 4119 struct device *dev = &bp->dev; 4120 4121 sysfs_remove_link(&dev->kobj, "ttyGNSS"); 4122 sysfs_remove_link(&dev->kobj, "ttyGNSS2"); 4123 sysfs_remove_link(&dev->kobj, "ttyMAC"); 4124 sysfs_remove_link(&dev->kobj, "ptp"); 4125 sysfs_remove_link(&dev->kobj, "pps"); 4126 } 4127 4128 static void 4129 ptp_ocp_detach(struct ptp_ocp *bp) 4130 { 4131 int i; 4132 4133 ptp_ocp_debugfs_remove_device(bp); 4134 ptp_ocp_detach_sysfs(bp); 4135 ptp_ocp_attr_group_del(bp); 4136 if (timer_pending(&bp->watchdog)) 4137 del_timer_sync(&bp->watchdog); 4138 if (bp->ts0) 4139 ptp_ocp_unregister_ext(bp->ts0); 4140 if (bp->ts1) 4141 ptp_ocp_unregister_ext(bp->ts1); 4142 if (bp->ts2) 4143 ptp_ocp_unregister_ext(bp->ts2); 4144 if (bp->ts3) 4145 ptp_ocp_unregister_ext(bp->ts3); 4146 if (bp->ts4) 4147 ptp_ocp_unregister_ext(bp->ts4); 4148 if (bp->pps) 4149 ptp_ocp_unregister_ext(bp->pps); 4150 for (i = 0; i < 4; i++) 4151 if (bp->signal_out[i]) 4152 ptp_ocp_unregister_ext(bp->signal_out[i]); 4153 if (bp->gnss_port.line != -1) 4154 serial8250_unregister_port(bp->gnss_port.line); 4155 if (bp->gnss2_port.line != -1) 4156 serial8250_unregister_port(bp->gnss2_port.line); 4157 if (bp->mac_port.line != -1) 4158 serial8250_unregister_port(bp->mac_port.line); 4159 if (bp->nmea_port.line != -1) 4160 serial8250_unregister_port(bp->nmea_port.line); 4161 platform_device_unregister(bp->spi_flash); 4162 platform_device_unregister(bp->i2c_ctrl); 4163 if (bp->i2c_clk) 4164 clk_hw_unregister_fixed_rate(bp->i2c_clk); 4165 if (bp->n_irqs) 4166 pci_free_irq_vectors(bp->pdev); 4167 if (bp->ptp) 4168 ptp_clock_unregister(bp->ptp); 4169 kfree(bp->ptp_info.pin_config); 4170 device_unregister(&bp->dev); 4171 } 4172 4173 static int 4174 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id) 4175 { 4176 struct devlink *devlink; 4177 struct ptp_ocp *bp; 4178 int err; 4179 4180 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev); 4181 if (!devlink) { 4182 dev_err(&pdev->dev, "devlink_alloc failed\n"); 4183 return -ENOMEM; 4184 } 4185 4186 err = pci_enable_device(pdev); 4187 if (err) { 4188 dev_err(&pdev->dev, "pci_enable_device\n"); 4189 goto out_free; 4190 } 4191 4192 bp = devlink_priv(devlink); 4193 err = ptp_ocp_device_init(bp, pdev); 4194 if (err) 4195 goto out_disable; 4196 4197 /* compat mode. 4198 * Older FPGA firmware only returns 2 irq's. 4199 * allow this - if not all of the IRQ's are returned, skip the 4200 * extra devices and just register the clock. 4201 */ 4202 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX); 4203 if (err < 0) { 4204 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err); 4205 goto out; 4206 } 4207 bp->n_irqs = err; 4208 pci_set_master(pdev); 4209 4210 err = ptp_ocp_register_resources(bp, id->driver_data); 4211 if (err) 4212 goto out; 4213 4214 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev); 4215 if (IS_ERR(bp->ptp)) { 4216 err = PTR_ERR(bp->ptp); 4217 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err); 4218 bp->ptp = NULL; 4219 goto out; 4220 } 4221 4222 err = ptp_ocp_complete(bp); 4223 if (err) 4224 goto out; 4225 4226 ptp_ocp_info(bp); 4227 devlink_register(devlink); 4228 return 0; 4229 4230 out: 4231 ptp_ocp_detach(bp); 4232 out_disable: 4233 pci_disable_device(pdev); 4234 out_free: 4235 devlink_free(devlink); 4236 return err; 4237 } 4238 4239 static void 4240 ptp_ocp_remove(struct pci_dev *pdev) 4241 { 4242 struct ptp_ocp *bp = pci_get_drvdata(pdev); 4243 struct devlink *devlink = priv_to_devlink(bp); 4244 4245 devlink_unregister(devlink); 4246 ptp_ocp_detach(bp); 4247 pci_disable_device(pdev); 4248 4249 devlink_free(devlink); 4250 } 4251 4252 static struct pci_driver ptp_ocp_driver = { 4253 .name = KBUILD_MODNAME, 4254 .id_table = ptp_ocp_pcidev_id, 4255 .probe = ptp_ocp_probe, 4256 .remove = ptp_ocp_remove, 4257 }; 4258 4259 static int 4260 ptp_ocp_i2c_notifier_call(struct notifier_block *nb, 4261 unsigned long action, void *data) 4262 { 4263 struct device *dev, *child = data; 4264 struct ptp_ocp *bp; 4265 bool add; 4266 4267 switch (action) { 4268 case BUS_NOTIFY_ADD_DEVICE: 4269 case BUS_NOTIFY_DEL_DEVICE: 4270 add = action == BUS_NOTIFY_ADD_DEVICE; 4271 break; 4272 default: 4273 return 0; 4274 } 4275 4276 if (!i2c_verify_adapter(child)) 4277 return 0; 4278 4279 dev = child; 4280 while ((dev = dev->parent)) 4281 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME)) 4282 goto found; 4283 return 0; 4284 4285 found: 4286 bp = dev_get_drvdata(dev); 4287 if (add) 4288 ptp_ocp_symlink(bp, child, "i2c"); 4289 else 4290 sysfs_remove_link(&bp->dev.kobj, "i2c"); 4291 4292 return 0; 4293 } 4294 4295 static struct notifier_block ptp_ocp_i2c_notifier = { 4296 .notifier_call = ptp_ocp_i2c_notifier_call, 4297 }; 4298 4299 static int __init 4300 ptp_ocp_init(void) 4301 { 4302 const char *what; 4303 int err; 4304 4305 ptp_ocp_debugfs_init(); 4306 4307 what = "timecard class"; 4308 err = class_register(&timecard_class); 4309 if (err) 4310 goto out; 4311 4312 what = "i2c notifier"; 4313 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 4314 if (err) 4315 goto out_notifier; 4316 4317 what = "ptp_ocp driver"; 4318 err = pci_register_driver(&ptp_ocp_driver); 4319 if (err) 4320 goto out_register; 4321 4322 return 0; 4323 4324 out_register: 4325 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 4326 out_notifier: 4327 class_unregister(&timecard_class); 4328 out: 4329 ptp_ocp_debugfs_fini(); 4330 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err); 4331 return err; 4332 } 4333 4334 static void __exit 4335 ptp_ocp_fini(void) 4336 { 4337 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 4338 pci_unregister_driver(&ptp_ocp_driver); 4339 class_unregister(&timecard_class); 4340 ptp_ocp_debugfs_fini(); 4341 } 4342 4343 module_init(ptp_ocp_init); 4344 module_exit(ptp_ocp_fini); 4345 4346 MODULE_DESCRIPTION("OpenCompute TimeCard driver"); 4347 MODULE_LICENSE("GPL v2"); 4348