1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * PTP hardware clock driver for the IDT 82P33XXX family of clocks. 4 * 5 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. 6 */ 7 #ifndef PTP_IDT82P33_H 8 #define PTP_IDT82P33_H 9 10 #include <linux/ktime.h> 11 #include <linux/workqueue.h> 12 13 14 /* Register Map - AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf */ 15 #define PAGE_NUM (8) 16 #define _ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f)) 17 #define _PAGE(addr) (((addr) >> 0x7) & 0x7) 18 #define _OFFSET(addr) ((addr) & 0x7f) 19 20 #define DPLL1_TOD_CNFG 0x134 21 #define DPLL2_TOD_CNFG 0x1B4 22 23 #define DPLL1_TOD_STS 0x10B 24 #define DPLL2_TOD_STS 0x18B 25 26 #define DPLL1_TOD_TRIGGER 0x115 27 #define DPLL2_TOD_TRIGGER 0x195 28 29 #define DPLL1_OPERATING_MODE_CNFG 0x120 30 #define DPLL2_OPERATING_MODE_CNFG 0x1A0 31 32 #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C 33 #define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC 34 35 #define DPLL1_PHASE_OFFSET_CNFG 0x143 36 #define DPLL2_PHASE_OFFSET_CNFG 0x1C3 37 38 #define DPLL1_SYNC_EDGE_CNFG 0X140 39 #define DPLL2_SYNC_EDGE_CNFG 0X1C0 40 41 #define DPLL1_INPUT_MODE_CNFG 0X116 42 #define DPLL2_INPUT_MODE_CNFG 0X196 43 44 #define OUT_MUX_CNFG(outn) _ADDR(0x6, (0xC * (outn))) 45 46 #define PAGE_ADDR 0x7F 47 /* Register Map end */ 48 49 /* Register definitions - AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf*/ 50 #define TOD_TRIGGER(wr_trig, rd_trig) ((wr_trig & 0xf) << 4 | (rd_trig & 0xf)) 51 #define SYNC_TOD BIT(1) 52 #define PH_OFFSET_EN BIT(7) 53 #define SQUELCH_ENABLE BIT(5) 54 55 /* Bit definitions for the DPLL_MODE register */ 56 #define PLL_MODE_SHIFT (0) 57 #define PLL_MODE_MASK (0x1F) 58 59 #define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef) 60 61 enum pll_mode { 62 PLL_MODE_MIN = 0, 63 PLL_MODE_AUTOMATIC = PLL_MODE_MIN, 64 PLL_MODE_FORCE_FREERUN = 1, 65 PLL_MODE_FORCE_HOLDOVER = 2, 66 PLL_MODE_FORCE_LOCKED = 4, 67 PLL_MODE_FORCE_PRE_LOCKED2 = 5, 68 PLL_MODE_FORCE_PRE_LOCKED = 6, 69 PLL_MODE_FORCE_LOST_PHASE = 7, 70 PLL_MODE_DCO = 10, 71 PLL_MODE_WPH = 18, 72 PLL_MODE_MAX = PLL_MODE_WPH, 73 }; 74 75 enum hw_tod_trig_sel { 76 HW_TOD_TRIG_SEL_MIN = 0, 77 HW_TOD_TRIG_SEL_NO_WRITE = HW_TOD_TRIG_SEL_MIN, 78 HW_TOD_TRIG_SEL_SYNC_SEL = 1, 79 HW_TOD_TRIG_SEL_IN12 = 2, 80 HW_TOD_TRIG_SEL_IN13 = 3, 81 HW_TOD_TRIG_SEL_IN14 = 4, 82 HW_TOD_TRIG_SEL_TOD_PPS = 5, 83 HW_TOD_TRIG_SEL_TIMER_INTERVAL = 6, 84 HW_TOD_TRIG_SEL_MSB_PHASE_OFFSET_CNFG = 7, 85 HW_TOD_TRIG_SEL_MSB_HOLDOVER_FREQ_CNFG = 8, 86 HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG = 9, 87 HW_TOD_RD_TRIG_SEL_LSB_TOD_STS = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG, 88 WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG, 89 }; 90 91 /* Register bit definitions end */ 92 #define FW_FILENAME "idt82p33xxx.bin" 93 #define MAX_PHC_PLL (2) 94 #define TOD_BYTE_COUNT (10) 95 #define MAX_MEASURMENT_COUNT (5) 96 #define SNAP_THRESHOLD_NS (150000) 97 #define SYNC_TOD_TIMEOUT_SEC (5) 98 #define IDT82P33_MAX_WRITE_COUNT (512) 99 100 #define PLLMASK_ADDR_HI 0xFF 101 #define PLLMASK_ADDR_LO 0xA5 102 103 #define PLL0_OUTMASK_ADDR_HI 0xFF 104 #define PLL0_OUTMASK_ADDR_LO 0xB0 105 106 #define PLL1_OUTMASK_ADDR_HI 0xFF 107 #define PLL1_OUTMASK_ADDR_LO 0xB2 108 109 #define PLL2_OUTMASK_ADDR_HI 0xFF 110 #define PLL2_OUTMASK_ADDR_LO 0xB4 111 112 #define PLL3_OUTMASK_ADDR_HI 0xFF 113 #define PLL3_OUTMASK_ADDR_LO 0xB6 114 115 #define DEFAULT_PLL_MASK (0x01) 116 #define DEFAULT_OUTPUT_MASK_PLL0 (0xc0) 117 #define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL0 118 119 /* PTP Hardware Clock interface */ 120 struct idt82p33_channel { 121 struct ptp_clock_info caps; 122 struct ptp_clock *ptp_clock; 123 struct idt82p33 *idt82p33; 124 enum pll_mode pll_mode; 125 /* task to turn off SYNC_TOD bit after pps sync */ 126 struct delayed_work sync_tod_work; 127 bool sync_tod_on; 128 s32 current_freq_ppb; 129 u8 output_mask; 130 u16 dpll_tod_cnfg; 131 u16 dpll_tod_trigger; 132 u16 dpll_tod_sts; 133 u16 dpll_mode_cnfg; 134 u16 dpll_freq_cnfg; 135 u16 dpll_phase_cnfg; 136 u16 dpll_sync_cnfg; 137 u16 dpll_input_mode_cnfg; 138 }; 139 140 struct idt82p33 { 141 struct idt82p33_channel channel[MAX_PHC_PLL]; 142 struct i2c_client *client; 143 u8 page_offset; 144 u8 pll_mask; 145 ktime_t start_time; 146 int calculate_overhead_flag; 147 s64 tod_write_overhead_ns; 148 /* Protects I2C read/modify/write registers from concurrent access */ 149 struct mutex reg_lock; 150 }; 151 152 /* firmware interface */ 153 struct idt82p33_fwrc { 154 u8 hiaddr; 155 u8 loaddr; 156 u8 value; 157 u8 reserved; 158 } __packed; 159 160 /** 161 * @brief Maximum absolute value for write phase offset in femtoseconds 162 */ 163 #define WRITE_PHASE_OFFSET_LIMIT (20000052084ll) 164 165 /** @brief Phase offset resolution 166 * 167 * DPLL phase offset = 10^15 fs / ( System Clock * 2^13) 168 * = 10^15 fs / ( 1638400000 * 2^23) 169 * = 74.5058059692382 fs 170 */ 171 #define IDT_T0DPLL_PHASE_RESOL 74506 172 173 174 #endif /* PTP_IDT82P33_H */ 175