1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright 2017 Broadcom 3 4 #include <linux/err.h> 5 #include <linux/io.h> 6 #include <linux/module.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/platform_device.h> 9 #include <linux/ptp_clock_kernel.h> 10 #include <linux/types.h> 11 12 #define DTE_NCO_LOW_TIME_REG 0x00 13 #define DTE_NCO_TIME_REG 0x04 14 #define DTE_NCO_OVERFLOW_REG 0x08 15 #define DTE_NCO_INC_REG 0x0c 16 17 #define DTE_NCO_SUM2_MASK 0xffffffff 18 #define DTE_NCO_SUM2_SHIFT 4ULL 19 20 #define DTE_NCO_SUM3_MASK 0xff 21 #define DTE_NCO_SUM3_SHIFT 36ULL 22 #define DTE_NCO_SUM3_WR_SHIFT 8 23 24 #define DTE_NCO_TS_WRAP_MASK 0xfff 25 #define DTE_NCO_TS_WRAP_LSHIFT 32 26 27 #define DTE_NCO_INC_DEFAULT 0x80000000 28 #define DTE_NUM_REGS_TO_RESTORE 4 29 30 /* Full wrap around is 44bits in ns (~4.887 hrs) */ 31 #define DTE_WRAP_AROUND_NSEC_SHIFT 44 32 33 /* 44 bits NCO */ 34 #define DTE_NCO_MAX_NS 0xFFFFFFFFFFFLL 35 36 /* 125MHz with 3.29 reg cfg */ 37 #define DTE_PPB_ADJ(ppb) (u32)(div64_u64((((u64)abs(ppb) * BIT(28)) +\ 38 62500000ULL), 125000000ULL)) 39 40 /* ptp dte priv structure */ 41 struct ptp_dte { 42 void __iomem *regs; 43 struct ptp_clock *ptp_clk; 44 struct ptp_clock_info caps; 45 struct device *dev; 46 u32 ts_ovf_last; 47 u32 ts_wrap_cnt; 48 spinlock_t lock; 49 u32 reg_val[DTE_NUM_REGS_TO_RESTORE]; 50 }; 51 52 static void dte_write_nco(void __iomem *regs, s64 ns) 53 { 54 u32 sum2, sum3; 55 56 sum2 = (u32)((ns >> DTE_NCO_SUM2_SHIFT) & DTE_NCO_SUM2_MASK); 57 /* compensate for ignoring sum1 */ 58 if (sum2 != DTE_NCO_SUM2_MASK) 59 sum2++; 60 61 /* to write sum3, bits [15:8] needs to be written */ 62 sum3 = (u32)(((ns >> DTE_NCO_SUM3_SHIFT) & DTE_NCO_SUM3_MASK) << 63 DTE_NCO_SUM3_WR_SHIFT); 64 65 writel(0, (regs + DTE_NCO_LOW_TIME_REG)); 66 writel(sum2, (regs + DTE_NCO_TIME_REG)); 67 writel(sum3, (regs + DTE_NCO_OVERFLOW_REG)); 68 } 69 70 static s64 dte_read_nco(void __iomem *regs) 71 { 72 u32 sum2, sum3; 73 s64 ns; 74 75 /* 76 * ignoring sum1 (4 bits) gives a 16ns resolution, which 77 * works due to the async register read. 78 */ 79 sum3 = readl(regs + DTE_NCO_OVERFLOW_REG) & DTE_NCO_SUM3_MASK; 80 sum2 = readl(regs + DTE_NCO_TIME_REG); 81 ns = ((s64)sum3 << DTE_NCO_SUM3_SHIFT) | 82 ((s64)sum2 << DTE_NCO_SUM2_SHIFT); 83 84 return ns; 85 } 86 87 static void dte_write_nco_delta(struct ptp_dte *ptp_dte, s64 delta) 88 { 89 s64 ns; 90 91 ns = dte_read_nco(ptp_dte->regs); 92 93 /* handle wraparound conditions */ 94 if ((delta < 0) && (abs(delta) > ns)) { 95 if (ptp_dte->ts_wrap_cnt) { 96 ns += DTE_NCO_MAX_NS + delta; 97 ptp_dte->ts_wrap_cnt--; 98 } else { 99 ns = 0; 100 } 101 } else { 102 ns += delta; 103 if (ns > DTE_NCO_MAX_NS) { 104 ptp_dte->ts_wrap_cnt++; 105 ns -= DTE_NCO_MAX_NS; 106 } 107 } 108 109 dte_write_nco(ptp_dte->regs, ns); 110 111 ptp_dte->ts_ovf_last = (ns >> DTE_NCO_TS_WRAP_LSHIFT) & 112 DTE_NCO_TS_WRAP_MASK; 113 } 114 115 static s64 dte_read_nco_with_ovf(struct ptp_dte *ptp_dte) 116 { 117 u32 ts_ovf; 118 s64 ns = 0; 119 120 ns = dte_read_nco(ptp_dte->regs); 121 122 /*Timestamp overflow: 8 LSB bits of sum3, 4 MSB bits of sum2 */ 123 ts_ovf = (ns >> DTE_NCO_TS_WRAP_LSHIFT) & DTE_NCO_TS_WRAP_MASK; 124 125 /* Check for wrap around */ 126 if (ts_ovf < ptp_dte->ts_ovf_last) 127 ptp_dte->ts_wrap_cnt++; 128 129 ptp_dte->ts_ovf_last = ts_ovf; 130 131 /* adjust for wraparounds */ 132 ns += (s64)(BIT_ULL(DTE_WRAP_AROUND_NSEC_SHIFT) * ptp_dte->ts_wrap_cnt); 133 134 return ns; 135 } 136 137 static int ptp_dte_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 138 { 139 u32 nco_incr; 140 unsigned long flags; 141 struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps); 142 143 if (abs(ppb) > ptp_dte->caps.max_adj) { 144 dev_err(ptp_dte->dev, "ppb adj too big\n"); 145 return -EINVAL; 146 } 147 148 if (ppb < 0) 149 nco_incr = DTE_NCO_INC_DEFAULT - DTE_PPB_ADJ(ppb); 150 else 151 nco_incr = DTE_NCO_INC_DEFAULT + DTE_PPB_ADJ(ppb); 152 153 spin_lock_irqsave(&ptp_dte->lock, flags); 154 writel(nco_incr, ptp_dte->regs + DTE_NCO_INC_REG); 155 spin_unlock_irqrestore(&ptp_dte->lock, flags); 156 157 return 0; 158 } 159 160 static int ptp_dte_adjtime(struct ptp_clock_info *ptp, s64 delta) 161 { 162 unsigned long flags; 163 struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps); 164 165 spin_lock_irqsave(&ptp_dte->lock, flags); 166 dte_write_nco_delta(ptp_dte, delta); 167 spin_unlock_irqrestore(&ptp_dte->lock, flags); 168 169 return 0; 170 } 171 172 static int ptp_dte_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 173 { 174 unsigned long flags; 175 struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps); 176 177 spin_lock_irqsave(&ptp_dte->lock, flags); 178 *ts = ns_to_timespec64(dte_read_nco_with_ovf(ptp_dte)); 179 spin_unlock_irqrestore(&ptp_dte->lock, flags); 180 181 return 0; 182 } 183 184 static int ptp_dte_settime(struct ptp_clock_info *ptp, 185 const struct timespec64 *ts) 186 { 187 unsigned long flags; 188 struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps); 189 190 spin_lock_irqsave(&ptp_dte->lock, flags); 191 192 /* Disable nco increment */ 193 writel(0, ptp_dte->regs + DTE_NCO_INC_REG); 194 195 dte_write_nco(ptp_dte->regs, timespec64_to_ns(ts)); 196 197 /* reset overflow and wrap counter */ 198 ptp_dte->ts_ovf_last = 0; 199 ptp_dte->ts_wrap_cnt = 0; 200 201 /* Enable nco increment */ 202 writel(DTE_NCO_INC_DEFAULT, ptp_dte->regs + DTE_NCO_INC_REG); 203 204 spin_unlock_irqrestore(&ptp_dte->lock, flags); 205 206 return 0; 207 } 208 209 static int ptp_dte_enable(struct ptp_clock_info *ptp, 210 struct ptp_clock_request *rq, int on) 211 { 212 return -EOPNOTSUPP; 213 } 214 215 static const struct ptp_clock_info ptp_dte_caps = { 216 .owner = THIS_MODULE, 217 .name = "DTE PTP timer", 218 .max_adj = 50000000, 219 .n_ext_ts = 0, 220 .n_pins = 0, 221 .pps = 0, 222 .adjfreq = ptp_dte_adjfreq, 223 .adjtime = ptp_dte_adjtime, 224 .gettime64 = ptp_dte_gettime, 225 .settime64 = ptp_dte_settime, 226 .enable = ptp_dte_enable, 227 }; 228 229 static int ptp_dte_probe(struct platform_device *pdev) 230 { 231 struct ptp_dte *ptp_dte; 232 struct device *dev = &pdev->dev; 233 234 ptp_dte = devm_kzalloc(dev, sizeof(struct ptp_dte), GFP_KERNEL); 235 if (!ptp_dte) 236 return -ENOMEM; 237 238 ptp_dte->regs = devm_platform_ioremap_resource(pdev, 0); 239 if (IS_ERR(ptp_dte->regs)) 240 return PTR_ERR(ptp_dte->regs); 241 242 spin_lock_init(&ptp_dte->lock); 243 244 ptp_dte->dev = dev; 245 ptp_dte->caps = ptp_dte_caps; 246 ptp_dte->ptp_clk = ptp_clock_register(&ptp_dte->caps, &pdev->dev); 247 if (IS_ERR(ptp_dte->ptp_clk)) { 248 dev_err(dev, 249 "%s: Failed to register ptp clock\n", __func__); 250 return PTR_ERR(ptp_dte->ptp_clk); 251 } 252 253 platform_set_drvdata(pdev, ptp_dte); 254 255 dev_info(dev, "ptp clk probe done\n"); 256 257 return 0; 258 } 259 260 static int ptp_dte_remove(struct platform_device *pdev) 261 { 262 struct ptp_dte *ptp_dte = platform_get_drvdata(pdev); 263 u8 i; 264 265 ptp_clock_unregister(ptp_dte->ptp_clk); 266 267 for (i = 0; i < DTE_NUM_REGS_TO_RESTORE; i++) 268 writel(0, ptp_dte->regs + (i * sizeof(u32))); 269 270 return 0; 271 } 272 273 #ifdef CONFIG_PM_SLEEP 274 static int ptp_dte_suspend(struct device *dev) 275 { 276 struct ptp_dte *ptp_dte = dev_get_drvdata(dev); 277 u8 i; 278 279 for (i = 0; i < DTE_NUM_REGS_TO_RESTORE; i++) { 280 ptp_dte->reg_val[i] = 281 readl(ptp_dte->regs + (i * sizeof(u32))); 282 } 283 284 /* disable the nco */ 285 writel(0, ptp_dte->regs + DTE_NCO_INC_REG); 286 287 return 0; 288 } 289 290 static int ptp_dte_resume(struct device *dev) 291 { 292 struct ptp_dte *ptp_dte = dev_get_drvdata(dev); 293 u8 i; 294 295 for (i = 0; i < DTE_NUM_REGS_TO_RESTORE; i++) { 296 if ((i * sizeof(u32)) != DTE_NCO_OVERFLOW_REG) 297 writel(ptp_dte->reg_val[i], 298 (ptp_dte->regs + (i * sizeof(u32)))); 299 else 300 writel(((ptp_dte->reg_val[i] & 301 DTE_NCO_SUM3_MASK) << DTE_NCO_SUM3_WR_SHIFT), 302 (ptp_dte->regs + (i * sizeof(u32)))); 303 } 304 305 return 0; 306 } 307 308 static const struct dev_pm_ops ptp_dte_pm_ops = { 309 .suspend = ptp_dte_suspend, 310 .resume = ptp_dte_resume 311 }; 312 313 #define PTP_DTE_PM_OPS (&ptp_dte_pm_ops) 314 #else 315 #define PTP_DTE_PM_OPS NULL 316 #endif 317 318 static const struct of_device_id ptp_dte_of_match[] = { 319 { .compatible = "brcm,ptp-dte", }, 320 {}, 321 }; 322 MODULE_DEVICE_TABLE(of, ptp_dte_of_match); 323 324 static struct platform_driver ptp_dte_driver = { 325 .driver = { 326 .name = "ptp-dte", 327 .pm = PTP_DTE_PM_OPS, 328 .of_match_table = ptp_dte_of_match, 329 }, 330 .probe = ptp_dte_probe, 331 .remove = ptp_dte_remove, 332 }; 333 module_platform_driver(ptp_dte_driver); 334 335 MODULE_AUTHOR("Broadcom"); 336 MODULE_DESCRIPTION("Broadcom DTE PTP Clock driver"); 337 MODULE_LICENSE("GPL v2"); 338