1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and 4 * synchronization devices. 5 * 6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. 7 */ 8 #ifndef PTP_IDTCLOCKMATRIX_H 9 #define PTP_IDTCLOCKMATRIX_H 10 11 #include <linux/ktime.h> 12 13 #include "idt8a340_reg.h" 14 15 #define FW_FILENAME "idtcm.bin" 16 #define MAX_TOD (4) 17 #define MAX_PLL (8) 18 19 #define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL) 20 21 #define TOD_MASK_ADDR (0xFFA5) 22 #define DEFAULT_TOD_MASK (0x04) 23 24 #define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8)) 25 #define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8)) 26 27 #define TOD0_PTP_PLL_ADDR (0xFFA8) 28 #define TOD1_PTP_PLL_ADDR (0xFFA9) 29 #define TOD2_PTP_PLL_ADDR (0xFFAA) 30 #define TOD3_PTP_PLL_ADDR (0xFFAB) 31 32 #define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0) 33 #define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2) 34 #define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4) 35 #define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6) 36 37 #define DEFAULT_OUTPUT_MASK_PLL0 (0x003) 38 #define DEFAULT_OUTPUT_MASK_PLL1 (0x00c) 39 #define DEFAULT_OUTPUT_MASK_PLL2 (0x030) 40 #define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0) 41 42 #define DEFAULT_TOD0_PTP_PLL (0) 43 #define DEFAULT_TOD1_PTP_PLL (1) 44 #define DEFAULT_TOD2_PTP_PLL (2) 45 #define DEFAULT_TOD3_PTP_PLL (3) 46 47 #define POST_SM_RESET_DELAY_MS (3000) 48 #define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED (150000) 49 #define PHASE_PULL_IN_THRESHOLD_NS (15000) 50 #define TOD_WRITE_OVERHEAD_COUNT_MAX (2) 51 #define TOD_BYTE_COUNT (11) 52 53 #define LOCK_TIMEOUT_MS (2000) 54 #define LOCK_POLL_INTERVAL_MS (10) 55 56 #define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef) 57 58 #define IDTCM_MAX_WRITE_COUNT (512) 59 60 #define FULL_FW_CFG_BYTES (SCRATCH - GPIO_USER_CONTROL) 61 #define FULL_FW_CFG_SKIPPED_BYTES (((SCRATCH >> 7) \ 62 - (GPIO_USER_CONTROL >> 7)) \ 63 * 4) /* 4 bytes skipped every 0x80 */ 64 65 /* Values of DPLL_N.DPLL_MODE.PLL_MODE */ 66 enum pll_mode { 67 PLL_MODE_MIN = 0, 68 PLL_MODE_NORMAL = PLL_MODE_MIN, 69 PLL_MODE_WRITE_PHASE = 1, 70 PLL_MODE_WRITE_FREQUENCY = 2, 71 PLL_MODE_GPIO_INC_DEC = 3, 72 PLL_MODE_SYNTHESIS = 4, 73 PLL_MODE_PHASE_MEASUREMENT = 5, 74 PLL_MODE_DISABLED = 6, 75 PLL_MODE_MAX = PLL_MODE_DISABLED, 76 }; 77 78 enum hw_tod_write_trig_sel { 79 HW_TOD_WR_TRIG_SEL_MIN = 0, 80 HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN, 81 HW_TOD_WR_TRIG_SEL_RESERVED = 1, 82 HW_TOD_WR_TRIG_SEL_TOD_PPS = 2, 83 HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3, 84 HW_TOD_WR_TRIG_SEL_PWM_PPS = 4, 85 HW_TOD_WR_TRIG_SEL_GPIO = 5, 86 HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6, 87 WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC, 88 }; 89 90 /* 4.8.7 only */ 91 enum scsr_tod_write_trig_sel { 92 SCSR_TOD_WR_TRIG_SEL_DISABLE = 0, 93 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1, 94 SCSR_TOD_WR_TRIG_SEL_REFCLK = 2, 95 SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3, 96 SCSR_TOD_WR_TRIG_SEL_TODPPS = 4, 97 SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5, 98 SCSR_TOD_WR_TRIG_SEL_GPIO = 6, 99 SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO, 100 }; 101 102 /* 4.8.7 only */ 103 enum scsr_tod_write_type_sel { 104 SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0, 105 SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1, 106 SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2, 107 SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS, 108 }; 109 110 /* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */ 111 enum dpll_state { 112 DPLL_STATE_MIN = 0, 113 DPLL_STATE_FREERUN = DPLL_STATE_MIN, 114 DPLL_STATE_LOCKACQ = 1, 115 DPLL_STATE_LOCKREC = 2, 116 DPLL_STATE_LOCKED = 3, 117 DPLL_STATE_HOLDOVER = 4, 118 DPLL_STATE_OPEN_LOOP = 5, 119 DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP, 120 }; 121 122 struct idtcm; 123 124 struct idtcm_channel { 125 struct ptp_clock_info caps; 126 struct ptp_clock *ptp_clock; 127 struct idtcm *idtcm; 128 u16 dpll_phase; 129 u16 dpll_freq; 130 u16 dpll_n; 131 u16 dpll_ctrl_n; 132 u16 dpll_phase_pull_in; 133 u16 tod_read_primary; 134 u16 tod_write; 135 u16 tod_n; 136 u16 hw_dpll_n; 137 enum pll_mode pll_mode; 138 u8 pll; 139 u16 output_mask; 140 }; 141 142 struct idtcm { 143 struct idtcm_channel channel[MAX_TOD]; 144 struct i2c_client *client; 145 u8 page_offset; 146 u8 tod_mask; 147 char version[16]; 148 u8 deprecated; 149 150 /* Overhead calculation for adjtime */ 151 u8 calculate_overhead_flag; 152 s64 tod_write_overhead_ns; 153 ktime_t start_time; 154 155 /* Protects I2C read/modify/write registers from concurrent access */ 156 struct mutex reg_lock; 157 }; 158 159 struct idtcm_fwrc { 160 u8 hiaddr; 161 u8 loaddr; 162 u8 value; 163 u8 reserved; 164 } __packed; 165 166 #endif /* PTP_IDTCLOCKMATRIX_H */ 167