1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and 4 * synchronization devices. 5 * 6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. 7 */ 8 #ifndef PTP_IDTCLOCKMATRIX_H 9 #define PTP_IDTCLOCKMATRIX_H 10 11 #include <linux/ktime.h> 12 13 #include "idt8a340_reg.h" 14 15 #define FW_FILENAME "idtcm.bin" 16 #define MAX_TOD (4) 17 #define MAX_PLL (8) 18 19 #define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL) 20 21 #define TOD_MASK_ADDR (0xFFA5) 22 #define DEFAULT_TOD_MASK (0x04) 23 24 #define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8)) 25 #define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8)) 26 27 #define TOD0_PTP_PLL_ADDR (0xFFA8) 28 #define TOD1_PTP_PLL_ADDR (0xFFA9) 29 #define TOD2_PTP_PLL_ADDR (0xFFAA) 30 #define TOD3_PTP_PLL_ADDR (0xFFAB) 31 32 #define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0) 33 #define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2) 34 #define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4) 35 #define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6) 36 37 #define DEFAULT_OUTPUT_MASK_PLL0 (0x003) 38 #define DEFAULT_OUTPUT_MASK_PLL1 (0x00c) 39 #define DEFAULT_OUTPUT_MASK_PLL2 (0x030) 40 #define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0) 41 42 #define DEFAULT_TOD0_PTP_PLL (0) 43 #define DEFAULT_TOD1_PTP_PLL (1) 44 #define DEFAULT_TOD2_PTP_PLL (2) 45 #define DEFAULT_TOD3_PTP_PLL (3) 46 47 #define POST_SM_RESET_DELAY_MS (3000) 48 #define PHASE_PULL_IN_THRESHOLD_NS (150000) 49 #define PHASE_PULL_IN_THRESHOLD_NS_V487 (15000) 50 #define TOD_WRITE_OVERHEAD_COUNT_MAX (2) 51 #define TOD_BYTE_COUNT (11) 52 #define WR_PHASE_SETUP_MS (5000) 53 54 #define OUTPUT_MODULE_FROM_INDEX(index) (OUTPUT_0 + (index) * 0x10) 55 56 #define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef) 57 58 /* Values of DPLL_N.DPLL_MODE.PLL_MODE */ 59 enum pll_mode { 60 PLL_MODE_MIN = 0, 61 PLL_MODE_NORMAL = PLL_MODE_MIN, 62 PLL_MODE_WRITE_PHASE = 1, 63 PLL_MODE_WRITE_FREQUENCY = 2, 64 PLL_MODE_GPIO_INC_DEC = 3, 65 PLL_MODE_SYNTHESIS = 4, 66 PLL_MODE_PHASE_MEASUREMENT = 5, 67 PLL_MODE_DISABLED = 6, 68 PLL_MODE_MAX = PLL_MODE_DISABLED, 69 }; 70 71 enum hw_tod_write_trig_sel { 72 HW_TOD_WR_TRIG_SEL_MIN = 0, 73 HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN, 74 HW_TOD_WR_TRIG_SEL_RESERVED = 1, 75 HW_TOD_WR_TRIG_SEL_TOD_PPS = 2, 76 HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3, 77 HW_TOD_WR_TRIG_SEL_PWM_PPS = 4, 78 HW_TOD_WR_TRIG_SEL_GPIO = 5, 79 HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6, 80 WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC, 81 }; 82 83 /* 4.8.7 only */ 84 enum scsr_tod_write_trig_sel { 85 SCSR_TOD_WR_TRIG_SEL_DISABLE = 0, 86 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1, 87 SCSR_TOD_WR_TRIG_SEL_REFCLK = 2, 88 SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3, 89 SCSR_TOD_WR_TRIG_SEL_TODPPS = 4, 90 SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5, 91 SCSR_TOD_WR_TRIG_SEL_GPIO = 6, 92 SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO, 93 }; 94 95 /* 4.8.7 only */ 96 enum scsr_tod_write_type_sel { 97 SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0, 98 SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1, 99 SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2, 100 SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS, 101 }; 102 103 struct idtcm; 104 105 struct idtcm_channel { 106 struct ptp_clock_info caps; 107 struct ptp_clock *ptp_clock; 108 struct idtcm *idtcm; 109 u16 dpll_phase; 110 u16 dpll_freq; 111 u16 dpll_n; 112 u16 dpll_ctrl_n; 113 u16 dpll_phase_pull_in; 114 u16 tod_read_primary; 115 u16 tod_write; 116 u16 tod_n; 117 u16 hw_dpll_n; 118 enum pll_mode pll_mode; 119 u8 pll; 120 u16 output_mask; 121 int write_phase_ready; 122 }; 123 124 struct idtcm { 125 struct idtcm_channel channel[MAX_TOD]; 126 struct i2c_client *client; 127 u8 page_offset; 128 u8 tod_mask; 129 char version[16]; 130 131 /* Overhead calculation for adjtime */ 132 u8 calculate_overhead_flag; 133 s64 tod_write_overhead_ns; 134 ktime_t start_time; 135 136 /* Protects I2C read/modify/write registers from concurrent access */ 137 struct mutex reg_lock; 138 }; 139 140 struct idtcm_fwrc { 141 u8 hiaddr; 142 u8 loaddr; 143 u8 value; 144 u8 reserved; 145 } __packed; 146 147 #endif /* PTP_IDTCLOCKMATRIX_H */ 148