1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and 4 * synchronization devices. 5 * 6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. 7 */ 8 #ifndef PTP_IDTCLOCKMATRIX_H 9 #define PTP_IDTCLOCKMATRIX_H 10 11 #include <linux/ktime.h> 12 13 #include "idt8a340_reg.h" 14 15 #define FW_FILENAME "idtcm.bin" 16 #define MAX_TOD (4) 17 #define MAX_PLL (8) 18 #define MAX_OUTPUT (12) 19 20 #define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL) 21 22 #define TOD_MASK_ADDR (0xFFA5) 23 #define DEFAULT_TOD_MASK (0x04) 24 25 #define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8)) 26 #define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8)) 27 28 #define TOD0_PTP_PLL_ADDR (0xFFA8) 29 #define TOD1_PTP_PLL_ADDR (0xFFA9) 30 #define TOD2_PTP_PLL_ADDR (0xFFAA) 31 #define TOD3_PTP_PLL_ADDR (0xFFAB) 32 33 #define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0) 34 #define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2) 35 #define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4) 36 #define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6) 37 38 #define DEFAULT_OUTPUT_MASK_PLL0 (0x003) 39 #define DEFAULT_OUTPUT_MASK_PLL1 (0x00c) 40 #define DEFAULT_OUTPUT_MASK_PLL2 (0x030) 41 #define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0) 42 43 #define DEFAULT_TOD0_PTP_PLL (0) 44 #define DEFAULT_TOD1_PTP_PLL (1) 45 #define DEFAULT_TOD2_PTP_PLL (2) 46 #define DEFAULT_TOD3_PTP_PLL (3) 47 48 #define POST_SM_RESET_DELAY_MS (3000) 49 #define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED (150000) 50 #define PHASE_PULL_IN_THRESHOLD_NS (15000) 51 #define TOD_WRITE_OVERHEAD_COUNT_MAX (2) 52 #define TOD_BYTE_COUNT (11) 53 54 #define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef) 55 56 #define IDTCM_MAX_WRITE_COUNT (512) 57 58 #define FULL_FW_CFG_BYTES (SCRATCH - GPIO_USER_CONTROL) 59 #define FULL_FW_CFG_SKIPPED_BYTES (((SCRATCH >> 7) \ 60 - (GPIO_USER_CONTROL >> 7)) \ 61 * 4) /* 4 bytes skipped every 0x80 */ 62 63 /* Values of DPLL_N.DPLL_MODE.PLL_MODE */ 64 enum pll_mode { 65 PLL_MODE_MIN = 0, 66 PLL_MODE_NORMAL = PLL_MODE_MIN, 67 PLL_MODE_WRITE_PHASE = 1, 68 PLL_MODE_WRITE_FREQUENCY = 2, 69 PLL_MODE_GPIO_INC_DEC = 3, 70 PLL_MODE_SYNTHESIS = 4, 71 PLL_MODE_PHASE_MEASUREMENT = 5, 72 PLL_MODE_DISABLED = 6, 73 PLL_MODE_MAX = PLL_MODE_DISABLED, 74 }; 75 76 enum hw_tod_write_trig_sel { 77 HW_TOD_WR_TRIG_SEL_MIN = 0, 78 HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN, 79 HW_TOD_WR_TRIG_SEL_RESERVED = 1, 80 HW_TOD_WR_TRIG_SEL_TOD_PPS = 2, 81 HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3, 82 HW_TOD_WR_TRIG_SEL_PWM_PPS = 4, 83 HW_TOD_WR_TRIG_SEL_GPIO = 5, 84 HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6, 85 WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC, 86 }; 87 88 /* 4.8.7 only */ 89 enum scsr_tod_write_trig_sel { 90 SCSR_TOD_WR_TRIG_SEL_DISABLE = 0, 91 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1, 92 SCSR_TOD_WR_TRIG_SEL_REFCLK = 2, 93 SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3, 94 SCSR_TOD_WR_TRIG_SEL_TODPPS = 4, 95 SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5, 96 SCSR_TOD_WR_TRIG_SEL_GPIO = 6, 97 SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO, 98 }; 99 100 /* 4.8.7 only */ 101 enum scsr_tod_write_type_sel { 102 SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0, 103 SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1, 104 SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2, 105 SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS, 106 }; 107 108 struct idtcm; 109 110 struct idtcm_channel { 111 struct ptp_clock_info caps; 112 struct ptp_clock *ptp_clock; 113 struct idtcm *idtcm; 114 u16 dpll_phase; 115 u16 dpll_freq; 116 u16 dpll_n; 117 u16 dpll_ctrl_n; 118 u16 dpll_phase_pull_in; 119 u16 tod_read_primary; 120 u16 tod_write; 121 u16 tod_n; 122 u16 hw_dpll_n; 123 enum pll_mode pll_mode; 124 u8 pll; 125 u16 output_mask; 126 u8 output_phase_adj[MAX_OUTPUT][4]; 127 }; 128 129 struct idtcm { 130 struct idtcm_channel channel[MAX_TOD]; 131 struct i2c_client *client; 132 u8 page_offset; 133 u8 tod_mask; 134 char version[16]; 135 u8 deprecated; 136 137 /* Overhead calculation for adjtime */ 138 u8 calculate_overhead_flag; 139 s64 tod_write_overhead_ns; 140 ktime_t start_time; 141 142 /* Protects I2C read/modify/write registers from concurrent access */ 143 struct mutex reg_lock; 144 }; 145 146 struct idtcm_fwrc { 147 u8 hiaddr; 148 u8 loaddr; 149 u8 value; 150 u8 reserved; 151 } __packed; 152 153 #endif /* PTP_IDTCLOCKMATRIX_H */ 154