1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and 4 * synchronization devices. 5 * 6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. 7 */ 8 #include <linux/firmware.h> 9 #include <linux/i2c.h> 10 #include <linux/module.h> 11 #include <linux/ptp_clock_kernel.h> 12 #include <linux/delay.h> 13 #include <linux/jiffies.h> 14 #include <linux/kernel.h> 15 #include <linux/timekeeping.h> 16 #include <linux/string.h> 17 18 #include "ptp_private.h" 19 #include "ptp_clockmatrix.h" 20 21 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family"); 22 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); 23 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>"); 24 MODULE_VERSION("1.0"); 25 MODULE_LICENSE("GPL"); 26 27 /* 28 * The name of the firmware file to be loaded 29 * over-rides any automatic selection 30 */ 31 static char *firmware; 32 module_param(firmware, charp, 0); 33 34 #define SETTIME_CORRECTION (0) 35 36 static int contains_full_configuration(const struct firmware *fw) 37 { 38 s32 full_count = FULL_FW_CFG_BYTES - FULL_FW_CFG_SKIPPED_BYTES; 39 struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data; 40 s32 count = 0; 41 u16 regaddr; 42 u8 loaddr; 43 s32 len; 44 45 /* If the firmware contains 'full configuration' SM_RESET can be used 46 * to ensure proper configuration. 47 * 48 * Full configuration is defined as the number of programmable 49 * bytes within the configuration range minus page offset addr range. 50 */ 51 for (len = fw->size; len > 0; len -= sizeof(*rec)) { 52 regaddr = rec->hiaddr << 8; 53 regaddr |= rec->loaddr; 54 55 loaddr = rec->loaddr; 56 57 rec++; 58 59 /* Top (status registers) and bottom are read-only */ 60 if (regaddr < GPIO_USER_CONTROL || regaddr >= SCRATCH) 61 continue; 62 63 /* Page size 128, last 4 bytes of page skipped */ 64 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb) 65 continue; 66 67 count++; 68 } 69 70 return (count >= full_count); 71 } 72 73 static int char_array_to_timespec(u8 *buf, 74 u8 count, 75 struct timespec64 *ts) 76 { 77 u8 i; 78 u64 nsec; 79 time64_t sec; 80 81 if (count < TOD_BYTE_COUNT) 82 return 1; 83 84 /* Sub-nanoseconds are in buf[0]. */ 85 nsec = buf[4]; 86 for (i = 0; i < 3; i++) { 87 nsec <<= 8; 88 nsec |= buf[3 - i]; 89 } 90 91 sec = buf[10]; 92 for (i = 0; i < 5; i++) { 93 sec <<= 8; 94 sec |= buf[9 - i]; 95 } 96 97 ts->tv_sec = sec; 98 ts->tv_nsec = nsec; 99 100 return 0; 101 } 102 103 static int timespec_to_char_array(struct timespec64 const *ts, 104 u8 *buf, 105 u8 count) 106 { 107 u8 i; 108 s32 nsec; 109 time64_t sec; 110 111 if (count < TOD_BYTE_COUNT) 112 return 1; 113 114 nsec = ts->tv_nsec; 115 sec = ts->tv_sec; 116 117 /* Sub-nanoseconds are in buf[0]. */ 118 buf[0] = 0; 119 for (i = 1; i < 5; i++) { 120 buf[i] = nsec & 0xff; 121 nsec >>= 8; 122 } 123 124 for (i = 5; i < TOD_BYTE_COUNT; i++) { 125 126 buf[i] = sec & 0xff; 127 sec >>= 8; 128 } 129 130 return 0; 131 } 132 133 static int idtcm_strverscmp(const char *version1, const char *version2) 134 { 135 u8 ver1[3], ver2[3]; 136 int i; 137 138 if (sscanf(version1, "%hhu.%hhu.%hhu", 139 &ver1[0], &ver1[1], &ver1[2]) != 3) 140 return -1; 141 if (sscanf(version2, "%hhu.%hhu.%hhu", 142 &ver2[0], &ver2[1], &ver2[2]) != 3) 143 return -1; 144 145 for (i = 0; i < 3; i++) { 146 if (ver1[i] > ver2[i]) 147 return 1; 148 if (ver1[i] < ver2[i]) 149 return -1; 150 } 151 152 return 0; 153 } 154 155 static int idtcm_xfer_read(struct idtcm *idtcm, 156 u8 regaddr, 157 u8 *buf, 158 u16 count) 159 { 160 struct i2c_client *client = idtcm->client; 161 struct i2c_msg msg[2]; 162 int cnt; 163 char *fmt = "i2c_transfer failed at %d in %s, at addr: %04X!\n"; 164 165 msg[0].addr = client->addr; 166 msg[0].flags = 0; 167 msg[0].len = 1; 168 msg[0].buf = ®addr; 169 170 msg[1].addr = client->addr; 171 msg[1].flags = I2C_M_RD; 172 msg[1].len = count; 173 msg[1].buf = buf; 174 175 cnt = i2c_transfer(client->adapter, msg, 2); 176 177 if (cnt < 0) { 178 dev_err(&client->dev, 179 fmt, 180 __LINE__, 181 __func__, 182 regaddr); 183 return cnt; 184 } else if (cnt != 2) { 185 dev_err(&client->dev, 186 "i2c_transfer sent only %d of %d messages\n", cnt, 2); 187 return -EIO; 188 } 189 190 return 0; 191 } 192 193 static int idtcm_xfer_write(struct idtcm *idtcm, 194 u8 regaddr, 195 u8 *buf, 196 u16 count) 197 { 198 struct i2c_client *client = idtcm->client; 199 /* we add 1 byte for device register */ 200 u8 msg[IDTCM_MAX_WRITE_COUNT + 1]; 201 int cnt; 202 char *fmt = "i2c_master_send failed at %d in %s, at addr: %04X!\n"; 203 204 if (count > IDTCM_MAX_WRITE_COUNT) 205 return -EINVAL; 206 207 msg[0] = regaddr; 208 memcpy(&msg[1], buf, count); 209 210 cnt = i2c_master_send(client, msg, count + 1); 211 212 if (cnt < 0) { 213 dev_err(&client->dev, 214 fmt, 215 __LINE__, 216 __func__, 217 regaddr); 218 return cnt; 219 } 220 221 return 0; 222 } 223 224 static int idtcm_page_offset(struct idtcm *idtcm, u8 val) 225 { 226 u8 buf[4]; 227 int err; 228 229 if (idtcm->page_offset == val) 230 return 0; 231 232 buf[0] = 0x0; 233 buf[1] = val; 234 buf[2] = 0x10; 235 buf[3] = 0x20; 236 237 err = idtcm_xfer_write(idtcm, PAGE_ADDR, buf, sizeof(buf)); 238 239 if (err) { 240 idtcm->page_offset = 0xff; 241 dev_err(&idtcm->client->dev, "failed to set page offset\n"); 242 } else { 243 idtcm->page_offset = val; 244 } 245 246 return err; 247 } 248 249 static int _idtcm_rdwr(struct idtcm *idtcm, 250 u16 regaddr, 251 u8 *buf, 252 u16 count, 253 bool write) 254 { 255 u8 hi; 256 u8 lo; 257 int err; 258 259 hi = (regaddr >> 8) & 0xff; 260 lo = regaddr & 0xff; 261 262 err = idtcm_page_offset(idtcm, hi); 263 264 if (err) 265 return err; 266 267 if (write) 268 return idtcm_xfer_write(idtcm, lo, buf, count); 269 270 return idtcm_xfer_read(idtcm, lo, buf, count); 271 } 272 273 static int idtcm_read(struct idtcm *idtcm, 274 u16 module, 275 u16 regaddr, 276 u8 *buf, 277 u16 count) 278 { 279 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false); 280 } 281 282 static int idtcm_write(struct idtcm *idtcm, 283 u16 module, 284 u16 regaddr, 285 u8 *buf, 286 u16 count) 287 { 288 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true); 289 } 290 291 static int clear_boot_status(struct idtcm *idtcm) 292 { 293 int err; 294 u8 buf[4] = {0}; 295 296 err = idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf)); 297 298 return err; 299 } 300 301 static int read_boot_status(struct idtcm *idtcm, u32 *status) 302 { 303 int err; 304 u8 buf[4] = {0}; 305 306 err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf)); 307 308 *status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 309 310 return err; 311 } 312 313 static int wait_for_boot_status_ready(struct idtcm *idtcm) 314 { 315 u32 status = 0; 316 u8 i = 30; /* 30 * 100ms = 3s */ 317 int err; 318 319 do { 320 err = read_boot_status(idtcm, &status); 321 322 if (err) 323 return err; 324 325 if (status == 0xA0) 326 return 0; 327 328 msleep(100); 329 i--; 330 331 } while (i); 332 333 dev_warn(&idtcm->client->dev, "%s timed out\n", __func__); 334 335 return -EBUSY; 336 } 337 338 static int _idtcm_gettime(struct idtcm_channel *channel, 339 struct timespec64 *ts) 340 { 341 struct idtcm *idtcm = channel->idtcm; 342 u8 buf[TOD_BYTE_COUNT]; 343 u8 timeout = 10; 344 u8 trigger; 345 int err; 346 347 err = idtcm_read(idtcm, channel->tod_read_primary, 348 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger)); 349 if (err) 350 return err; 351 352 trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT); 353 trigger |= (1 << TOD_READ_TRIGGER_SHIFT); 354 trigger &= ~TOD_READ_TRIGGER_MODE; /* single shot */ 355 356 err = idtcm_write(idtcm, channel->tod_read_primary, 357 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger)); 358 if (err) 359 return err; 360 361 /* wait trigger to be 0 */ 362 while (trigger & TOD_READ_TRIGGER_MASK) { 363 364 if (idtcm->calculate_overhead_flag) 365 idtcm->start_time = ktime_get_raw(); 366 367 err = idtcm_read(idtcm, channel->tod_read_primary, 368 TOD_READ_PRIMARY_CMD, &trigger, 369 sizeof(trigger)); 370 371 if (err) 372 return err; 373 374 if (--timeout == 0) 375 return -EIO; 376 } 377 378 err = idtcm_read(idtcm, channel->tod_read_primary, 379 TOD_READ_PRIMARY, buf, sizeof(buf)); 380 381 if (err) 382 return err; 383 384 err = char_array_to_timespec(buf, sizeof(buf), ts); 385 386 return err; 387 } 388 389 static int _sync_pll_output(struct idtcm *idtcm, 390 u8 pll, 391 u8 sync_src, 392 u8 qn, 393 u8 qn_plus_1) 394 { 395 int err; 396 u8 val; 397 u16 sync_ctrl0; 398 u16 sync_ctrl1; 399 u8 temp; 400 401 if ((qn == 0) && (qn_plus_1 == 0)) 402 return 0; 403 404 switch (pll) { 405 case 0: 406 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0; 407 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1; 408 break; 409 case 1: 410 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0; 411 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1; 412 break; 413 case 2: 414 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0; 415 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1; 416 break; 417 case 3: 418 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0; 419 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1; 420 break; 421 case 4: 422 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0; 423 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1; 424 break; 425 case 5: 426 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0; 427 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1; 428 break; 429 case 6: 430 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0; 431 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1; 432 break; 433 case 7: 434 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0; 435 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1; 436 break; 437 default: 438 return -EINVAL; 439 } 440 441 val = SYNCTRL1_MASTER_SYNC_RST; 442 443 /* Place master sync in reset */ 444 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 445 if (err) 446 return err; 447 448 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src)); 449 if (err) 450 return err; 451 452 /* Set sync trigger mask */ 453 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG; 454 455 if (qn) 456 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG; 457 458 if (qn_plus_1) 459 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG; 460 461 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 462 if (err) 463 return err; 464 465 /* PLL5 can have OUT8 as second additional output. */ 466 if ((pll == 5) && (qn_plus_1 != 0)) { 467 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE, 468 &temp, sizeof(temp)); 469 if (err) 470 return err; 471 472 temp &= ~(Q9_TO_Q8_SYNC_TRIG); 473 474 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE, 475 &temp, sizeof(temp)); 476 if (err) 477 return err; 478 479 temp |= Q9_TO_Q8_SYNC_TRIG; 480 481 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE, 482 &temp, sizeof(temp)); 483 if (err) 484 return err; 485 } 486 487 /* PLL6 can have OUT11 as second additional output. */ 488 if ((pll == 6) && (qn_plus_1 != 0)) { 489 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE, 490 &temp, sizeof(temp)); 491 if (err) 492 return err; 493 494 temp &= ~(Q10_TO_Q11_SYNC_TRIG); 495 496 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE, 497 &temp, sizeof(temp)); 498 if (err) 499 return err; 500 501 temp |= Q10_TO_Q11_SYNC_TRIG; 502 503 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE, 504 &temp, sizeof(temp)); 505 if (err) 506 return err; 507 } 508 509 /* Place master sync out of reset */ 510 val &= ~(SYNCTRL1_MASTER_SYNC_RST); 511 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 512 513 return err; 514 } 515 516 static int sync_source_dpll_tod_pps(u16 tod_addr, u8 *sync_src) 517 { 518 int err = 0; 519 520 switch (tod_addr) { 521 case TOD_0: 522 *sync_src = SYNC_SOURCE_DPLL0_TOD_PPS; 523 break; 524 case TOD_1: 525 *sync_src = SYNC_SOURCE_DPLL1_TOD_PPS; 526 break; 527 case TOD_2: 528 *sync_src = SYNC_SOURCE_DPLL2_TOD_PPS; 529 break; 530 case TOD_3: 531 *sync_src = SYNC_SOURCE_DPLL3_TOD_PPS; 532 break; 533 default: 534 err = -EINVAL; 535 } 536 537 return err; 538 } 539 540 static int idtcm_sync_pps_output(struct idtcm_channel *channel) 541 { 542 struct idtcm *idtcm = channel->idtcm; 543 544 u8 pll; 545 u8 sync_src; 546 u8 qn; 547 u8 qn_plus_1; 548 int err = 0; 549 u8 out8_mux = 0; 550 u8 out11_mux = 0; 551 u8 temp; 552 553 u16 output_mask = channel->output_mask; 554 555 err = sync_source_dpll_tod_pps(channel->tod_n, &sync_src); 556 if (err) 557 return err; 558 559 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE, 560 &temp, sizeof(temp)); 561 if (err) 562 return err; 563 564 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) == 565 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) 566 out8_mux = 1; 567 568 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE, 569 &temp, sizeof(temp)); 570 if (err) 571 return err; 572 573 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) == 574 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) 575 out11_mux = 1; 576 577 for (pll = 0; pll < 8; pll++) { 578 qn = 0; 579 qn_plus_1 = 0; 580 581 if (pll < 4) { 582 /* First 4 pll has 2 outputs */ 583 qn = output_mask & 0x1; 584 output_mask = output_mask >> 1; 585 qn_plus_1 = output_mask & 0x1; 586 output_mask = output_mask >> 1; 587 } else if (pll == 4) { 588 if (out8_mux == 0) { 589 qn = output_mask & 0x1; 590 output_mask = output_mask >> 1; 591 } 592 } else if (pll == 5) { 593 if (out8_mux) { 594 qn_plus_1 = output_mask & 0x1; 595 output_mask = output_mask >> 1; 596 } 597 qn = output_mask & 0x1; 598 output_mask = output_mask >> 1; 599 } else if (pll == 6) { 600 qn = output_mask & 0x1; 601 output_mask = output_mask >> 1; 602 if (out11_mux) { 603 qn_plus_1 = output_mask & 0x1; 604 output_mask = output_mask >> 1; 605 } 606 } else if (pll == 7) { 607 if (out11_mux == 0) { 608 qn = output_mask & 0x1; 609 output_mask = output_mask >> 1; 610 } 611 } 612 613 if ((qn != 0) || (qn_plus_1 != 0)) 614 err = _sync_pll_output(idtcm, pll, sync_src, qn, 615 qn_plus_1); 616 617 if (err) 618 return err; 619 } 620 621 return err; 622 } 623 624 static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel, 625 struct timespec64 const *ts, 626 enum hw_tod_write_trig_sel wr_trig) 627 { 628 struct idtcm *idtcm = channel->idtcm; 629 630 u8 buf[TOD_BYTE_COUNT]; 631 u8 cmd; 632 int err; 633 struct timespec64 local_ts = *ts; 634 s64 total_overhead_ns; 635 636 /* Configure HW TOD write trigger. */ 637 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 638 &cmd, sizeof(cmd)); 639 640 if (err) 641 return err; 642 643 cmd &= ~(0x0f); 644 cmd |= wr_trig | 0x08; 645 646 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 647 &cmd, sizeof(cmd)); 648 649 if (err) 650 return err; 651 652 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) { 653 654 err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); 655 656 if (err) 657 return err; 658 659 err = idtcm_write(idtcm, channel->hw_dpll_n, 660 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 661 662 if (err) 663 return err; 664 } 665 666 /* ARM HW TOD write trigger. */ 667 cmd &= ~(0x08); 668 669 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 670 &cmd, sizeof(cmd)); 671 672 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) { 673 674 if (idtcm->calculate_overhead_flag) { 675 /* Assumption: I2C @ 400KHz */ 676 total_overhead_ns = ktime_to_ns(ktime_get_raw() 677 - idtcm->start_time) 678 + idtcm->tod_write_overhead_ns 679 + SETTIME_CORRECTION; 680 681 timespec64_add_ns(&local_ts, total_overhead_ns); 682 683 idtcm->calculate_overhead_flag = 0; 684 } 685 686 err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); 687 688 if (err) 689 return err; 690 691 err = idtcm_write(idtcm, channel->hw_dpll_n, 692 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 693 } 694 695 return err; 696 } 697 698 static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel, 699 struct timespec64 const *ts, 700 enum scsr_tod_write_trig_sel wr_trig, 701 enum scsr_tod_write_type_sel wr_type) 702 { 703 struct idtcm *idtcm = channel->idtcm; 704 unsigned char buf[TOD_BYTE_COUNT], cmd; 705 struct timespec64 local_ts = *ts; 706 int err, count = 0; 707 708 timespec64_add_ns(&local_ts, SETTIME_CORRECTION); 709 710 err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); 711 712 if (err) 713 return err; 714 715 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE, 716 buf, sizeof(buf)); 717 if (err) 718 return err; 719 720 /* Trigger the write operation. */ 721 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD, 722 &cmd, sizeof(cmd)); 723 if (err) 724 return err; 725 726 cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT); 727 cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT); 728 cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT); 729 cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT); 730 731 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD, 732 &cmd, sizeof(cmd)); 733 if (err) 734 return err; 735 736 /* Wait for the operation to complete. */ 737 while (1) { 738 /* pps trigger takes up to 1 sec to complete */ 739 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS) 740 msleep(50); 741 742 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD, 743 &cmd, sizeof(cmd)); 744 if (err) 745 return err; 746 747 if ((cmd & TOD_WRITE_SELECTION_MASK) == 0) 748 break; 749 750 if (++count > 20) { 751 dev_err(&idtcm->client->dev, 752 "Timed out waiting for the write counter\n"); 753 return -EIO; 754 } 755 } 756 757 return 0; 758 } 759 760 static int _idtcm_settime(struct idtcm_channel *channel, 761 struct timespec64 const *ts) 762 { 763 struct idtcm *idtcm = channel->idtcm; 764 int err; 765 766 err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB); 767 768 if (err) { 769 dev_err(&idtcm->client->dev, 770 "%s: Set HW ToD failed\n", __func__); 771 return err; 772 } 773 774 return idtcm_sync_pps_output(channel); 775 } 776 777 static int _idtcm_settime_v487(struct idtcm_channel *channel, 778 struct timespec64 const *ts, 779 enum scsr_tod_write_type_sel wr_type) 780 { 781 return _idtcm_set_dpll_scsr_tod(channel, ts, 782 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE, 783 wr_type); 784 } 785 786 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel, 787 s32 offset_ns) 788 { 789 int err; 790 int i; 791 struct idtcm *idtcm = channel->idtcm; 792 793 u8 buf[4]; 794 795 for (i = 0; i < 4; i++) { 796 buf[i] = 0xff & (offset_ns); 797 offset_ns >>= 8; 798 } 799 800 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET, 801 buf, sizeof(buf)); 802 803 return err; 804 } 805 806 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel, 807 u32 max_ffo_ppb) 808 { 809 int err; 810 u8 i; 811 struct idtcm *idtcm = channel->idtcm; 812 813 u8 buf[3]; 814 815 if (max_ffo_ppb & 0xff000000) 816 max_ffo_ppb = 0; 817 818 for (i = 0; i < 3; i++) { 819 buf[i] = 0xff & (max_ffo_ppb); 820 max_ffo_ppb >>= 8; 821 } 822 823 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, 824 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf)); 825 826 return err; 827 } 828 829 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel) 830 { 831 int err; 832 struct idtcm *idtcm = channel->idtcm; 833 834 u8 buf; 835 836 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL, 837 &buf, sizeof(buf)); 838 839 if (err) 840 return err; 841 842 if (buf == 0) { 843 buf = 0x01; 844 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, 845 PULL_IN_CTRL, &buf, sizeof(buf)); 846 } else { 847 err = -EBUSY; 848 } 849 850 return err; 851 } 852 853 static int idtcm_do_phase_pull_in(struct idtcm_channel *channel, 854 s32 offset_ns, 855 u32 max_ffo_ppb) 856 { 857 int err; 858 859 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns); 860 861 if (err) 862 return err; 863 864 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb); 865 866 if (err) 867 return err; 868 869 err = idtcm_start_phase_pull_in(channel); 870 871 return err; 872 } 873 874 static int set_tod_write_overhead(struct idtcm_channel *channel) 875 { 876 struct idtcm *idtcm = channel->idtcm; 877 s64 current_ns = 0; 878 s64 lowest_ns = 0; 879 int err; 880 u8 i; 881 882 ktime_t start; 883 ktime_t stop; 884 885 char buf[TOD_BYTE_COUNT] = {0}; 886 887 /* Set page offset */ 888 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0, 889 buf, sizeof(buf)); 890 891 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) { 892 893 start = ktime_get_raw(); 894 895 err = idtcm_write(idtcm, channel->hw_dpll_n, 896 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 897 898 if (err) 899 return err; 900 901 stop = ktime_get_raw(); 902 903 current_ns = ktime_to_ns(stop - start); 904 905 if (i == 0) { 906 lowest_ns = current_ns; 907 } else { 908 if (current_ns < lowest_ns) 909 lowest_ns = current_ns; 910 } 911 } 912 913 idtcm->tod_write_overhead_ns = lowest_ns; 914 915 return err; 916 } 917 918 static int _idtcm_adjtime(struct idtcm_channel *channel, s64 delta) 919 { 920 int err; 921 struct idtcm *idtcm = channel->idtcm; 922 struct timespec64 ts; 923 s64 now; 924 925 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) { 926 err = idtcm_do_phase_pull_in(channel, delta, 0); 927 } else { 928 idtcm->calculate_overhead_flag = 1; 929 930 err = set_tod_write_overhead(channel); 931 932 if (err) 933 return err; 934 935 err = _idtcm_gettime(channel, &ts); 936 937 if (err) 938 return err; 939 940 now = timespec64_to_ns(&ts); 941 now += delta; 942 943 ts = ns_to_timespec64(now); 944 945 err = _idtcm_settime(channel, &ts); 946 } 947 948 return err; 949 } 950 951 static int idtcm_state_machine_reset(struct idtcm *idtcm) 952 { 953 u8 byte = SM_RESET_CMD; 954 u32 status = 0; 955 int err; 956 u8 i; 957 958 clear_boot_status(idtcm); 959 960 err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte)); 961 962 if (!err) { 963 for (i = 0; i < 30; i++) { 964 msleep_interruptible(100); 965 read_boot_status(idtcm, &status); 966 967 if (status == 0xA0) { 968 dev_dbg(&idtcm->client->dev, 969 "SM_RESET completed in %d ms\n", 970 i * 100); 971 break; 972 } 973 } 974 975 if (!status) 976 dev_err(&idtcm->client->dev, "Timed out waiting for CM_RESET to complete\n"); 977 } 978 979 return err; 980 } 981 982 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id) 983 { 984 return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8)); 985 } 986 987 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id) 988 { 989 int err; 990 u8 buf[2] = {0}; 991 992 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf)); 993 994 *product_id = (buf[1] << 8) | buf[0]; 995 996 return err; 997 } 998 999 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major) 1000 { 1001 int err; 1002 u8 buf = 0; 1003 1004 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf)); 1005 1006 *major = buf >> 1; 1007 1008 return err; 1009 } 1010 1011 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor) 1012 { 1013 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8)); 1014 } 1015 1016 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix) 1017 { 1018 return idtcm_read(idtcm, 1019 GENERAL_STATUS, 1020 HOTFIX_REL, 1021 hotfix, 1022 sizeof(u8)); 1023 } 1024 1025 static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm, 1026 u8 *config_select) 1027 { 1028 return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT, 1029 config_select, sizeof(u8)); 1030 } 1031 1032 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val) 1033 { 1034 int err = 0; 1035 1036 switch (addr) { 1037 case TOD0_OUT_ALIGN_MASK_ADDR: 1038 SET_U16_LSB(idtcm->channel[0].output_mask, val); 1039 break; 1040 case TOD0_OUT_ALIGN_MASK_ADDR + 1: 1041 SET_U16_MSB(idtcm->channel[0].output_mask, val); 1042 break; 1043 case TOD1_OUT_ALIGN_MASK_ADDR: 1044 SET_U16_LSB(idtcm->channel[1].output_mask, val); 1045 break; 1046 case TOD1_OUT_ALIGN_MASK_ADDR + 1: 1047 SET_U16_MSB(idtcm->channel[1].output_mask, val); 1048 break; 1049 case TOD2_OUT_ALIGN_MASK_ADDR: 1050 SET_U16_LSB(idtcm->channel[2].output_mask, val); 1051 break; 1052 case TOD2_OUT_ALIGN_MASK_ADDR + 1: 1053 SET_U16_MSB(idtcm->channel[2].output_mask, val); 1054 break; 1055 case TOD3_OUT_ALIGN_MASK_ADDR: 1056 SET_U16_LSB(idtcm->channel[3].output_mask, val); 1057 break; 1058 case TOD3_OUT_ALIGN_MASK_ADDR + 1: 1059 SET_U16_MSB(idtcm->channel[3].output_mask, val); 1060 break; 1061 default: 1062 err = -EFAULT; /* Bad address */; 1063 break; 1064 } 1065 1066 return err; 1067 } 1068 1069 static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll) 1070 { 1071 if (index >= MAX_TOD) { 1072 dev_err(&idtcm->client->dev, "ToD%d not supported\n", index); 1073 return -EINVAL; 1074 } 1075 1076 if (pll >= MAX_PLL) { 1077 dev_err(&idtcm->client->dev, "Pll%d not supported\n", pll); 1078 return -EINVAL; 1079 } 1080 1081 idtcm->channel[index].pll = pll; 1082 1083 return 0; 1084 } 1085 1086 static int check_and_set_masks(struct idtcm *idtcm, 1087 u16 regaddr, 1088 u8 val) 1089 { 1090 int err = 0; 1091 1092 switch (regaddr) { 1093 case TOD_MASK_ADDR: 1094 if ((val & 0xf0) || !(val & 0x0f)) { 1095 dev_err(&idtcm->client->dev, 1096 "Invalid TOD mask 0x%hhx\n", val); 1097 err = -EINVAL; 1098 } else { 1099 idtcm->tod_mask = val; 1100 } 1101 break; 1102 case TOD0_PTP_PLL_ADDR: 1103 err = set_tod_ptp_pll(idtcm, 0, val); 1104 break; 1105 case TOD1_PTP_PLL_ADDR: 1106 err = set_tod_ptp_pll(idtcm, 1, val); 1107 break; 1108 case TOD2_PTP_PLL_ADDR: 1109 err = set_tod_ptp_pll(idtcm, 2, val); 1110 break; 1111 case TOD3_PTP_PLL_ADDR: 1112 err = set_tod_ptp_pll(idtcm, 3, val); 1113 break; 1114 default: 1115 err = set_pll_output_mask(idtcm, regaddr, val); 1116 break; 1117 } 1118 1119 return err; 1120 } 1121 1122 static void display_pll_and_masks(struct idtcm *idtcm) 1123 { 1124 u8 i; 1125 u8 mask; 1126 1127 dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x\n", idtcm->tod_mask); 1128 1129 for (i = 0; i < MAX_TOD; i++) { 1130 mask = 1 << i; 1131 1132 if (mask & idtcm->tod_mask) 1133 dev_dbg(&idtcm->client->dev, 1134 "TOD%d pll = %d output_mask = 0x%04x\n", 1135 i, idtcm->channel[i].pll, 1136 idtcm->channel[i].output_mask); 1137 } 1138 } 1139 1140 static int idtcm_load_firmware(struct idtcm *idtcm, 1141 struct device *dev) 1142 { 1143 char fname[128] = FW_FILENAME; 1144 const struct firmware *fw; 1145 struct idtcm_fwrc *rec; 1146 u32 regaddr; 1147 int err; 1148 s32 len; 1149 u8 val; 1150 u8 loaddr; 1151 1152 if (firmware) /* module parameter */ 1153 snprintf(fname, sizeof(fname), "%s", firmware); 1154 1155 dev_dbg(&idtcm->client->dev, "requesting firmware '%s'\n", fname); 1156 1157 err = request_firmware(&fw, fname, dev); 1158 1159 if (err) { 1160 dev_err(&idtcm->client->dev, 1161 "Failed at line %d in func %s!\n", 1162 __LINE__, 1163 __func__); 1164 return err; 1165 } 1166 1167 dev_dbg(&idtcm->client->dev, "firmware size %zu bytes\n", fw->size); 1168 1169 rec = (struct idtcm_fwrc *) fw->data; 1170 1171 if (contains_full_configuration(fw)) 1172 idtcm_state_machine_reset(idtcm); 1173 1174 for (len = fw->size; len > 0; len -= sizeof(*rec)) { 1175 1176 if (rec->reserved) { 1177 dev_err(&idtcm->client->dev, 1178 "bad firmware, reserved field non-zero\n"); 1179 err = -EINVAL; 1180 } else { 1181 regaddr = rec->hiaddr << 8; 1182 regaddr |= rec->loaddr; 1183 1184 val = rec->value; 1185 loaddr = rec->loaddr; 1186 1187 rec++; 1188 1189 err = check_and_set_masks(idtcm, regaddr, val); 1190 } 1191 1192 if (err != -EINVAL) { 1193 err = 0; 1194 1195 /* Top (status registers) and bottom are read-only */ 1196 if ((regaddr < GPIO_USER_CONTROL) 1197 || (regaddr >= SCRATCH)) 1198 continue; 1199 1200 /* Page size 128, last 4 bytes of page skipped */ 1201 if (((loaddr > 0x7b) && (loaddr <= 0x7f)) 1202 || loaddr > 0xfb) 1203 continue; 1204 1205 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val)); 1206 } 1207 1208 if (err) 1209 goto out; 1210 } 1211 1212 display_pll_and_masks(idtcm); 1213 1214 out: 1215 release_firmware(fw); 1216 return err; 1217 } 1218 1219 static int idtcm_output_enable(struct idtcm_channel *channel, 1220 bool enable, unsigned int outn) 1221 { 1222 struct idtcm *idtcm = channel->idtcm; 1223 int err; 1224 u8 val; 1225 1226 err = idtcm_read(idtcm, OUTPUT_MODULE_FROM_INDEX(outn), 1227 OUT_CTRL_1, &val, sizeof(val)); 1228 1229 if (err) 1230 return err; 1231 1232 if (enable) 1233 val |= SQUELCH_DISABLE; 1234 else 1235 val &= ~SQUELCH_DISABLE; 1236 1237 return idtcm_write(idtcm, OUTPUT_MODULE_FROM_INDEX(outn), 1238 OUT_CTRL_1, &val, sizeof(val)); 1239 } 1240 1241 static int idtcm_output_mask_enable(struct idtcm_channel *channel, 1242 bool enable) 1243 { 1244 u16 mask; 1245 int err; 1246 u8 outn; 1247 1248 mask = channel->output_mask; 1249 outn = 0; 1250 1251 while (mask) { 1252 1253 if (mask & 0x1) { 1254 1255 err = idtcm_output_enable(channel, enable, outn); 1256 1257 if (err) 1258 return err; 1259 } 1260 1261 mask >>= 0x1; 1262 outn++; 1263 } 1264 1265 return 0; 1266 } 1267 1268 static int idtcm_perout_enable(struct idtcm_channel *channel, 1269 bool enable, 1270 struct ptp_perout_request *perout) 1271 { 1272 unsigned int flags = perout->flags; 1273 1274 if (flags == PEROUT_ENABLE_OUTPUT_MASK) 1275 return idtcm_output_mask_enable(channel, enable); 1276 1277 /* Enable/disable individual output instead */ 1278 return idtcm_output_enable(channel, enable, perout->index); 1279 } 1280 1281 static int idtcm_set_pll_mode(struct idtcm_channel *channel, 1282 enum pll_mode pll_mode) 1283 { 1284 struct idtcm *idtcm = channel->idtcm; 1285 int err; 1286 u8 dpll_mode; 1287 1288 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE, 1289 &dpll_mode, sizeof(dpll_mode)); 1290 if (err) 1291 return err; 1292 1293 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT); 1294 1295 dpll_mode |= (pll_mode << PLL_MODE_SHIFT); 1296 1297 channel->pll_mode = pll_mode; 1298 1299 err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE, 1300 &dpll_mode, sizeof(dpll_mode)); 1301 if (err) 1302 return err; 1303 1304 return 0; 1305 } 1306 1307 /* PTP Hardware Clock interface */ 1308 1309 /** 1310 * @brief Maximum absolute value for write phase offset in picoseconds 1311 * 1312 * Destination signed register is 32-bit register in resolution of 50ps 1313 * 1314 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350 1315 */ 1316 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns) 1317 { 1318 struct idtcm *idtcm = channel->idtcm; 1319 1320 int err; 1321 u8 i; 1322 u8 buf[4] = {0}; 1323 s32 phase_50ps; 1324 s64 offset_ps; 1325 1326 if (channel->pll_mode != PLL_MODE_WRITE_PHASE) { 1327 1328 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE); 1329 1330 if (err) 1331 return err; 1332 } 1333 1334 offset_ps = (s64)delta_ns * 1000; 1335 1336 /* 1337 * Check for 32-bit signed max * 50: 1338 * 1339 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350 1340 */ 1341 if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS) 1342 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS; 1343 else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS) 1344 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS; 1345 1346 phase_50ps = DIV_ROUND_CLOSEST(div64_s64(offset_ps, 50), 1); 1347 1348 for (i = 0; i < 4; i++) { 1349 buf[i] = phase_50ps & 0xff; 1350 phase_50ps >>= 8; 1351 } 1352 1353 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE, 1354 buf, sizeof(buf)); 1355 1356 return err; 1357 } 1358 1359 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm) 1360 { 1361 struct idtcm *idtcm = channel->idtcm; 1362 u8 i; 1363 bool neg_adj = 0; 1364 int err; 1365 u8 buf[6] = {0}; 1366 s64 fcw; 1367 1368 if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) { 1369 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY); 1370 if (err) 1371 return err; 1372 } 1373 1374 /* 1375 * Frequency Control Word unit is: 1.11 * 10^-10 ppm 1376 * 1377 * adjfreq: 1378 * ppb * 10^9 1379 * FCW = ---------- 1380 * 111 1381 * 1382 * adjfine: 1383 * ppm_16 * 5^12 1384 * FCW = ------------- 1385 * 111 * 2^4 1386 */ 1387 if (scaled_ppm < 0) { 1388 neg_adj = 1; 1389 scaled_ppm = -scaled_ppm; 1390 } 1391 1392 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */ 1393 fcw = scaled_ppm * 244140625ULL; 1394 1395 fcw = div_u64(fcw, 1776); 1396 1397 if (neg_adj) 1398 fcw = -fcw; 1399 1400 for (i = 0; i < 6; i++) { 1401 buf[i] = fcw & 0xff; 1402 fcw >>= 8; 1403 } 1404 1405 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ, 1406 buf, sizeof(buf)); 1407 1408 return err; 1409 } 1410 1411 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 1412 { 1413 struct idtcm_channel *channel = 1414 container_of(ptp, struct idtcm_channel, caps); 1415 struct idtcm *idtcm = channel->idtcm; 1416 int err; 1417 1418 mutex_lock(&idtcm->reg_lock); 1419 1420 err = _idtcm_gettime(channel, ts); 1421 1422 if (err) 1423 dev_err(&idtcm->client->dev, 1424 "Failed at line %d in func %s!\n", 1425 __LINE__, 1426 __func__); 1427 1428 mutex_unlock(&idtcm->reg_lock); 1429 1430 return err; 1431 } 1432 1433 static int idtcm_settime(struct ptp_clock_info *ptp, 1434 const struct timespec64 *ts) 1435 { 1436 struct idtcm_channel *channel = 1437 container_of(ptp, struct idtcm_channel, caps); 1438 struct idtcm *idtcm = channel->idtcm; 1439 int err; 1440 1441 mutex_lock(&idtcm->reg_lock); 1442 1443 err = _idtcm_settime(channel, ts); 1444 1445 if (err) 1446 dev_err(&idtcm->client->dev, 1447 "Failed at line %d in func %s!\n", 1448 __LINE__, 1449 __func__); 1450 1451 mutex_unlock(&idtcm->reg_lock); 1452 1453 return err; 1454 } 1455 1456 static int idtcm_settime_v487(struct ptp_clock_info *ptp, 1457 const struct timespec64 *ts) 1458 { 1459 struct idtcm_channel *channel = 1460 container_of(ptp, struct idtcm_channel, caps); 1461 struct idtcm *idtcm = channel->idtcm; 1462 int err; 1463 1464 mutex_lock(&idtcm->reg_lock); 1465 1466 err = _idtcm_settime_v487(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE); 1467 1468 if (err) 1469 dev_err(&idtcm->client->dev, 1470 "Failed at line %d in func %s!\n", 1471 __LINE__, 1472 __func__); 1473 1474 mutex_unlock(&idtcm->reg_lock); 1475 1476 return err; 1477 } 1478 1479 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta) 1480 { 1481 struct idtcm_channel *channel = 1482 container_of(ptp, struct idtcm_channel, caps); 1483 struct idtcm *idtcm = channel->idtcm; 1484 int err; 1485 1486 mutex_lock(&idtcm->reg_lock); 1487 1488 err = _idtcm_adjtime(channel, delta); 1489 1490 if (err) 1491 dev_err(&idtcm->client->dev, 1492 "Failed at line %d in func %s!\n", 1493 __LINE__, 1494 __func__); 1495 1496 mutex_unlock(&idtcm->reg_lock); 1497 1498 return err; 1499 } 1500 1501 static int idtcm_adjtime_v487(struct ptp_clock_info *ptp, s64 delta) 1502 { 1503 struct idtcm_channel *channel = 1504 container_of(ptp, struct idtcm_channel, caps); 1505 struct idtcm *idtcm = channel->idtcm; 1506 struct timespec64 ts; 1507 enum scsr_tod_write_type_sel type; 1508 int err; 1509 1510 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_V487) { 1511 err = idtcm_do_phase_pull_in(channel, delta, 0); 1512 if (err) 1513 dev_err(&idtcm->client->dev, 1514 "Failed at line %d in func %s!\n", 1515 __LINE__, 1516 __func__); 1517 return err; 1518 } 1519 1520 if (delta >= 0) { 1521 ts = ns_to_timespec64(delta); 1522 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS; 1523 } else { 1524 ts = ns_to_timespec64(-delta); 1525 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS; 1526 } 1527 1528 mutex_lock(&idtcm->reg_lock); 1529 1530 err = _idtcm_settime_v487(channel, &ts, type); 1531 1532 if (err) 1533 dev_err(&idtcm->client->dev, 1534 "Failed at line %d in func %s!\n", 1535 __LINE__, 1536 __func__); 1537 1538 mutex_unlock(&idtcm->reg_lock); 1539 1540 return err; 1541 } 1542 1543 static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta) 1544 { 1545 struct idtcm_channel *channel = 1546 container_of(ptp, struct idtcm_channel, caps); 1547 1548 struct idtcm *idtcm = channel->idtcm; 1549 1550 int err; 1551 1552 mutex_lock(&idtcm->reg_lock); 1553 1554 err = _idtcm_adjphase(channel, delta); 1555 1556 if (err) 1557 dev_err(&idtcm->client->dev, 1558 "Failed at line %d in func %s!\n", 1559 __LINE__, 1560 __func__); 1561 1562 mutex_unlock(&idtcm->reg_lock); 1563 1564 return err; 1565 } 1566 1567 static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 1568 { 1569 struct idtcm_channel *channel = 1570 container_of(ptp, struct idtcm_channel, caps); 1571 1572 struct idtcm *idtcm = channel->idtcm; 1573 1574 int err; 1575 1576 mutex_lock(&idtcm->reg_lock); 1577 1578 err = _idtcm_adjfine(channel, scaled_ppm); 1579 1580 if (err) 1581 dev_err(&idtcm->client->dev, 1582 "Failed at line %d in func %s!\n", 1583 __LINE__, 1584 __func__); 1585 1586 mutex_unlock(&idtcm->reg_lock); 1587 1588 return err; 1589 } 1590 1591 static int idtcm_enable(struct ptp_clock_info *ptp, 1592 struct ptp_clock_request *rq, int on) 1593 { 1594 int err; 1595 1596 struct idtcm_channel *channel = 1597 container_of(ptp, struct idtcm_channel, caps); 1598 1599 switch (rq->type) { 1600 case PTP_CLK_REQ_PEROUT: 1601 if (!on) { 1602 err = idtcm_perout_enable(channel, false, &rq->perout); 1603 if (err) 1604 dev_err(&channel->idtcm->client->dev, 1605 "Failed at line %d in func %s!\n", 1606 __LINE__, 1607 __func__); 1608 return err; 1609 } 1610 1611 /* Only accept a 1-PPS aligned to the second. */ 1612 if (rq->perout.start.nsec || rq->perout.period.sec != 1 || 1613 rq->perout.period.nsec) 1614 return -ERANGE; 1615 1616 err = idtcm_perout_enable(channel, true, &rq->perout); 1617 if (err) 1618 dev_err(&channel->idtcm->client->dev, 1619 "Failed at line %d in func %s!\n", 1620 __LINE__, 1621 __func__); 1622 return err; 1623 default: 1624 break; 1625 } 1626 1627 return -EOPNOTSUPP; 1628 } 1629 1630 static int _enable_pll_tod_sync(struct idtcm *idtcm, 1631 u8 pll, 1632 u8 sync_src, 1633 u8 qn, 1634 u8 qn_plus_1) 1635 { 1636 int err; 1637 u8 val; 1638 u16 dpll; 1639 u16 out0 = 0, out1 = 0; 1640 1641 if ((qn == 0) && (qn_plus_1 == 0)) 1642 return 0; 1643 1644 switch (pll) { 1645 case 0: 1646 dpll = DPLL_0; 1647 if (qn) 1648 out0 = OUTPUT_0; 1649 if (qn_plus_1) 1650 out1 = OUTPUT_1; 1651 break; 1652 case 1: 1653 dpll = DPLL_1; 1654 if (qn) 1655 out0 = OUTPUT_2; 1656 if (qn_plus_1) 1657 out1 = OUTPUT_3; 1658 break; 1659 case 2: 1660 dpll = DPLL_2; 1661 if (qn) 1662 out0 = OUTPUT_4; 1663 if (qn_plus_1) 1664 out1 = OUTPUT_5; 1665 break; 1666 case 3: 1667 dpll = DPLL_3; 1668 if (qn) 1669 out0 = OUTPUT_6; 1670 if (qn_plus_1) 1671 out1 = OUTPUT_7; 1672 break; 1673 case 4: 1674 dpll = DPLL_4; 1675 if (qn) 1676 out0 = OUTPUT_8; 1677 break; 1678 case 5: 1679 dpll = DPLL_5; 1680 if (qn) 1681 out0 = OUTPUT_9; 1682 if (qn_plus_1) 1683 out1 = OUTPUT_8; 1684 break; 1685 case 6: 1686 dpll = DPLL_6; 1687 if (qn) 1688 out0 = OUTPUT_10; 1689 if (qn_plus_1) 1690 out1 = OUTPUT_11; 1691 break; 1692 case 7: 1693 dpll = DPLL_7; 1694 if (qn) 1695 out0 = OUTPUT_11; 1696 break; 1697 default: 1698 return -EINVAL; 1699 } 1700 1701 /* 1702 * Enable OUTPUT OUT_SYNC. 1703 */ 1704 if (out0) { 1705 err = idtcm_read(idtcm, out0, OUT_CTRL_1, &val, sizeof(val)); 1706 1707 if (err) 1708 return err; 1709 1710 val &= ~OUT_SYNC_DISABLE; 1711 1712 err = idtcm_write(idtcm, out0, OUT_CTRL_1, &val, sizeof(val)); 1713 1714 if (err) 1715 return err; 1716 } 1717 1718 if (out1) { 1719 err = idtcm_read(idtcm, out1, OUT_CTRL_1, &val, sizeof(val)); 1720 1721 if (err) 1722 return err; 1723 1724 val &= ~OUT_SYNC_DISABLE; 1725 1726 err = idtcm_write(idtcm, out1, OUT_CTRL_1, &val, sizeof(val)); 1727 1728 if (err) 1729 return err; 1730 } 1731 1732 /* enable dpll sync tod pps, must be set before dpll_mode */ 1733 err = idtcm_read(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val)); 1734 if (err) 1735 return err; 1736 1737 val &= ~(TOD_SYNC_SOURCE_MASK << TOD_SYNC_SOURCE_SHIFT); 1738 val |= (sync_src << TOD_SYNC_SOURCE_SHIFT); 1739 val |= TOD_SYNC_EN; 1740 1741 return idtcm_write(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val)); 1742 } 1743 1744 static int idtcm_enable_tod_sync(struct idtcm_channel *channel) 1745 { 1746 struct idtcm *idtcm = channel->idtcm; 1747 1748 u8 pll; 1749 u8 sync_src; 1750 u8 qn; 1751 u8 qn_plus_1; 1752 u8 cfg; 1753 int err = 0; 1754 u16 output_mask = channel->output_mask; 1755 u8 out8_mux = 0; 1756 u8 out11_mux = 0; 1757 u8 temp; 1758 1759 /* 1760 * set tod_out_sync_enable to 0. 1761 */ 1762 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg)); 1763 if (err) 1764 return err; 1765 1766 cfg &= ~TOD_OUT_SYNC_ENABLE; 1767 1768 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg)); 1769 if (err) 1770 return err; 1771 1772 switch (channel->tod_n) { 1773 case TOD_0: 1774 sync_src = 0; 1775 break; 1776 case TOD_1: 1777 sync_src = 1; 1778 break; 1779 case TOD_2: 1780 sync_src = 2; 1781 break; 1782 case TOD_3: 1783 sync_src = 3; 1784 break; 1785 default: 1786 return -EINVAL; 1787 } 1788 1789 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE, 1790 &temp, sizeof(temp)); 1791 if (err) 1792 return err; 1793 1794 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) == 1795 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) 1796 out8_mux = 1; 1797 1798 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE, 1799 &temp, sizeof(temp)); 1800 if (err) 1801 return err; 1802 1803 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) == 1804 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) 1805 out11_mux = 1; 1806 1807 for (pll = 0; pll < 8; pll++) { 1808 qn = 0; 1809 qn_plus_1 = 0; 1810 1811 if (pll < 4) { 1812 /* First 4 pll has 2 outputs */ 1813 qn = output_mask & 0x1; 1814 output_mask = output_mask >> 1; 1815 qn_plus_1 = output_mask & 0x1; 1816 output_mask = output_mask >> 1; 1817 } else if (pll == 4) { 1818 if (out8_mux == 0) { 1819 qn = output_mask & 0x1; 1820 output_mask = output_mask >> 1; 1821 } 1822 } else if (pll == 5) { 1823 if (out8_mux) { 1824 qn_plus_1 = output_mask & 0x1; 1825 output_mask = output_mask >> 1; 1826 } 1827 qn = output_mask & 0x1; 1828 output_mask = output_mask >> 1; 1829 } else if (pll == 6) { 1830 qn = output_mask & 0x1; 1831 output_mask = output_mask >> 1; 1832 if (out11_mux) { 1833 qn_plus_1 = output_mask & 0x1; 1834 output_mask = output_mask >> 1; 1835 } 1836 } else if (pll == 7) { 1837 if (out11_mux == 0) { 1838 qn = output_mask & 0x1; 1839 output_mask = output_mask >> 1; 1840 } 1841 } 1842 1843 if ((qn != 0) || (qn_plus_1 != 0)) 1844 err = _enable_pll_tod_sync(idtcm, pll, sync_src, qn, 1845 qn_plus_1); 1846 1847 if (err) 1848 return err; 1849 } 1850 1851 return err; 1852 } 1853 1854 static int idtcm_enable_tod(struct idtcm_channel *channel) 1855 { 1856 struct idtcm *idtcm = channel->idtcm; 1857 struct timespec64 ts = {0, 0}; 1858 u8 cfg; 1859 int err; 1860 1861 /* 1862 * Start the TOD clock ticking. 1863 */ 1864 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg)); 1865 if (err) 1866 return err; 1867 1868 cfg |= TOD_ENABLE; 1869 1870 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg)); 1871 if (err) 1872 return err; 1873 1874 return _idtcm_settime(channel, &ts); 1875 } 1876 1877 static void idtcm_display_version_info(struct idtcm *idtcm) 1878 { 1879 u8 major; 1880 u8 minor; 1881 u8 hotfix; 1882 u16 product_id; 1883 u8 hw_rev_id; 1884 u8 config_select; 1885 char *fmt = "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d\n"; 1886 1887 idtcm_read_major_release(idtcm, &major); 1888 idtcm_read_minor_release(idtcm, &minor); 1889 idtcm_read_hotfix_release(idtcm, &hotfix); 1890 1891 idtcm_read_product_id(idtcm, &product_id); 1892 idtcm_read_hw_rev_id(idtcm, &hw_rev_id); 1893 1894 idtcm_read_otp_scsr_config_select(idtcm, &config_select); 1895 1896 snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u", 1897 major, minor, hotfix); 1898 1899 dev_info(&idtcm->client->dev, fmt, major, minor, hotfix, 1900 product_id, hw_rev_id, config_select); 1901 } 1902 1903 static const struct ptp_clock_info idtcm_caps_v487 = { 1904 .owner = THIS_MODULE, 1905 .max_adj = 244000, 1906 .n_per_out = 12, 1907 .adjphase = &idtcm_adjphase, 1908 .adjfine = &idtcm_adjfine, 1909 .adjtime = &idtcm_adjtime_v487, 1910 .gettime64 = &idtcm_gettime, 1911 .settime64 = &idtcm_settime_v487, 1912 .enable = &idtcm_enable, 1913 }; 1914 1915 static const struct ptp_clock_info idtcm_caps = { 1916 .owner = THIS_MODULE, 1917 .max_adj = 244000, 1918 .n_per_out = 12, 1919 .adjphase = &idtcm_adjphase, 1920 .adjfine = &idtcm_adjfine, 1921 .adjtime = &idtcm_adjtime, 1922 .gettime64 = &idtcm_gettime, 1923 .settime64 = &idtcm_settime, 1924 .enable = &idtcm_enable, 1925 }; 1926 1927 static int configure_channel_pll(struct idtcm_channel *channel) 1928 { 1929 int err = 0; 1930 1931 switch (channel->pll) { 1932 case 0: 1933 channel->dpll_freq = DPLL_FREQ_0; 1934 channel->dpll_n = DPLL_0; 1935 channel->hw_dpll_n = HW_DPLL_0; 1936 channel->dpll_phase = DPLL_PHASE_0; 1937 channel->dpll_ctrl_n = DPLL_CTRL_0; 1938 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0; 1939 break; 1940 case 1: 1941 channel->dpll_freq = DPLL_FREQ_1; 1942 channel->dpll_n = DPLL_1; 1943 channel->hw_dpll_n = HW_DPLL_1; 1944 channel->dpll_phase = DPLL_PHASE_1; 1945 channel->dpll_ctrl_n = DPLL_CTRL_1; 1946 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1; 1947 break; 1948 case 2: 1949 channel->dpll_freq = DPLL_FREQ_2; 1950 channel->dpll_n = DPLL_2; 1951 channel->hw_dpll_n = HW_DPLL_2; 1952 channel->dpll_phase = DPLL_PHASE_2; 1953 channel->dpll_ctrl_n = DPLL_CTRL_2; 1954 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2; 1955 break; 1956 case 3: 1957 channel->dpll_freq = DPLL_FREQ_3; 1958 channel->dpll_n = DPLL_3; 1959 channel->hw_dpll_n = HW_DPLL_3; 1960 channel->dpll_phase = DPLL_PHASE_3; 1961 channel->dpll_ctrl_n = DPLL_CTRL_3; 1962 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3; 1963 break; 1964 case 4: 1965 channel->dpll_freq = DPLL_FREQ_4; 1966 channel->dpll_n = DPLL_4; 1967 channel->hw_dpll_n = HW_DPLL_4; 1968 channel->dpll_phase = DPLL_PHASE_4; 1969 channel->dpll_ctrl_n = DPLL_CTRL_4; 1970 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4; 1971 break; 1972 case 5: 1973 channel->dpll_freq = DPLL_FREQ_5; 1974 channel->dpll_n = DPLL_5; 1975 channel->hw_dpll_n = HW_DPLL_5; 1976 channel->dpll_phase = DPLL_PHASE_5; 1977 channel->dpll_ctrl_n = DPLL_CTRL_5; 1978 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5; 1979 break; 1980 case 6: 1981 channel->dpll_freq = DPLL_FREQ_6; 1982 channel->dpll_n = DPLL_6; 1983 channel->hw_dpll_n = HW_DPLL_6; 1984 channel->dpll_phase = DPLL_PHASE_6; 1985 channel->dpll_ctrl_n = DPLL_CTRL_6; 1986 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6; 1987 break; 1988 case 7: 1989 channel->dpll_freq = DPLL_FREQ_7; 1990 channel->dpll_n = DPLL_7; 1991 channel->hw_dpll_n = HW_DPLL_7; 1992 channel->dpll_phase = DPLL_PHASE_7; 1993 channel->dpll_ctrl_n = DPLL_CTRL_7; 1994 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7; 1995 break; 1996 default: 1997 err = -EINVAL; 1998 } 1999 2000 return err; 2001 } 2002 2003 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) 2004 { 2005 struct idtcm_channel *channel; 2006 int err; 2007 2008 if (!(index < MAX_TOD)) 2009 return -EINVAL; 2010 2011 channel = &idtcm->channel[index]; 2012 2013 /* Set pll addresses */ 2014 err = configure_channel_pll(channel); 2015 if (err) 2016 return err; 2017 2018 /* Set tod addresses */ 2019 switch (index) { 2020 case 0: 2021 channel->tod_read_primary = TOD_READ_PRIMARY_0; 2022 channel->tod_write = TOD_WRITE_0; 2023 channel->tod_n = TOD_0; 2024 break; 2025 case 1: 2026 channel->tod_read_primary = TOD_READ_PRIMARY_1; 2027 channel->tod_write = TOD_WRITE_1; 2028 channel->tod_n = TOD_1; 2029 break; 2030 case 2: 2031 channel->tod_read_primary = TOD_READ_PRIMARY_2; 2032 channel->tod_write = TOD_WRITE_2; 2033 channel->tod_n = TOD_2; 2034 break; 2035 case 3: 2036 channel->tod_read_primary = TOD_READ_PRIMARY_3; 2037 channel->tod_write = TOD_WRITE_3; 2038 channel->tod_n = TOD_3; 2039 break; 2040 default: 2041 return -EINVAL; 2042 } 2043 2044 channel->idtcm = idtcm; 2045 2046 if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0) 2047 channel->caps = idtcm_caps_v487; 2048 else 2049 channel->caps = idtcm_caps; 2050 2051 snprintf(channel->caps.name, sizeof(channel->caps.name), 2052 "IDT CM TOD%u", index); 2053 2054 if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0) { 2055 err = idtcm_enable_tod_sync(channel); 2056 if (err) { 2057 dev_err(&idtcm->client->dev, 2058 "Failed at line %d in func %s!\n", 2059 __LINE__, 2060 __func__); 2061 return err; 2062 } 2063 } 2064 2065 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY); 2066 if (err) { 2067 dev_err(&idtcm->client->dev, 2068 "Failed at line %d in func %s!\n", 2069 __LINE__, 2070 __func__); 2071 return err; 2072 } 2073 2074 err = idtcm_enable_tod(channel); 2075 if (err) { 2076 dev_err(&idtcm->client->dev, 2077 "Failed at line %d in func %s!\n", 2078 __LINE__, 2079 __func__); 2080 return err; 2081 } 2082 2083 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL); 2084 2085 if (IS_ERR(channel->ptp_clock)) { 2086 err = PTR_ERR(channel->ptp_clock); 2087 channel->ptp_clock = NULL; 2088 return err; 2089 } 2090 2091 if (!channel->ptp_clock) 2092 return -ENOTSUPP; 2093 2094 dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d\n", 2095 index, channel->ptp_clock->index); 2096 2097 return 0; 2098 } 2099 2100 static void ptp_clock_unregister_all(struct idtcm *idtcm) 2101 { 2102 u8 i; 2103 struct idtcm_channel *channel; 2104 2105 for (i = 0; i < MAX_TOD; i++) { 2106 2107 channel = &idtcm->channel[i]; 2108 2109 if (channel->ptp_clock) 2110 ptp_clock_unregister(channel->ptp_clock); 2111 } 2112 } 2113 2114 static void set_default_masks(struct idtcm *idtcm) 2115 { 2116 idtcm->tod_mask = DEFAULT_TOD_MASK; 2117 2118 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL; 2119 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL; 2120 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL; 2121 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL; 2122 2123 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0; 2124 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1; 2125 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2; 2126 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3; 2127 } 2128 2129 static int idtcm_probe(struct i2c_client *client, 2130 const struct i2c_device_id *id) 2131 { 2132 struct idtcm *idtcm; 2133 int err; 2134 u8 i; 2135 char *fmt = "Failed at %d in line %s with channel output %d!\n"; 2136 2137 /* Unused for now */ 2138 (void)id; 2139 2140 idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL); 2141 2142 if (!idtcm) 2143 return -ENOMEM; 2144 2145 idtcm->client = client; 2146 idtcm->page_offset = 0xff; 2147 idtcm->calculate_overhead_flag = 0; 2148 2149 set_default_masks(idtcm); 2150 2151 mutex_init(&idtcm->reg_lock); 2152 mutex_lock(&idtcm->reg_lock); 2153 2154 idtcm_display_version_info(idtcm); 2155 2156 err = idtcm_load_firmware(idtcm, &client->dev); 2157 2158 if (err) 2159 dev_warn(&idtcm->client->dev, 2160 "loading firmware failed with %d\n", err); 2161 2162 if (wait_for_boot_status_ready(idtcm)) 2163 dev_warn(&idtcm->client->dev, "BOOT_STATUS != 0xA0\n"); 2164 2165 if (idtcm->tod_mask) { 2166 for (i = 0; i < MAX_TOD; i++) { 2167 if (idtcm->tod_mask & (1 << i)) { 2168 err = idtcm_enable_channel(idtcm, i); 2169 if (err) { 2170 dev_err(&idtcm->client->dev, 2171 fmt, 2172 __LINE__, 2173 __func__, 2174 i); 2175 break; 2176 } 2177 } 2178 } 2179 } else { 2180 dev_err(&idtcm->client->dev, 2181 "no PLLs flagged as PHCs, nothing to do\n"); 2182 err = -ENODEV; 2183 } 2184 2185 mutex_unlock(&idtcm->reg_lock); 2186 2187 if (err) { 2188 ptp_clock_unregister_all(idtcm); 2189 return err; 2190 } 2191 2192 i2c_set_clientdata(client, idtcm); 2193 2194 return 0; 2195 } 2196 2197 static int idtcm_remove(struct i2c_client *client) 2198 { 2199 struct idtcm *idtcm = i2c_get_clientdata(client); 2200 2201 ptp_clock_unregister_all(idtcm); 2202 2203 mutex_destroy(&idtcm->reg_lock); 2204 2205 return 0; 2206 } 2207 2208 #ifdef CONFIG_OF 2209 static const struct of_device_id idtcm_dt_id[] = { 2210 { .compatible = "idt,8a34000" }, 2211 { .compatible = "idt,8a34001" }, 2212 { .compatible = "idt,8a34002" }, 2213 { .compatible = "idt,8a34003" }, 2214 { .compatible = "idt,8a34004" }, 2215 { .compatible = "idt,8a34005" }, 2216 { .compatible = "idt,8a34006" }, 2217 { .compatible = "idt,8a34007" }, 2218 { .compatible = "idt,8a34008" }, 2219 { .compatible = "idt,8a34009" }, 2220 { .compatible = "idt,8a34010" }, 2221 { .compatible = "idt,8a34011" }, 2222 { .compatible = "idt,8a34012" }, 2223 { .compatible = "idt,8a34013" }, 2224 { .compatible = "idt,8a34014" }, 2225 { .compatible = "idt,8a34015" }, 2226 { .compatible = "idt,8a34016" }, 2227 { .compatible = "idt,8a34017" }, 2228 { .compatible = "idt,8a34018" }, 2229 { .compatible = "idt,8a34019" }, 2230 { .compatible = "idt,8a34040" }, 2231 { .compatible = "idt,8a34041" }, 2232 { .compatible = "idt,8a34042" }, 2233 { .compatible = "idt,8a34043" }, 2234 { .compatible = "idt,8a34044" }, 2235 { .compatible = "idt,8a34045" }, 2236 { .compatible = "idt,8a34046" }, 2237 { .compatible = "idt,8a34047" }, 2238 { .compatible = "idt,8a34048" }, 2239 { .compatible = "idt,8a34049" }, 2240 {}, 2241 }; 2242 MODULE_DEVICE_TABLE(of, idtcm_dt_id); 2243 #endif 2244 2245 static const struct i2c_device_id idtcm_i2c_id[] = { 2246 { "8a34000" }, 2247 { "8a34001" }, 2248 { "8a34002" }, 2249 { "8a34003" }, 2250 { "8a34004" }, 2251 { "8a34005" }, 2252 { "8a34006" }, 2253 { "8a34007" }, 2254 { "8a34008" }, 2255 { "8a34009" }, 2256 { "8a34010" }, 2257 { "8a34011" }, 2258 { "8a34012" }, 2259 { "8a34013" }, 2260 { "8a34014" }, 2261 { "8a34015" }, 2262 { "8a34016" }, 2263 { "8a34017" }, 2264 { "8a34018" }, 2265 { "8a34019" }, 2266 { "8a34040" }, 2267 { "8a34041" }, 2268 { "8a34042" }, 2269 { "8a34043" }, 2270 { "8a34044" }, 2271 { "8a34045" }, 2272 { "8a34046" }, 2273 { "8a34047" }, 2274 { "8a34048" }, 2275 { "8a34049" }, 2276 {}, 2277 }; 2278 MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id); 2279 2280 static struct i2c_driver idtcm_driver = { 2281 .driver = { 2282 .of_match_table = of_match_ptr(idtcm_dt_id), 2283 .name = "idtcm", 2284 }, 2285 .probe = idtcm_probe, 2286 .remove = idtcm_remove, 2287 .id_table = idtcm_i2c_id, 2288 }; 2289 2290 module_i2c_driver(idtcm_driver); 2291