1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and 4 * synchronization devices. 5 * 6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. 7 */ 8 #include <linux/firmware.h> 9 #include <linux/i2c.h> 10 #include <linux/module.h> 11 #include <linux/ptp_clock_kernel.h> 12 #include <linux/delay.h> 13 #include <linux/jiffies.h> 14 #include <linux/kernel.h> 15 #include <linux/timekeeping.h> 16 #include <linux/string.h> 17 18 #include "ptp_private.h" 19 #include "ptp_clockmatrix.h" 20 21 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family"); 22 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); 23 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>"); 24 MODULE_VERSION("1.0"); 25 MODULE_LICENSE("GPL"); 26 27 /* 28 * The name of the firmware file to be loaded 29 * over-rides any automatic selection 30 */ 31 static char *firmware; 32 module_param(firmware, charp, 0); 33 34 #define SETTIME_CORRECTION (0) 35 36 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm); 37 38 static int contains_full_configuration(struct idtcm *idtcm, 39 const struct firmware *fw) 40 { 41 struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data; 42 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH); 43 s32 full_count; 44 s32 count = 0; 45 u16 regaddr; 46 u8 loaddr; 47 s32 len; 48 49 /* 4 bytes skipped every 0x80 */ 50 full_count = (scratch - GPIO_USER_CONTROL) - 51 ((scratch >> 7) - (GPIO_USER_CONTROL >> 7)) * 4; 52 53 /* If the firmware contains 'full configuration' SM_RESET can be used 54 * to ensure proper configuration. 55 * 56 * Full configuration is defined as the number of programmable 57 * bytes within the configuration range minus page offset addr range. 58 */ 59 for (len = fw->size; len > 0; len -= sizeof(*rec)) { 60 regaddr = rec->hiaddr << 8; 61 regaddr |= rec->loaddr; 62 63 loaddr = rec->loaddr; 64 65 rec++; 66 67 /* Top (status registers) and bottom are read-only */ 68 if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch) 69 continue; 70 71 /* Page size 128, last 4 bytes of page skipped */ 72 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb) 73 continue; 74 75 count++; 76 } 77 78 return (count >= full_count); 79 } 80 81 static int char_array_to_timespec(u8 *buf, 82 u8 count, 83 struct timespec64 *ts) 84 { 85 u8 i; 86 u64 nsec; 87 time64_t sec; 88 89 if (count < TOD_BYTE_COUNT) 90 return 1; 91 92 /* Sub-nanoseconds are in buf[0]. */ 93 nsec = buf[4]; 94 for (i = 0; i < 3; i++) { 95 nsec <<= 8; 96 nsec |= buf[3 - i]; 97 } 98 99 sec = buf[10]; 100 for (i = 0; i < 5; i++) { 101 sec <<= 8; 102 sec |= buf[9 - i]; 103 } 104 105 ts->tv_sec = sec; 106 ts->tv_nsec = nsec; 107 108 return 0; 109 } 110 111 static int timespec_to_char_array(struct timespec64 const *ts, 112 u8 *buf, 113 u8 count) 114 { 115 u8 i; 116 s32 nsec; 117 time64_t sec; 118 119 if (count < TOD_BYTE_COUNT) 120 return 1; 121 122 nsec = ts->tv_nsec; 123 sec = ts->tv_sec; 124 125 /* Sub-nanoseconds are in buf[0]. */ 126 buf[0] = 0; 127 for (i = 1; i < 5; i++) { 128 buf[i] = nsec & 0xff; 129 nsec >>= 8; 130 } 131 132 for (i = 5; i < TOD_BYTE_COUNT; i++) { 133 134 buf[i] = sec & 0xff; 135 sec >>= 8; 136 } 137 138 return 0; 139 } 140 141 static int idtcm_strverscmp(const char *version1, const char *version2) 142 { 143 u8 ver1[3], ver2[3]; 144 int i; 145 146 if (sscanf(version1, "%hhu.%hhu.%hhu", 147 &ver1[0], &ver1[1], &ver1[2]) != 3) 148 return -1; 149 if (sscanf(version2, "%hhu.%hhu.%hhu", 150 &ver2[0], &ver2[1], &ver2[2]) != 3) 151 return -1; 152 153 for (i = 0; i < 3; i++) { 154 if (ver1[i] > ver2[i]) 155 return 1; 156 if (ver1[i] < ver2[i]) 157 return -1; 158 } 159 160 return 0; 161 } 162 163 static enum fw_version idtcm_fw_version(const char *version) 164 { 165 enum fw_version ver = V_DEFAULT; 166 167 if (idtcm_strverscmp(version, "4.8.7") >= 0) 168 ver = V487; 169 170 if (idtcm_strverscmp(version, "5.2.0") >= 0) 171 ver = V520; 172 173 return ver; 174 } 175 176 static int idtcm_xfer_read(struct idtcm *idtcm, 177 u8 regaddr, 178 u8 *buf, 179 u16 count) 180 { 181 struct i2c_client *client = idtcm->client; 182 struct i2c_msg msg[2]; 183 int cnt; 184 185 msg[0].addr = client->addr; 186 msg[0].flags = 0; 187 msg[0].len = 1; 188 msg[0].buf = ®addr; 189 190 msg[1].addr = client->addr; 191 msg[1].flags = I2C_M_RD; 192 msg[1].len = count; 193 msg[1].buf = buf; 194 195 cnt = i2c_transfer(client->adapter, msg, 2); 196 197 if (cnt < 0) { 198 dev_err(&client->dev, 199 "i2c_transfer failed at %d in %s, at addr: %04x!", 200 __LINE__, __func__, regaddr); 201 return cnt; 202 } else if (cnt != 2) { 203 dev_err(&client->dev, 204 "i2c_transfer sent only %d of %d messages", cnt, 2); 205 return -EIO; 206 } 207 208 return 0; 209 } 210 211 static int idtcm_xfer_write(struct idtcm *idtcm, 212 u8 regaddr, 213 u8 *buf, 214 u16 count) 215 { 216 struct i2c_client *client = idtcm->client; 217 /* we add 1 byte for device register */ 218 u8 msg[IDTCM_MAX_WRITE_COUNT + 1]; 219 int cnt; 220 221 if (count > IDTCM_MAX_WRITE_COUNT) 222 return -EINVAL; 223 224 msg[0] = regaddr; 225 memcpy(&msg[1], buf, count); 226 227 cnt = i2c_master_send(client, msg, count + 1); 228 229 if (cnt < 0) { 230 dev_err(&client->dev, 231 "i2c_master_send failed at %d in %s, at addr: %04x!", 232 __LINE__, __func__, regaddr); 233 return cnt; 234 } 235 236 return 0; 237 } 238 239 static int idtcm_page_offset(struct idtcm *idtcm, u8 val) 240 { 241 u8 buf[4]; 242 int err; 243 244 if (idtcm->page_offset == val) 245 return 0; 246 247 buf[0] = 0x0; 248 buf[1] = val; 249 buf[2] = 0x10; 250 buf[3] = 0x20; 251 252 err = idtcm_xfer_write(idtcm, PAGE_ADDR, buf, sizeof(buf)); 253 if (err) { 254 idtcm->page_offset = 0xff; 255 dev_err(&idtcm->client->dev, "failed to set page offset"); 256 } else { 257 idtcm->page_offset = val; 258 } 259 260 return err; 261 } 262 263 static int _idtcm_rdwr(struct idtcm *idtcm, 264 u16 regaddr, 265 u8 *buf, 266 u16 count, 267 bool write) 268 { 269 u8 hi; 270 u8 lo; 271 int err; 272 273 hi = (regaddr >> 8) & 0xff; 274 lo = regaddr & 0xff; 275 276 err = idtcm_page_offset(idtcm, hi); 277 if (err) 278 return err; 279 280 if (write) 281 return idtcm_xfer_write(idtcm, lo, buf, count); 282 283 return idtcm_xfer_read(idtcm, lo, buf, count); 284 } 285 286 static int idtcm_read(struct idtcm *idtcm, 287 u16 module, 288 u16 regaddr, 289 u8 *buf, 290 u16 count) 291 { 292 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false); 293 } 294 295 static int idtcm_write(struct idtcm *idtcm, 296 u16 module, 297 u16 regaddr, 298 u8 *buf, 299 u16 count) 300 { 301 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true); 302 } 303 304 static int clear_boot_status(struct idtcm *idtcm) 305 { 306 u8 buf[4] = {0}; 307 308 return idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf)); 309 } 310 311 static int read_boot_status(struct idtcm *idtcm, u32 *status) 312 { 313 int err; 314 u8 buf[4] = {0}; 315 316 err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf)); 317 318 *status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 319 320 return err; 321 } 322 323 static int wait_for_boot_status_ready(struct idtcm *idtcm) 324 { 325 u32 status = 0; 326 u8 i = 30; /* 30 * 100ms = 3s */ 327 int err; 328 329 do { 330 err = read_boot_status(idtcm, &status); 331 if (err) 332 return err; 333 334 if (status == 0xA0) 335 return 0; 336 337 msleep(100); 338 i--; 339 340 } while (i); 341 342 dev_warn(&idtcm->client->dev, "%s timed out", __func__); 343 344 return -EBUSY; 345 } 346 347 static int read_sys_apll_status(struct idtcm *idtcm, u8 *status) 348 { 349 return idtcm_read(idtcm, STATUS, DPLL_SYS_APLL_STATUS, status, 350 sizeof(u8)); 351 } 352 353 static int read_sys_dpll_status(struct idtcm *idtcm, u8 *status) 354 { 355 return idtcm_read(idtcm, STATUS, DPLL_SYS_STATUS, status, sizeof(u8)); 356 } 357 358 static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm) 359 { 360 unsigned long timeout = jiffies + msecs_to_jiffies(LOCK_TIMEOUT_MS); 361 u8 apll = 0; 362 u8 dpll = 0; 363 int err; 364 365 do { 366 err = read_sys_apll_status(idtcm, &apll); 367 if (err) 368 return err; 369 370 err = read_sys_dpll_status(idtcm, &dpll); 371 if (err) 372 return err; 373 374 apll &= SYS_APLL_LOSS_LOCK_LIVE_MASK; 375 dpll &= DPLL_SYS_STATE_MASK; 376 377 if (apll == SYS_APLL_LOSS_LOCK_LIVE_LOCKED && 378 dpll == DPLL_STATE_LOCKED) { 379 return 0; 380 } else if (dpll == DPLL_STATE_FREERUN || 381 dpll == DPLL_STATE_HOLDOVER || 382 dpll == DPLL_STATE_OPEN_LOOP) { 383 dev_warn(&idtcm->client->dev, 384 "No wait state: DPLL_SYS_STATE %d", dpll); 385 return -EPERM; 386 } 387 388 msleep(LOCK_POLL_INTERVAL_MS); 389 } while (time_is_after_jiffies(timeout)); 390 391 dev_warn(&idtcm->client->dev, 392 "%d ms lock timeout: SYS APLL Loss Lock %d SYS DPLL state %d", 393 LOCK_TIMEOUT_MS, apll, dpll); 394 395 return -ETIME; 396 } 397 398 static void wait_for_chip_ready(struct idtcm *idtcm) 399 { 400 if (wait_for_boot_status_ready(idtcm)) 401 dev_warn(&idtcm->client->dev, "BOOT_STATUS != 0xA0"); 402 403 if (wait_for_sys_apll_dpll_lock(idtcm)) 404 dev_warn(&idtcm->client->dev, 405 "Continuing while SYS APLL/DPLL is not locked"); 406 } 407 408 static int _idtcm_gettime(struct idtcm_channel *channel, 409 struct timespec64 *ts) 410 { 411 struct idtcm *idtcm = channel->idtcm; 412 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD); 413 u8 buf[TOD_BYTE_COUNT]; 414 u8 timeout = 10; 415 u8 trigger; 416 int err; 417 418 err = idtcm_read(idtcm, channel->tod_read_primary, 419 tod_read_cmd, &trigger, sizeof(trigger)); 420 if (err) 421 return err; 422 423 trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT); 424 trigger |= (1 << TOD_READ_TRIGGER_SHIFT); 425 trigger &= ~TOD_READ_TRIGGER_MODE; /* single shot */ 426 427 err = idtcm_write(idtcm, channel->tod_read_primary, 428 tod_read_cmd, &trigger, sizeof(trigger)); 429 if (err) 430 return err; 431 432 /* wait trigger to be 0 */ 433 while (trigger & TOD_READ_TRIGGER_MASK) { 434 if (idtcm->calculate_overhead_flag) 435 idtcm->start_time = ktime_get_raw(); 436 437 err = idtcm_read(idtcm, channel->tod_read_primary, 438 tod_read_cmd, &trigger, 439 sizeof(trigger)); 440 if (err) 441 return err; 442 443 if (--timeout == 0) 444 return -EIO; 445 } 446 447 err = idtcm_read(idtcm, channel->tod_read_primary, 448 TOD_READ_PRIMARY, buf, sizeof(buf)); 449 if (err) 450 return err; 451 452 err = char_array_to_timespec(buf, sizeof(buf), ts); 453 454 return err; 455 } 456 457 static int _sync_pll_output(struct idtcm *idtcm, 458 u8 pll, 459 u8 sync_src, 460 u8 qn, 461 u8 qn_plus_1) 462 { 463 int err; 464 u8 val; 465 u16 sync_ctrl0; 466 u16 sync_ctrl1; 467 u8 temp; 468 469 if (qn == 0 && qn_plus_1 == 0) 470 return 0; 471 472 switch (pll) { 473 case 0: 474 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0; 475 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1; 476 break; 477 case 1: 478 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0; 479 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1; 480 break; 481 case 2: 482 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0; 483 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1; 484 break; 485 case 3: 486 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0; 487 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1; 488 break; 489 case 4: 490 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0; 491 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1; 492 break; 493 case 5: 494 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0; 495 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1; 496 break; 497 case 6: 498 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0; 499 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1; 500 break; 501 case 7: 502 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0; 503 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1; 504 break; 505 default: 506 return -EINVAL; 507 } 508 509 val = SYNCTRL1_MASTER_SYNC_RST; 510 511 /* Place master sync in reset */ 512 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 513 if (err) 514 return err; 515 516 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src)); 517 if (err) 518 return err; 519 520 /* Set sync trigger mask */ 521 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG; 522 523 if (qn) 524 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG; 525 526 if (qn_plus_1) 527 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG; 528 529 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 530 if (err) 531 return err; 532 533 /* PLL5 can have OUT8 as second additional output. */ 534 if (pll == 5 && qn_plus_1 != 0) { 535 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE, 536 &temp, sizeof(temp)); 537 if (err) 538 return err; 539 540 temp &= ~(Q9_TO_Q8_SYNC_TRIG); 541 542 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE, 543 &temp, sizeof(temp)); 544 if (err) 545 return err; 546 547 temp |= Q9_TO_Q8_SYNC_TRIG; 548 549 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE, 550 &temp, sizeof(temp)); 551 if (err) 552 return err; 553 } 554 555 /* PLL6 can have OUT11 as second additional output. */ 556 if (pll == 6 && qn_plus_1 != 0) { 557 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE, 558 &temp, sizeof(temp)); 559 if (err) 560 return err; 561 562 temp &= ~(Q10_TO_Q11_SYNC_TRIG); 563 564 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE, 565 &temp, sizeof(temp)); 566 if (err) 567 return err; 568 569 temp |= Q10_TO_Q11_SYNC_TRIG; 570 571 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE, 572 &temp, sizeof(temp)); 573 if (err) 574 return err; 575 } 576 577 /* Place master sync out of reset */ 578 val &= ~(SYNCTRL1_MASTER_SYNC_RST); 579 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 580 581 return err; 582 } 583 584 static int idtcm_sync_pps_output(struct idtcm_channel *channel) 585 { 586 struct idtcm *idtcm = channel->idtcm; 587 u8 pll; 588 u8 qn; 589 u8 qn_plus_1; 590 int err = 0; 591 u8 out8_mux = 0; 592 u8 out11_mux = 0; 593 u8 temp; 594 u16 output_mask = channel->output_mask; 595 596 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE, 597 &temp, sizeof(temp)); 598 if (err) 599 return err; 600 601 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) == 602 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) 603 out8_mux = 1; 604 605 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE, 606 &temp, sizeof(temp)); 607 if (err) 608 return err; 609 610 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) == 611 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) 612 out11_mux = 1; 613 614 for (pll = 0; pll < 8; pll++) { 615 qn = 0; 616 qn_plus_1 = 0; 617 618 if (pll < 4) { 619 /* First 4 pll has 2 outputs */ 620 qn = output_mask & 0x1; 621 output_mask = output_mask >> 1; 622 qn_plus_1 = output_mask & 0x1; 623 output_mask = output_mask >> 1; 624 } else if (pll == 4) { 625 if (out8_mux == 0) { 626 qn = output_mask & 0x1; 627 output_mask = output_mask >> 1; 628 } 629 } else if (pll == 5) { 630 if (out8_mux) { 631 qn_plus_1 = output_mask & 0x1; 632 output_mask = output_mask >> 1; 633 } 634 qn = output_mask & 0x1; 635 output_mask = output_mask >> 1; 636 } else if (pll == 6) { 637 qn = output_mask & 0x1; 638 output_mask = output_mask >> 1; 639 if (out11_mux) { 640 qn_plus_1 = output_mask & 0x1; 641 output_mask = output_mask >> 1; 642 } 643 } else if (pll == 7) { 644 if (out11_mux == 0) { 645 qn = output_mask & 0x1; 646 output_mask = output_mask >> 1; 647 } 648 } 649 650 if (qn != 0 || qn_plus_1 != 0) 651 err = _sync_pll_output(idtcm, pll, channel->sync_src, 652 qn, qn_plus_1); 653 654 if (err) 655 return err; 656 } 657 658 return err; 659 } 660 661 static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel, 662 struct timespec64 const *ts, 663 enum hw_tod_write_trig_sel wr_trig) 664 { 665 struct idtcm *idtcm = channel->idtcm; 666 u8 buf[TOD_BYTE_COUNT]; 667 u8 cmd; 668 int err; 669 struct timespec64 local_ts = *ts; 670 s64 total_overhead_ns; 671 672 /* Configure HW TOD write trigger. */ 673 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 674 &cmd, sizeof(cmd)); 675 if (err) 676 return err; 677 678 cmd &= ~(0x0f); 679 cmd |= wr_trig | 0x08; 680 681 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 682 &cmd, sizeof(cmd)); 683 if (err) 684 return err; 685 686 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) { 687 err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); 688 if (err) 689 return err; 690 691 err = idtcm_write(idtcm, channel->hw_dpll_n, 692 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 693 if (err) 694 return err; 695 } 696 697 /* ARM HW TOD write trigger. */ 698 cmd &= ~(0x08); 699 700 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 701 &cmd, sizeof(cmd)); 702 703 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) { 704 if (idtcm->calculate_overhead_flag) { 705 /* Assumption: I2C @ 400KHz */ 706 ktime_t diff = ktime_sub(ktime_get_raw(), 707 idtcm->start_time); 708 total_overhead_ns = ktime_to_ns(diff) 709 + idtcm->tod_write_overhead_ns 710 + SETTIME_CORRECTION; 711 712 timespec64_add_ns(&local_ts, total_overhead_ns); 713 714 idtcm->calculate_overhead_flag = 0; 715 } 716 717 err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); 718 if (err) 719 return err; 720 721 err = idtcm_write(idtcm, channel->hw_dpll_n, 722 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 723 } 724 725 return err; 726 } 727 728 static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel, 729 struct timespec64 const *ts, 730 enum scsr_tod_write_trig_sel wr_trig, 731 enum scsr_tod_write_type_sel wr_type) 732 { 733 struct idtcm *idtcm = channel->idtcm; 734 unsigned char buf[TOD_BYTE_COUNT], cmd; 735 struct timespec64 local_ts = *ts; 736 int err, count = 0; 737 738 timespec64_add_ns(&local_ts, SETTIME_CORRECTION); 739 740 err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); 741 if (err) 742 return err; 743 744 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE, 745 buf, sizeof(buf)); 746 if (err) 747 return err; 748 749 /* Trigger the write operation. */ 750 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD, 751 &cmd, sizeof(cmd)); 752 if (err) 753 return err; 754 755 cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT); 756 cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT); 757 cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT); 758 cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT); 759 760 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD, 761 &cmd, sizeof(cmd)); 762 if (err) 763 return err; 764 765 /* Wait for the operation to complete. */ 766 while (1) { 767 /* pps trigger takes up to 1 sec to complete */ 768 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS) 769 msleep(50); 770 771 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD, 772 &cmd, sizeof(cmd)); 773 if (err) 774 return err; 775 776 if ((cmd & TOD_WRITE_SELECTION_MASK) == 0) 777 break; 778 779 if (++count > 20) { 780 dev_err(&idtcm->client->dev, 781 "Timed out waiting for the write counter"); 782 return -EIO; 783 } 784 } 785 786 return 0; 787 } 788 789 static int get_output_base_addr(enum fw_version ver, u8 outn) 790 { 791 int base; 792 793 switch (outn) { 794 case 0: 795 base = IDTCM_FW_REG(ver, V520, OUTPUT_0); 796 break; 797 case 1: 798 base = IDTCM_FW_REG(ver, V520, OUTPUT_1); 799 break; 800 case 2: 801 base = IDTCM_FW_REG(ver, V520, OUTPUT_2); 802 break; 803 case 3: 804 base = IDTCM_FW_REG(ver, V520, OUTPUT_3); 805 break; 806 case 4: 807 base = IDTCM_FW_REG(ver, V520, OUTPUT_4); 808 break; 809 case 5: 810 base = IDTCM_FW_REG(ver, V520, OUTPUT_5); 811 break; 812 case 6: 813 base = IDTCM_FW_REG(ver, V520, OUTPUT_6); 814 break; 815 case 7: 816 base = IDTCM_FW_REG(ver, V520, OUTPUT_7); 817 break; 818 case 8: 819 base = IDTCM_FW_REG(ver, V520, OUTPUT_8); 820 break; 821 case 9: 822 base = IDTCM_FW_REG(ver, V520, OUTPUT_9); 823 break; 824 case 10: 825 base = IDTCM_FW_REG(ver, V520, OUTPUT_10); 826 break; 827 case 11: 828 base = IDTCM_FW_REG(ver, V520, OUTPUT_11); 829 break; 830 default: 831 base = -EINVAL; 832 } 833 834 return base; 835 } 836 837 static int _idtcm_settime_deprecated(struct idtcm_channel *channel, 838 struct timespec64 const *ts) 839 { 840 struct idtcm *idtcm = channel->idtcm; 841 int err; 842 843 err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB); 844 if (err) { 845 dev_err(&idtcm->client->dev, 846 "%s: Set HW ToD failed", __func__); 847 return err; 848 } 849 850 return idtcm_sync_pps_output(channel); 851 } 852 853 static int _idtcm_settime(struct idtcm_channel *channel, 854 struct timespec64 const *ts, 855 enum scsr_tod_write_type_sel wr_type) 856 { 857 return _idtcm_set_dpll_scsr_tod(channel, ts, 858 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE, 859 wr_type); 860 } 861 862 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel, 863 s32 offset_ns) 864 { 865 int err; 866 int i; 867 struct idtcm *idtcm = channel->idtcm; 868 u8 buf[4]; 869 870 for (i = 0; i < 4; i++) { 871 buf[i] = 0xff & (offset_ns); 872 offset_ns >>= 8; 873 } 874 875 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET, 876 buf, sizeof(buf)); 877 878 return err; 879 } 880 881 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel, 882 u32 max_ffo_ppb) 883 { 884 int err; 885 u8 i; 886 struct idtcm *idtcm = channel->idtcm; 887 u8 buf[3]; 888 889 if (max_ffo_ppb & 0xff000000) 890 max_ffo_ppb = 0; 891 892 for (i = 0; i < 3; i++) { 893 buf[i] = 0xff & (max_ffo_ppb); 894 max_ffo_ppb >>= 8; 895 } 896 897 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, 898 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf)); 899 900 return err; 901 } 902 903 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel) 904 { 905 int err; 906 struct idtcm *idtcm = channel->idtcm; 907 u8 buf; 908 909 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL, 910 &buf, sizeof(buf)); 911 if (err) 912 return err; 913 914 if (buf == 0) { 915 buf = 0x01; 916 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, 917 PULL_IN_CTRL, &buf, sizeof(buf)); 918 } else { 919 err = -EBUSY; 920 } 921 922 return err; 923 } 924 925 static int do_phase_pull_in_fw(struct idtcm_channel *channel, 926 s32 offset_ns, 927 u32 max_ffo_ppb) 928 { 929 int err; 930 931 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns); 932 if (err) 933 return err; 934 935 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb); 936 if (err) 937 return err; 938 939 err = idtcm_start_phase_pull_in(channel); 940 941 return err; 942 } 943 944 static int set_tod_write_overhead(struct idtcm_channel *channel) 945 { 946 struct idtcm *idtcm = channel->idtcm; 947 s64 current_ns = 0; 948 s64 lowest_ns = 0; 949 int err; 950 u8 i; 951 ktime_t start; 952 ktime_t stop; 953 ktime_t diff; 954 955 char buf[TOD_BYTE_COUNT] = {0}; 956 957 /* Set page offset */ 958 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0, 959 buf, sizeof(buf)); 960 961 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) { 962 start = ktime_get_raw(); 963 964 err = idtcm_write(idtcm, channel->hw_dpll_n, 965 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 966 if (err) 967 return err; 968 969 stop = ktime_get_raw(); 970 971 diff = ktime_sub(stop, start); 972 973 current_ns = ktime_to_ns(diff); 974 975 if (i == 0) { 976 lowest_ns = current_ns; 977 } else { 978 if (current_ns < lowest_ns) 979 lowest_ns = current_ns; 980 } 981 } 982 983 idtcm->tod_write_overhead_ns = lowest_ns; 984 985 return err; 986 } 987 988 static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta) 989 { 990 int err; 991 struct idtcm *idtcm = channel->idtcm; 992 struct timespec64 ts; 993 s64 now; 994 995 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) { 996 err = channel->do_phase_pull_in(channel, delta, 0); 997 } else { 998 idtcm->calculate_overhead_flag = 1; 999 1000 err = set_tod_write_overhead(channel); 1001 if (err) 1002 return err; 1003 1004 err = _idtcm_gettime(channel, &ts); 1005 if (err) 1006 return err; 1007 1008 now = timespec64_to_ns(&ts); 1009 now += delta; 1010 1011 ts = ns_to_timespec64(now); 1012 1013 err = _idtcm_settime_deprecated(channel, &ts); 1014 } 1015 1016 return err; 1017 } 1018 1019 static int idtcm_state_machine_reset(struct idtcm *idtcm) 1020 { 1021 u8 byte = SM_RESET_CMD; 1022 u32 status = 0; 1023 int err; 1024 u8 i; 1025 1026 clear_boot_status(idtcm); 1027 1028 err = idtcm_write(idtcm, RESET_CTRL, 1029 IDTCM_FW_REG(idtcm->fw_ver, V520, SM_RESET), 1030 &byte, sizeof(byte)); 1031 1032 if (!err) { 1033 for (i = 0; i < 30; i++) { 1034 msleep_interruptible(100); 1035 read_boot_status(idtcm, &status); 1036 1037 if (status == 0xA0) { 1038 dev_dbg(&idtcm->client->dev, 1039 "SM_RESET completed in %d ms", i * 100); 1040 break; 1041 } 1042 } 1043 1044 if (!status) 1045 dev_err(&idtcm->client->dev, 1046 "Timed out waiting for CM_RESET to complete"); 1047 } 1048 1049 return err; 1050 } 1051 1052 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id) 1053 { 1054 return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8)); 1055 } 1056 1057 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id) 1058 { 1059 int err; 1060 u8 buf[2] = {0}; 1061 1062 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf)); 1063 1064 *product_id = (buf[1] << 8) | buf[0]; 1065 1066 return err; 1067 } 1068 1069 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major) 1070 { 1071 int err; 1072 u8 buf = 0; 1073 1074 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf)); 1075 1076 *major = buf >> 1; 1077 1078 return err; 1079 } 1080 1081 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor) 1082 { 1083 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8)); 1084 } 1085 1086 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix) 1087 { 1088 return idtcm_read(idtcm, 1089 GENERAL_STATUS, 1090 HOTFIX_REL, 1091 hotfix, 1092 sizeof(u8)); 1093 } 1094 1095 static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm, 1096 u8 *config_select) 1097 { 1098 return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT, 1099 config_select, sizeof(u8)); 1100 } 1101 1102 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val) 1103 { 1104 int err = 0; 1105 1106 switch (addr) { 1107 case TOD0_OUT_ALIGN_MASK_ADDR: 1108 SET_U16_LSB(idtcm->channel[0].output_mask, val); 1109 break; 1110 case TOD0_OUT_ALIGN_MASK_ADDR + 1: 1111 SET_U16_MSB(idtcm->channel[0].output_mask, val); 1112 break; 1113 case TOD1_OUT_ALIGN_MASK_ADDR: 1114 SET_U16_LSB(idtcm->channel[1].output_mask, val); 1115 break; 1116 case TOD1_OUT_ALIGN_MASK_ADDR + 1: 1117 SET_U16_MSB(idtcm->channel[1].output_mask, val); 1118 break; 1119 case TOD2_OUT_ALIGN_MASK_ADDR: 1120 SET_U16_LSB(idtcm->channel[2].output_mask, val); 1121 break; 1122 case TOD2_OUT_ALIGN_MASK_ADDR + 1: 1123 SET_U16_MSB(idtcm->channel[2].output_mask, val); 1124 break; 1125 case TOD3_OUT_ALIGN_MASK_ADDR: 1126 SET_U16_LSB(idtcm->channel[3].output_mask, val); 1127 break; 1128 case TOD3_OUT_ALIGN_MASK_ADDR + 1: 1129 SET_U16_MSB(idtcm->channel[3].output_mask, val); 1130 break; 1131 default: 1132 err = -EFAULT; /* Bad address */; 1133 break; 1134 } 1135 1136 return err; 1137 } 1138 1139 static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll) 1140 { 1141 if (index >= MAX_TOD) { 1142 dev_err(&idtcm->client->dev, "ToD%d not supported", index); 1143 return -EINVAL; 1144 } 1145 1146 if (pll >= MAX_PLL) { 1147 dev_err(&idtcm->client->dev, "Pll%d not supported", pll); 1148 return -EINVAL; 1149 } 1150 1151 idtcm->channel[index].pll = pll; 1152 1153 return 0; 1154 } 1155 1156 static int check_and_set_masks(struct idtcm *idtcm, 1157 u16 regaddr, 1158 u8 val) 1159 { 1160 int err = 0; 1161 1162 switch (regaddr) { 1163 case TOD_MASK_ADDR: 1164 if ((val & 0xf0) || !(val & 0x0f)) { 1165 dev_err(&idtcm->client->dev, "Invalid TOD mask 0x%02x", val); 1166 err = -EINVAL; 1167 } else { 1168 idtcm->tod_mask = val; 1169 } 1170 break; 1171 case TOD0_PTP_PLL_ADDR: 1172 err = set_tod_ptp_pll(idtcm, 0, val); 1173 break; 1174 case TOD1_PTP_PLL_ADDR: 1175 err = set_tod_ptp_pll(idtcm, 1, val); 1176 break; 1177 case TOD2_PTP_PLL_ADDR: 1178 err = set_tod_ptp_pll(idtcm, 2, val); 1179 break; 1180 case TOD3_PTP_PLL_ADDR: 1181 err = set_tod_ptp_pll(idtcm, 3, val); 1182 break; 1183 default: 1184 err = set_pll_output_mask(idtcm, regaddr, val); 1185 break; 1186 } 1187 1188 return err; 1189 } 1190 1191 static void display_pll_and_masks(struct idtcm *idtcm) 1192 { 1193 u8 i; 1194 u8 mask; 1195 1196 dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x", idtcm->tod_mask); 1197 1198 for (i = 0; i < MAX_TOD; i++) { 1199 mask = 1 << i; 1200 1201 if (mask & idtcm->tod_mask) 1202 dev_dbg(&idtcm->client->dev, 1203 "TOD%d pll = %d output_mask = 0x%04x", 1204 i, idtcm->channel[i].pll, 1205 idtcm->channel[i].output_mask); 1206 } 1207 } 1208 1209 static int idtcm_load_firmware(struct idtcm *idtcm, 1210 struct device *dev) 1211 { 1212 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH); 1213 char fname[128] = FW_FILENAME; 1214 const struct firmware *fw; 1215 struct idtcm_fwrc *rec; 1216 u32 regaddr; 1217 int err; 1218 s32 len; 1219 u8 val; 1220 u8 loaddr; 1221 1222 if (firmware) /* module parameter */ 1223 snprintf(fname, sizeof(fname), "%s", firmware); 1224 1225 dev_info(&idtcm->client->dev, "firmware '%s'", fname); 1226 1227 err = request_firmware(&fw, fname, dev); 1228 if (err) { 1229 dev_err(&idtcm->client->dev, 1230 "Failed at line %d in %s!", __LINE__, __func__); 1231 return err; 1232 } 1233 1234 dev_dbg(&idtcm->client->dev, "firmware size %zu bytes", fw->size); 1235 1236 rec = (struct idtcm_fwrc *) fw->data; 1237 1238 if (contains_full_configuration(idtcm, fw)) 1239 idtcm_state_machine_reset(idtcm); 1240 1241 for (len = fw->size; len > 0; len -= sizeof(*rec)) { 1242 if (rec->reserved) { 1243 dev_err(&idtcm->client->dev, 1244 "bad firmware, reserved field non-zero"); 1245 err = -EINVAL; 1246 } else { 1247 regaddr = rec->hiaddr << 8; 1248 regaddr |= rec->loaddr; 1249 1250 val = rec->value; 1251 loaddr = rec->loaddr; 1252 1253 rec++; 1254 1255 err = check_and_set_masks(idtcm, regaddr, val); 1256 } 1257 1258 if (err != -EINVAL) { 1259 err = 0; 1260 1261 /* Top (status registers) and bottom are read-only */ 1262 if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch) 1263 continue; 1264 1265 /* Page size 128, last 4 bytes of page skipped */ 1266 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb) 1267 continue; 1268 1269 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val)); 1270 } 1271 1272 if (err) 1273 goto out; 1274 } 1275 1276 display_pll_and_masks(idtcm); 1277 1278 out: 1279 release_firmware(fw); 1280 return err; 1281 } 1282 1283 static int idtcm_output_enable(struct idtcm_channel *channel, 1284 bool enable, unsigned int outn) 1285 { 1286 struct idtcm *idtcm = channel->idtcm; 1287 int base; 1288 int err; 1289 u8 val; 1290 1291 base = get_output_base_addr(idtcm->fw_ver, outn); 1292 1293 if (!(base > 0)) { 1294 dev_err(&idtcm->client->dev, 1295 "%s - Unsupported out%d", __func__, outn); 1296 return base; 1297 } 1298 1299 err = idtcm_read(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val)); 1300 if (err) 1301 return err; 1302 1303 if (enable) 1304 val |= SQUELCH_DISABLE; 1305 else 1306 val &= ~SQUELCH_DISABLE; 1307 1308 return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val)); 1309 } 1310 1311 static int idtcm_output_mask_enable(struct idtcm_channel *channel, 1312 bool enable) 1313 { 1314 u16 mask; 1315 int err; 1316 u8 outn; 1317 1318 mask = channel->output_mask; 1319 outn = 0; 1320 1321 while (mask) { 1322 if (mask & 0x1) { 1323 err = idtcm_output_enable(channel, enable, outn); 1324 if (err) 1325 return err; 1326 } 1327 1328 mask >>= 0x1; 1329 outn++; 1330 } 1331 1332 return 0; 1333 } 1334 1335 static int idtcm_perout_enable(struct idtcm_channel *channel, 1336 bool enable, 1337 struct ptp_perout_request *perout) 1338 { 1339 struct idtcm *idtcm = channel->idtcm; 1340 unsigned int flags = perout->flags; 1341 struct timespec64 ts = {0, 0}; 1342 int err; 1343 1344 if (flags == PEROUT_ENABLE_OUTPUT_MASK) 1345 err = idtcm_output_mask_enable(channel, enable); 1346 else 1347 err = idtcm_output_enable(channel, enable, perout->index); 1348 1349 if (err) { 1350 dev_err(&idtcm->client->dev, "Unable to set output enable"); 1351 return err; 1352 } 1353 1354 /* Align output to internal 1 PPS */ 1355 return _idtcm_settime(channel, &ts, SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS); 1356 } 1357 1358 static int idtcm_get_pll_mode(struct idtcm_channel *channel, 1359 enum pll_mode *mode) 1360 { 1361 struct idtcm *idtcm = channel->idtcm; 1362 int err; 1363 u8 dpll_mode; 1364 1365 err = idtcm_read(idtcm, channel->dpll_n, 1366 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE), 1367 &dpll_mode, sizeof(dpll_mode)); 1368 if (err) 1369 return err; 1370 1371 *mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK; 1372 1373 return 0; 1374 } 1375 1376 static int idtcm_set_pll_mode(struct idtcm_channel *channel, 1377 enum pll_mode mode) 1378 { 1379 struct idtcm *idtcm = channel->idtcm; 1380 int err; 1381 u8 dpll_mode; 1382 1383 err = idtcm_read(idtcm, channel->dpll_n, 1384 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE), 1385 &dpll_mode, sizeof(dpll_mode)); 1386 if (err) 1387 return err; 1388 1389 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT); 1390 1391 dpll_mode |= (mode << PLL_MODE_SHIFT); 1392 1393 err = idtcm_write(idtcm, channel->dpll_n, 1394 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE), 1395 &dpll_mode, sizeof(dpll_mode)); 1396 return err; 1397 } 1398 1399 static int idtcm_get_manual_reference(struct idtcm_channel *channel, 1400 enum manual_reference *ref) 1401 { 1402 struct idtcm *idtcm = channel->idtcm; 1403 u8 dpll_manu_ref_cfg; 1404 int err; 1405 1406 err = idtcm_read(idtcm, channel->dpll_ctrl_n, 1407 DPLL_CTRL_DPLL_MANU_REF_CFG, 1408 &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg)); 1409 if (err) 1410 return err; 1411 1412 dpll_manu_ref_cfg &= (MANUAL_REFERENCE_MASK << MANUAL_REFERENCE_SHIFT); 1413 1414 *ref = dpll_manu_ref_cfg >> MANUAL_REFERENCE_SHIFT; 1415 1416 return 0; 1417 } 1418 1419 static int idtcm_set_manual_reference(struct idtcm_channel *channel, 1420 enum manual_reference ref) 1421 { 1422 struct idtcm *idtcm = channel->idtcm; 1423 u8 dpll_manu_ref_cfg; 1424 int err; 1425 1426 err = idtcm_read(idtcm, channel->dpll_ctrl_n, 1427 DPLL_CTRL_DPLL_MANU_REF_CFG, 1428 &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg)); 1429 if (err) 1430 return err; 1431 1432 dpll_manu_ref_cfg &= ~(MANUAL_REFERENCE_MASK << MANUAL_REFERENCE_SHIFT); 1433 1434 dpll_manu_ref_cfg |= (ref << MANUAL_REFERENCE_SHIFT); 1435 1436 err = idtcm_write(idtcm, channel->dpll_ctrl_n, 1437 DPLL_CTRL_DPLL_MANU_REF_CFG, 1438 &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg)); 1439 1440 return err; 1441 } 1442 1443 static int configure_dpll_mode_write_frequency(struct idtcm_channel *channel) 1444 { 1445 struct idtcm *idtcm = channel->idtcm; 1446 int err; 1447 1448 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY); 1449 1450 if (err) 1451 dev_err(&idtcm->client->dev, "Failed to set pll mode to write frequency"); 1452 else 1453 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY; 1454 1455 return err; 1456 } 1457 1458 static int configure_dpll_mode_write_phase(struct idtcm_channel *channel) 1459 { 1460 struct idtcm *idtcm = channel->idtcm; 1461 int err; 1462 1463 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE); 1464 1465 if (err) 1466 dev_err(&idtcm->client->dev, "Failed to set pll mode to write phase"); 1467 else 1468 channel->mode = PTP_PLL_MODE_WRITE_PHASE; 1469 1470 return err; 1471 } 1472 1473 static int configure_manual_reference_write_frequency(struct idtcm_channel *channel) 1474 { 1475 struct idtcm *idtcm = channel->idtcm; 1476 int err; 1477 1478 err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_FREQUENCY); 1479 1480 if (err) 1481 dev_err(&idtcm->client->dev, "Failed to set manual reference to write frequency"); 1482 else 1483 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY; 1484 1485 return err; 1486 } 1487 1488 static int configure_manual_reference_write_phase(struct idtcm_channel *channel) 1489 { 1490 struct idtcm *idtcm = channel->idtcm; 1491 int err; 1492 1493 err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_PHASE); 1494 1495 if (err) 1496 dev_err(&idtcm->client->dev, "Failed to set manual reference to write phase"); 1497 else 1498 channel->mode = PTP_PLL_MODE_WRITE_PHASE; 1499 1500 return err; 1501 } 1502 1503 static int idtcm_stop_phase_pull_in(struct idtcm_channel *channel) 1504 { 1505 int err; 1506 1507 err = _idtcm_adjfine(channel, channel->current_freq_scaled_ppm); 1508 if (err) 1509 return err; 1510 1511 channel->phase_pull_in = false; 1512 1513 return 0; 1514 } 1515 1516 static long idtcm_work_handler(struct ptp_clock_info *ptp) 1517 { 1518 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1519 struct idtcm *idtcm = channel->idtcm; 1520 1521 mutex_lock(&idtcm->reg_lock); 1522 1523 (void)idtcm_stop_phase_pull_in(channel); 1524 1525 mutex_unlock(&idtcm->reg_lock); 1526 1527 /* Return a negative value here to not reschedule */ 1528 return -1; 1529 } 1530 1531 static s32 phase_pull_in_scaled_ppm(s32 current_ppm, s32 phase_pull_in_ppb) 1532 { 1533 /* ppb = scaled_ppm * 125 / 2^13 */ 1534 /* scaled_ppm = ppb * 2^13 / 125 */ 1535 1536 s64 max_scaled_ppm = (PHASE_PULL_IN_MAX_PPB << 13) / 125; 1537 s64 scaled_ppm = (phase_pull_in_ppb << 13) / 125; 1538 1539 current_ppm += scaled_ppm; 1540 1541 if (current_ppm > max_scaled_ppm) 1542 current_ppm = max_scaled_ppm; 1543 else if (current_ppm < -max_scaled_ppm) 1544 current_ppm = -max_scaled_ppm; 1545 1546 return current_ppm; 1547 } 1548 1549 static int do_phase_pull_in_sw(struct idtcm_channel *channel, 1550 s32 delta_ns, 1551 u32 max_ffo_ppb) 1552 { 1553 s32 current_ppm = channel->current_freq_scaled_ppm; 1554 u32 duration_ms = MSEC_PER_SEC; 1555 s32 delta_ppm; 1556 s32 ppb; 1557 int err; 1558 1559 /* If the ToD correction is less than PHASE_PULL_IN_MIN_THRESHOLD_NS, 1560 * skip. The error introduced by the ToD adjustment procedure would 1561 * be bigger than the required ToD correction 1562 */ 1563 if (abs(delta_ns) < PHASE_PULL_IN_MIN_THRESHOLD_NS) 1564 return 0; 1565 1566 if (max_ffo_ppb == 0) 1567 max_ffo_ppb = PHASE_PULL_IN_MAX_PPB; 1568 1569 /* For most cases, keep phase pull-in duration 1 second */ 1570 ppb = delta_ns; 1571 while (abs(ppb) > max_ffo_ppb) { 1572 duration_ms *= 2; 1573 ppb /= 2; 1574 } 1575 1576 delta_ppm = phase_pull_in_scaled_ppm(current_ppm, ppb); 1577 1578 err = _idtcm_adjfine(channel, delta_ppm); 1579 1580 if (err) 1581 return err; 1582 1583 /* schedule the worker to cancel phase pull-in */ 1584 ptp_schedule_worker(channel->ptp_clock, 1585 msecs_to_jiffies(duration_ms) - 1); 1586 1587 channel->phase_pull_in = true; 1588 1589 return 0; 1590 } 1591 1592 static int initialize_operating_mode_with_manual_reference(struct idtcm_channel *channel, 1593 enum manual_reference ref) 1594 { 1595 struct idtcm *idtcm = channel->idtcm; 1596 1597 channel->mode = PTP_PLL_MODE_UNSUPPORTED; 1598 channel->configure_write_frequency = configure_manual_reference_write_frequency; 1599 channel->configure_write_phase = configure_manual_reference_write_phase; 1600 channel->do_phase_pull_in = do_phase_pull_in_sw; 1601 1602 switch (ref) { 1603 case MANU_REF_WRITE_PHASE: 1604 channel->mode = PTP_PLL_MODE_WRITE_PHASE; 1605 break; 1606 case MANU_REF_WRITE_FREQUENCY: 1607 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY; 1608 break; 1609 default: 1610 dev_warn(&idtcm->client->dev, 1611 "Unsupported MANUAL_REFERENCE: 0x%02x", ref); 1612 } 1613 1614 return 0; 1615 } 1616 1617 static int initialize_operating_mode_with_pll_mode(struct idtcm_channel *channel, 1618 enum pll_mode mode) 1619 { 1620 struct idtcm *idtcm = channel->idtcm; 1621 int err = 0; 1622 1623 channel->mode = PTP_PLL_MODE_UNSUPPORTED; 1624 channel->configure_write_frequency = configure_dpll_mode_write_frequency; 1625 channel->configure_write_phase = configure_dpll_mode_write_phase; 1626 channel->do_phase_pull_in = do_phase_pull_in_fw; 1627 1628 switch (mode) { 1629 case PLL_MODE_WRITE_PHASE: 1630 channel->mode = PTP_PLL_MODE_WRITE_PHASE; 1631 break; 1632 case PLL_MODE_WRITE_FREQUENCY: 1633 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY; 1634 break; 1635 default: 1636 dev_err(&idtcm->client->dev, 1637 "Unsupported PLL_MODE: 0x%02x", mode); 1638 err = -EINVAL; 1639 } 1640 1641 return err; 1642 } 1643 1644 static int initialize_dco_operating_mode(struct idtcm_channel *channel) 1645 { 1646 enum manual_reference ref = MANU_REF_XO_DPLL; 1647 enum pll_mode mode = PLL_MODE_DISABLED; 1648 struct idtcm *idtcm = channel->idtcm; 1649 int err; 1650 1651 channel->mode = PTP_PLL_MODE_UNSUPPORTED; 1652 1653 err = idtcm_get_pll_mode(channel, &mode); 1654 if (err) { 1655 dev_err(&idtcm->client->dev, "Unable to read pll mode!"); 1656 return err; 1657 } 1658 1659 if (mode == PLL_MODE_PLL) { 1660 err = idtcm_get_manual_reference(channel, &ref); 1661 if (err) { 1662 dev_err(&idtcm->client->dev, "Unable to read manual reference!"); 1663 return err; 1664 } 1665 err = initialize_operating_mode_with_manual_reference(channel, ref); 1666 } else { 1667 err = initialize_operating_mode_with_pll_mode(channel, mode); 1668 } 1669 1670 if (channel->mode == PTP_PLL_MODE_WRITE_PHASE) 1671 channel->configure_write_frequency(channel); 1672 1673 return err; 1674 } 1675 1676 /* PTP Hardware Clock interface */ 1677 1678 /** 1679 * Maximum absolute value for write phase offset in picoseconds 1680 * 1681 * @channel: channel 1682 * @delta_ns: delta in nanoseconds 1683 * 1684 * Destination signed register is 32-bit register in resolution of 50ps 1685 * 1686 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350 1687 */ 1688 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns) 1689 { 1690 struct idtcm *idtcm = channel->idtcm; 1691 int err; 1692 u8 i; 1693 u8 buf[4] = {0}; 1694 s32 phase_50ps; 1695 s64 offset_ps; 1696 1697 if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) { 1698 err = channel->configure_write_phase(channel); 1699 if (err) 1700 return err; 1701 } 1702 1703 offset_ps = (s64)delta_ns * 1000; 1704 1705 /* 1706 * Check for 32-bit signed max * 50: 1707 * 1708 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350 1709 */ 1710 if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS) 1711 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS; 1712 else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS) 1713 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS; 1714 1715 phase_50ps = div_s64(offset_ps, 50); 1716 1717 for (i = 0; i < 4; i++) { 1718 buf[i] = phase_50ps & 0xff; 1719 phase_50ps >>= 8; 1720 } 1721 1722 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE, 1723 buf, sizeof(buf)); 1724 1725 return err; 1726 } 1727 1728 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm) 1729 { 1730 struct idtcm *idtcm = channel->idtcm; 1731 u8 i; 1732 int err; 1733 u8 buf[6] = {0}; 1734 s64 fcw; 1735 1736 if (channel->mode != PTP_PLL_MODE_WRITE_FREQUENCY) { 1737 err = channel->configure_write_frequency(channel); 1738 if (err) 1739 return err; 1740 } 1741 1742 /* 1743 * Frequency Control Word unit is: 1.11 * 10^-10 ppm 1744 * 1745 * adjfreq: 1746 * ppb * 10^9 1747 * FCW = ---------- 1748 * 111 1749 * 1750 * adjfine: 1751 * ppm_16 * 5^12 1752 * FCW = ------------- 1753 * 111 * 2^4 1754 */ 1755 1756 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */ 1757 fcw = scaled_ppm * 244140625ULL; 1758 1759 fcw = div_s64(fcw, 1776); 1760 1761 for (i = 0; i < 6; i++) { 1762 buf[i] = fcw & 0xff; 1763 fcw >>= 8; 1764 } 1765 1766 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ, 1767 buf, sizeof(buf)); 1768 1769 return err; 1770 } 1771 1772 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 1773 { 1774 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1775 struct idtcm *idtcm = channel->idtcm; 1776 int err; 1777 1778 mutex_lock(&idtcm->reg_lock); 1779 1780 err = _idtcm_gettime(channel, ts); 1781 if (err) 1782 dev_err(&idtcm->client->dev, "Failed at line %d in %s!", 1783 __LINE__, __func__); 1784 1785 mutex_unlock(&idtcm->reg_lock); 1786 1787 return err; 1788 } 1789 1790 static int idtcm_settime_deprecated(struct ptp_clock_info *ptp, 1791 const struct timespec64 *ts) 1792 { 1793 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1794 struct idtcm *idtcm = channel->idtcm; 1795 int err; 1796 1797 mutex_lock(&idtcm->reg_lock); 1798 1799 err = _idtcm_settime_deprecated(channel, ts); 1800 if (err) 1801 dev_err(&idtcm->client->dev, 1802 "Failed at line %d in %s!", __LINE__, __func__); 1803 1804 mutex_unlock(&idtcm->reg_lock); 1805 1806 return err; 1807 } 1808 1809 static int idtcm_settime(struct ptp_clock_info *ptp, 1810 const struct timespec64 *ts) 1811 { 1812 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1813 struct idtcm *idtcm = channel->idtcm; 1814 int err; 1815 1816 mutex_lock(&idtcm->reg_lock); 1817 1818 err = _idtcm_settime(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE); 1819 if (err) 1820 dev_err(&idtcm->client->dev, 1821 "Failed at line %d in %s!", __LINE__, __func__); 1822 1823 mutex_unlock(&idtcm->reg_lock); 1824 1825 return err; 1826 } 1827 1828 static int idtcm_adjtime_deprecated(struct ptp_clock_info *ptp, s64 delta) 1829 { 1830 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1831 struct idtcm *idtcm = channel->idtcm; 1832 int err; 1833 1834 mutex_lock(&idtcm->reg_lock); 1835 1836 err = _idtcm_adjtime_deprecated(channel, delta); 1837 if (err) 1838 dev_err(&idtcm->client->dev, 1839 "Failed at line %d in %s!", __LINE__, __func__); 1840 1841 mutex_unlock(&idtcm->reg_lock); 1842 1843 return err; 1844 } 1845 1846 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta) 1847 { 1848 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1849 struct idtcm *idtcm = channel->idtcm; 1850 struct timespec64 ts; 1851 enum scsr_tod_write_type_sel type; 1852 int err; 1853 1854 if (channel->phase_pull_in == true) 1855 return 0; 1856 1857 mutex_lock(&idtcm->reg_lock); 1858 1859 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) { 1860 err = channel->do_phase_pull_in(channel, delta, 0); 1861 if (err) 1862 dev_err(&idtcm->client->dev, 1863 "Failed at line %d in %s!", __LINE__, __func__); 1864 } else { 1865 if (delta >= 0) { 1866 ts = ns_to_timespec64(delta); 1867 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS; 1868 } else { 1869 ts = ns_to_timespec64(-delta); 1870 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS; 1871 } 1872 err = _idtcm_settime(channel, &ts, type); 1873 if (err) 1874 dev_err(&idtcm->client->dev, 1875 "Failed at line %d in %s!", __LINE__, __func__); 1876 } 1877 mutex_unlock(&idtcm->reg_lock); 1878 1879 return err; 1880 } 1881 1882 static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta) 1883 { 1884 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1885 struct idtcm *idtcm = channel->idtcm; 1886 int err; 1887 1888 mutex_lock(&idtcm->reg_lock); 1889 1890 err = _idtcm_adjphase(channel, delta); 1891 if (err) 1892 dev_err(&idtcm->client->dev, 1893 "Failed at line %d in %s!", __LINE__, __func__); 1894 1895 mutex_unlock(&idtcm->reg_lock); 1896 1897 return err; 1898 } 1899 1900 static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 1901 { 1902 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1903 struct idtcm *idtcm = channel->idtcm; 1904 int err; 1905 1906 if (channel->phase_pull_in == true) 1907 return 0; 1908 1909 if (scaled_ppm == channel->current_freq_scaled_ppm) 1910 return 0; 1911 1912 mutex_lock(&idtcm->reg_lock); 1913 1914 err = _idtcm_adjfine(channel, scaled_ppm); 1915 1916 mutex_unlock(&idtcm->reg_lock); 1917 1918 if (!err) 1919 channel->current_freq_scaled_ppm = scaled_ppm; 1920 1921 return err; 1922 } 1923 1924 static int idtcm_enable(struct ptp_clock_info *ptp, 1925 struct ptp_clock_request *rq, int on) 1926 { 1927 int err; 1928 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1929 1930 switch (rq->type) { 1931 case PTP_CLK_REQ_PEROUT: 1932 if (!on) { 1933 err = idtcm_perout_enable(channel, false, &rq->perout); 1934 if (err) 1935 dev_err(&channel->idtcm->client->dev, 1936 "Failed at line %d in %s!", 1937 __LINE__, __func__); 1938 return err; 1939 } 1940 1941 /* Only accept a 1-PPS aligned to the second. */ 1942 if (rq->perout.start.nsec || rq->perout.period.sec != 1 || 1943 rq->perout.period.nsec) 1944 return -ERANGE; 1945 1946 err = idtcm_perout_enable(channel, true, &rq->perout); 1947 if (err) 1948 dev_err(&channel->idtcm->client->dev, 1949 "Failed at line %d in %s!", __LINE__, __func__); 1950 return err; 1951 default: 1952 break; 1953 } 1954 1955 return -EOPNOTSUPP; 1956 } 1957 1958 static int idtcm_enable_tod(struct idtcm_channel *channel) 1959 { 1960 struct idtcm *idtcm = channel->idtcm; 1961 struct timespec64 ts = {0, 0}; 1962 u16 tod_cfg = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_CFG); 1963 u8 cfg; 1964 int err; 1965 1966 /* STEELAI-366 - Temporary workaround for ts2phc compatibility */ 1967 if (0) { 1968 err = idtcm_output_mask_enable(channel, false); 1969 if (err) 1970 return err; 1971 } 1972 1973 /* 1974 * Start the TOD clock ticking. 1975 */ 1976 err = idtcm_read(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg)); 1977 if (err) 1978 return err; 1979 1980 cfg |= TOD_ENABLE; 1981 1982 err = idtcm_write(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg)); 1983 if (err) 1984 return err; 1985 1986 if (idtcm->fw_ver < V487) 1987 return _idtcm_settime_deprecated(channel, &ts); 1988 else 1989 return _idtcm_settime(channel, &ts, 1990 SCSR_TOD_WR_TYPE_SEL_ABSOLUTE); 1991 } 1992 1993 static void idtcm_set_version_info(struct idtcm *idtcm) 1994 { 1995 u8 major; 1996 u8 minor; 1997 u8 hotfix; 1998 u16 product_id; 1999 u8 hw_rev_id; 2000 u8 config_select; 2001 2002 idtcm_read_major_release(idtcm, &major); 2003 idtcm_read_minor_release(idtcm, &minor); 2004 idtcm_read_hotfix_release(idtcm, &hotfix); 2005 2006 idtcm_read_product_id(idtcm, &product_id); 2007 idtcm_read_hw_rev_id(idtcm, &hw_rev_id); 2008 2009 idtcm_read_otp_scsr_config_select(idtcm, &config_select); 2010 2011 snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u", 2012 major, minor, hotfix); 2013 2014 idtcm->fw_ver = idtcm_fw_version(idtcm->version); 2015 2016 dev_info(&idtcm->client->dev, 2017 "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d", 2018 major, minor, hotfix, 2019 product_id, hw_rev_id, config_select); 2020 } 2021 2022 static const struct ptp_clock_info idtcm_caps = { 2023 .owner = THIS_MODULE, 2024 .max_adj = 244000, 2025 .n_per_out = 12, 2026 .adjphase = &idtcm_adjphase, 2027 .adjfine = &idtcm_adjfine, 2028 .adjtime = &idtcm_adjtime, 2029 .gettime64 = &idtcm_gettime, 2030 .settime64 = &idtcm_settime, 2031 .enable = &idtcm_enable, 2032 .do_aux_work = &idtcm_work_handler, 2033 }; 2034 2035 static const struct ptp_clock_info idtcm_caps_deprecated = { 2036 .owner = THIS_MODULE, 2037 .max_adj = 244000, 2038 .n_per_out = 12, 2039 .adjphase = &idtcm_adjphase, 2040 .adjfine = &idtcm_adjfine, 2041 .adjtime = &idtcm_adjtime_deprecated, 2042 .gettime64 = &idtcm_gettime, 2043 .settime64 = &idtcm_settime_deprecated, 2044 .enable = &idtcm_enable, 2045 .do_aux_work = &idtcm_work_handler, 2046 }; 2047 2048 static int configure_channel_pll(struct idtcm_channel *channel) 2049 { 2050 struct idtcm *idtcm = channel->idtcm; 2051 int err = 0; 2052 2053 switch (channel->pll) { 2054 case 0: 2055 channel->dpll_freq = DPLL_FREQ_0; 2056 channel->dpll_n = DPLL_0; 2057 channel->hw_dpll_n = HW_DPLL_0; 2058 channel->dpll_phase = DPLL_PHASE_0; 2059 channel->dpll_ctrl_n = DPLL_CTRL_0; 2060 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0; 2061 break; 2062 case 1: 2063 channel->dpll_freq = DPLL_FREQ_1; 2064 channel->dpll_n = DPLL_1; 2065 channel->hw_dpll_n = HW_DPLL_1; 2066 channel->dpll_phase = DPLL_PHASE_1; 2067 channel->dpll_ctrl_n = DPLL_CTRL_1; 2068 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1; 2069 break; 2070 case 2: 2071 channel->dpll_freq = DPLL_FREQ_2; 2072 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_2); 2073 channel->hw_dpll_n = HW_DPLL_2; 2074 channel->dpll_phase = DPLL_PHASE_2; 2075 channel->dpll_ctrl_n = DPLL_CTRL_2; 2076 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2; 2077 break; 2078 case 3: 2079 channel->dpll_freq = DPLL_FREQ_3; 2080 channel->dpll_n = DPLL_3; 2081 channel->hw_dpll_n = HW_DPLL_3; 2082 channel->dpll_phase = DPLL_PHASE_3; 2083 channel->dpll_ctrl_n = DPLL_CTRL_3; 2084 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3; 2085 break; 2086 case 4: 2087 channel->dpll_freq = DPLL_FREQ_4; 2088 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_4); 2089 channel->hw_dpll_n = HW_DPLL_4; 2090 channel->dpll_phase = DPLL_PHASE_4; 2091 channel->dpll_ctrl_n = DPLL_CTRL_4; 2092 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4; 2093 break; 2094 case 5: 2095 channel->dpll_freq = DPLL_FREQ_5; 2096 channel->dpll_n = DPLL_5; 2097 channel->hw_dpll_n = HW_DPLL_5; 2098 channel->dpll_phase = DPLL_PHASE_5; 2099 channel->dpll_ctrl_n = DPLL_CTRL_5; 2100 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5; 2101 break; 2102 case 6: 2103 channel->dpll_freq = DPLL_FREQ_6; 2104 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_6); 2105 channel->hw_dpll_n = HW_DPLL_6; 2106 channel->dpll_phase = DPLL_PHASE_6; 2107 channel->dpll_ctrl_n = DPLL_CTRL_6; 2108 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6; 2109 break; 2110 case 7: 2111 channel->dpll_freq = DPLL_FREQ_7; 2112 channel->dpll_n = DPLL_7; 2113 channel->hw_dpll_n = HW_DPLL_7; 2114 channel->dpll_phase = DPLL_PHASE_7; 2115 channel->dpll_ctrl_n = DPLL_CTRL_7; 2116 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7; 2117 break; 2118 default: 2119 err = -EINVAL; 2120 } 2121 2122 return err; 2123 } 2124 2125 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) 2126 { 2127 enum fw_version fw_ver = idtcm->fw_ver; 2128 struct idtcm_channel *channel; 2129 int err; 2130 2131 if (!(index < MAX_TOD)) 2132 return -EINVAL; 2133 2134 channel = &idtcm->channel[index]; 2135 2136 channel->idtcm = idtcm; 2137 channel->current_freq_scaled_ppm = 0; 2138 2139 /* Set pll addresses */ 2140 err = configure_channel_pll(channel); 2141 if (err) 2142 return err; 2143 2144 /* Set tod addresses */ 2145 switch (index) { 2146 case 0: 2147 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_0); 2148 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_0); 2149 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_0); 2150 channel->sync_src = SYNC_SOURCE_DPLL0_TOD_PPS; 2151 break; 2152 case 1: 2153 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_1); 2154 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_1); 2155 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_1); 2156 channel->sync_src = SYNC_SOURCE_DPLL1_TOD_PPS; 2157 break; 2158 case 2: 2159 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_2); 2160 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_2); 2161 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_2); 2162 channel->sync_src = SYNC_SOURCE_DPLL2_TOD_PPS; 2163 break; 2164 case 3: 2165 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_3); 2166 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_3); 2167 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_3); 2168 channel->sync_src = SYNC_SOURCE_DPLL3_TOD_PPS; 2169 break; 2170 default: 2171 return -EINVAL; 2172 } 2173 2174 if (idtcm->fw_ver < V487) 2175 channel->caps = idtcm_caps_deprecated; 2176 else 2177 channel->caps = idtcm_caps; 2178 2179 snprintf(channel->caps.name, sizeof(channel->caps.name), 2180 "IDT CM TOD%u", index); 2181 2182 err = initialize_dco_operating_mode(channel); 2183 if (err) 2184 return err; 2185 2186 err = idtcm_enable_tod(channel); 2187 if (err) { 2188 dev_err(&idtcm->client->dev, 2189 "Failed at line %d in %s!", __LINE__, __func__); 2190 return err; 2191 } 2192 2193 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL); 2194 2195 if (IS_ERR(channel->ptp_clock)) { 2196 err = PTR_ERR(channel->ptp_clock); 2197 channel->ptp_clock = NULL; 2198 return err; 2199 } 2200 2201 if (!channel->ptp_clock) 2202 return -ENOTSUPP; 2203 2204 dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d", 2205 index, channel->ptp_clock->index); 2206 2207 return 0; 2208 } 2209 2210 static void ptp_clock_unregister_all(struct idtcm *idtcm) 2211 { 2212 u8 i; 2213 struct idtcm_channel *channel; 2214 2215 for (i = 0; i < MAX_TOD; i++) { 2216 channel = &idtcm->channel[i]; 2217 if (channel->ptp_clock) 2218 ptp_clock_unregister(channel->ptp_clock); 2219 } 2220 } 2221 2222 static void set_default_masks(struct idtcm *idtcm) 2223 { 2224 idtcm->tod_mask = DEFAULT_TOD_MASK; 2225 2226 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL; 2227 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL; 2228 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL; 2229 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL; 2230 2231 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0; 2232 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1; 2233 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2; 2234 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3; 2235 } 2236 2237 static int idtcm_probe(struct i2c_client *client, 2238 const struct i2c_device_id *id) 2239 { 2240 struct idtcm *idtcm; 2241 int err; 2242 u8 i; 2243 2244 /* Unused for now */ 2245 (void)id; 2246 2247 idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL); 2248 2249 if (!idtcm) 2250 return -ENOMEM; 2251 2252 idtcm->client = client; 2253 idtcm->page_offset = 0xff; 2254 idtcm->calculate_overhead_flag = 0; 2255 2256 set_default_masks(idtcm); 2257 2258 mutex_init(&idtcm->reg_lock); 2259 mutex_lock(&idtcm->reg_lock); 2260 2261 idtcm_set_version_info(idtcm); 2262 2263 err = idtcm_load_firmware(idtcm, &client->dev); 2264 if (err) 2265 dev_warn(&idtcm->client->dev, "loading firmware failed with %d", err); 2266 2267 wait_for_chip_ready(idtcm); 2268 2269 if (idtcm->tod_mask) { 2270 for (i = 0; i < MAX_TOD; i++) { 2271 if (idtcm->tod_mask & (1 << i)) { 2272 err = idtcm_enable_channel(idtcm, i); 2273 if (err) { 2274 dev_err(&idtcm->client->dev, 2275 "idtcm_enable_channel %d failed!", i); 2276 break; 2277 } 2278 } 2279 } 2280 } else { 2281 dev_err(&idtcm->client->dev, 2282 "no PLLs flagged as PHCs, nothing to do"); 2283 err = -ENODEV; 2284 } 2285 2286 mutex_unlock(&idtcm->reg_lock); 2287 2288 if (err) { 2289 ptp_clock_unregister_all(idtcm); 2290 return err; 2291 } 2292 2293 i2c_set_clientdata(client, idtcm); 2294 2295 return 0; 2296 } 2297 2298 static int idtcm_remove(struct i2c_client *client) 2299 { 2300 struct idtcm *idtcm = i2c_get_clientdata(client); 2301 2302 ptp_clock_unregister_all(idtcm); 2303 2304 mutex_destroy(&idtcm->reg_lock); 2305 2306 return 0; 2307 } 2308 2309 #ifdef CONFIG_OF 2310 static const struct of_device_id idtcm_dt_id[] = { 2311 { .compatible = "idt,8a34000" }, 2312 { .compatible = "idt,8a34001" }, 2313 { .compatible = "idt,8a34002" }, 2314 { .compatible = "idt,8a34003" }, 2315 { .compatible = "idt,8a34004" }, 2316 { .compatible = "idt,8a34005" }, 2317 { .compatible = "idt,8a34006" }, 2318 { .compatible = "idt,8a34007" }, 2319 { .compatible = "idt,8a34008" }, 2320 { .compatible = "idt,8a34009" }, 2321 { .compatible = "idt,8a34010" }, 2322 { .compatible = "idt,8a34011" }, 2323 { .compatible = "idt,8a34012" }, 2324 { .compatible = "idt,8a34013" }, 2325 { .compatible = "idt,8a34014" }, 2326 { .compatible = "idt,8a34015" }, 2327 { .compatible = "idt,8a34016" }, 2328 { .compatible = "idt,8a34017" }, 2329 { .compatible = "idt,8a34018" }, 2330 { .compatible = "idt,8a34019" }, 2331 { .compatible = "idt,8a34040" }, 2332 { .compatible = "idt,8a34041" }, 2333 { .compatible = "idt,8a34042" }, 2334 { .compatible = "idt,8a34043" }, 2335 { .compatible = "idt,8a34044" }, 2336 { .compatible = "idt,8a34045" }, 2337 { .compatible = "idt,8a34046" }, 2338 { .compatible = "idt,8a34047" }, 2339 { .compatible = "idt,8a34048" }, 2340 { .compatible = "idt,8a34049" }, 2341 {}, 2342 }; 2343 MODULE_DEVICE_TABLE(of, idtcm_dt_id); 2344 #endif 2345 2346 static const struct i2c_device_id idtcm_i2c_id[] = { 2347 { "8a34000" }, 2348 { "8a34001" }, 2349 { "8a34002" }, 2350 { "8a34003" }, 2351 { "8a34004" }, 2352 { "8a34005" }, 2353 { "8a34006" }, 2354 { "8a34007" }, 2355 { "8a34008" }, 2356 { "8a34009" }, 2357 { "8a34010" }, 2358 { "8a34011" }, 2359 { "8a34012" }, 2360 { "8a34013" }, 2361 { "8a34014" }, 2362 { "8a34015" }, 2363 { "8a34016" }, 2364 { "8a34017" }, 2365 { "8a34018" }, 2366 { "8a34019" }, 2367 { "8a34040" }, 2368 { "8a34041" }, 2369 { "8a34042" }, 2370 { "8a34043" }, 2371 { "8a34044" }, 2372 { "8a34045" }, 2373 { "8a34046" }, 2374 { "8a34047" }, 2375 { "8a34048" }, 2376 { "8a34049" }, 2377 {}, 2378 }; 2379 MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id); 2380 2381 static struct i2c_driver idtcm_driver = { 2382 .driver = { 2383 .of_match_table = of_match_ptr(idtcm_dt_id), 2384 .name = "idtcm", 2385 }, 2386 .probe = idtcm_probe, 2387 .remove = idtcm_remove, 2388 .id_table = idtcm_i2c_id, 2389 }; 2390 2391 module_i2c_driver(idtcm_driver); 2392