1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and 4 * synchronization devices. 5 * 6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. 7 */ 8 #include <linux/firmware.h> 9 #include <linux/i2c.h> 10 #include <linux/module.h> 11 #include <linux/ptp_clock_kernel.h> 12 #include <linux/delay.h> 13 #include <linux/kernel.h> 14 #include <linux/timekeeping.h> 15 16 #include "ptp_private.h" 17 #include "ptp_clockmatrix.h" 18 19 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family"); 20 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); 21 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>"); 22 MODULE_VERSION("1.0"); 23 MODULE_LICENSE("GPL"); 24 25 #define SETTIME_CORRECTION (0) 26 27 static int char_array_to_timespec(u8 *buf, 28 u8 count, 29 struct timespec64 *ts) 30 { 31 u8 i; 32 u64 nsec; 33 time64_t sec; 34 35 if (count < TOD_BYTE_COUNT) 36 return 1; 37 38 /* Sub-nanoseconds are in buf[0]. */ 39 nsec = buf[4]; 40 for (i = 0; i < 3; i++) { 41 nsec <<= 8; 42 nsec |= buf[3 - i]; 43 } 44 45 sec = buf[10]; 46 for (i = 0; i < 5; i++) { 47 sec <<= 8; 48 sec |= buf[9 - i]; 49 } 50 51 ts->tv_sec = sec; 52 ts->tv_nsec = nsec; 53 54 return 0; 55 } 56 57 static int timespec_to_char_array(struct timespec64 const *ts, 58 u8 *buf, 59 u8 count) 60 { 61 u8 i; 62 s32 nsec; 63 time64_t sec; 64 65 if (count < TOD_BYTE_COUNT) 66 return 1; 67 68 nsec = ts->tv_nsec; 69 sec = ts->tv_sec; 70 71 /* Sub-nanoseconds are in buf[0]. */ 72 buf[0] = 0; 73 for (i = 1; i < 5; i++) { 74 buf[i] = nsec & 0xff; 75 nsec >>= 8; 76 } 77 78 for (i = 5; i < TOD_BYTE_COUNT; i++) { 79 80 buf[i] = sec & 0xff; 81 sec >>= 8; 82 } 83 84 return 0; 85 } 86 87 static int idtcm_xfer(struct idtcm *idtcm, 88 u8 regaddr, 89 u8 *buf, 90 u16 count, 91 bool write) 92 { 93 struct i2c_client *client = idtcm->client; 94 struct i2c_msg msg[2]; 95 int cnt; 96 97 msg[0].addr = client->addr; 98 msg[0].flags = 0; 99 msg[0].len = 1; 100 msg[0].buf = ®addr; 101 102 msg[1].addr = client->addr; 103 msg[1].flags = write ? 0 : I2C_M_RD; 104 msg[1].len = count; 105 msg[1].buf = buf; 106 107 cnt = i2c_transfer(client->adapter, msg, 2); 108 109 if (cnt < 0) { 110 dev_err(&client->dev, "i2c_transfer returned %d\n", cnt); 111 return cnt; 112 } else if (cnt != 2) { 113 dev_err(&client->dev, 114 "i2c_transfer sent only %d of %d messages\n", cnt, 2); 115 return -EIO; 116 } 117 118 return 0; 119 } 120 121 static int idtcm_page_offset(struct idtcm *idtcm, u8 val) 122 { 123 u8 buf[4]; 124 int err; 125 126 if (idtcm->page_offset == val) 127 return 0; 128 129 buf[0] = 0x0; 130 buf[1] = val; 131 buf[2] = 0x10; 132 buf[3] = 0x20; 133 134 err = idtcm_xfer(idtcm, PAGE_ADDR, buf, sizeof(buf), 1); 135 136 if (err) 137 dev_err(&idtcm->client->dev, "failed to set page offset\n"); 138 else 139 idtcm->page_offset = val; 140 141 return err; 142 } 143 144 static int _idtcm_rdwr(struct idtcm *idtcm, 145 u16 regaddr, 146 u8 *buf, 147 u16 count, 148 bool write) 149 { 150 u8 hi; 151 u8 lo; 152 int err; 153 154 hi = (regaddr >> 8) & 0xff; 155 lo = regaddr & 0xff; 156 157 err = idtcm_page_offset(idtcm, hi); 158 159 if (err) 160 goto out; 161 162 err = idtcm_xfer(idtcm, lo, buf, count, write); 163 out: 164 return err; 165 } 166 167 static int idtcm_read(struct idtcm *idtcm, 168 u16 module, 169 u16 regaddr, 170 u8 *buf, 171 u16 count) 172 { 173 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false); 174 } 175 176 static int idtcm_write(struct idtcm *idtcm, 177 u16 module, 178 u16 regaddr, 179 u8 *buf, 180 u16 count) 181 { 182 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true); 183 } 184 185 static int _idtcm_gettime(struct idtcm_channel *channel, 186 struct timespec64 *ts) 187 { 188 struct idtcm *idtcm = channel->idtcm; 189 u8 buf[TOD_BYTE_COUNT]; 190 u8 trigger; 191 int err; 192 193 err = idtcm_read(idtcm, channel->tod_read_primary, 194 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger)); 195 if (err) 196 return err; 197 198 trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT); 199 trigger |= (1 << TOD_READ_TRIGGER_SHIFT); 200 trigger |= TOD_READ_TRIGGER_MODE; 201 202 err = idtcm_write(idtcm, channel->tod_read_primary, 203 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger)); 204 205 if (err) 206 return err; 207 208 if (idtcm->calculate_overhead_flag) 209 idtcm->start_time = ktime_get_raw(); 210 211 err = idtcm_read(idtcm, channel->tod_read_primary, 212 TOD_READ_PRIMARY, buf, sizeof(buf)); 213 214 if (err) 215 return err; 216 217 err = char_array_to_timespec(buf, sizeof(buf), ts); 218 219 return err; 220 } 221 222 static int _sync_pll_output(struct idtcm *idtcm, 223 u8 pll, 224 u8 sync_src, 225 u8 qn, 226 u8 qn_plus_1) 227 { 228 int err; 229 u8 val; 230 u16 sync_ctrl0; 231 u16 sync_ctrl1; 232 233 if ((qn == 0) && (qn_plus_1 == 0)) 234 return 0; 235 236 switch (pll) { 237 case 0: 238 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0; 239 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1; 240 break; 241 case 1: 242 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0; 243 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1; 244 break; 245 case 2: 246 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0; 247 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1; 248 break; 249 case 3: 250 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0; 251 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1; 252 break; 253 case 4: 254 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0; 255 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1; 256 break; 257 case 5: 258 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0; 259 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1; 260 break; 261 case 6: 262 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0; 263 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1; 264 break; 265 case 7: 266 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0; 267 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1; 268 break; 269 default: 270 return -EINVAL; 271 } 272 273 val = SYNCTRL1_MASTER_SYNC_RST; 274 275 /* Place master sync in reset */ 276 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 277 if (err) 278 return err; 279 280 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src)); 281 if (err) 282 return err; 283 284 /* Set sync trigger mask */ 285 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG; 286 287 if (qn) 288 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG; 289 290 if (qn_plus_1) 291 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG; 292 293 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 294 if (err) 295 return err; 296 297 /* Place master sync out of reset */ 298 val &= ~(SYNCTRL1_MASTER_SYNC_RST); 299 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 300 301 return err; 302 } 303 304 static int idtcm_sync_pps_output(struct idtcm_channel *channel) 305 { 306 struct idtcm *idtcm = channel->idtcm; 307 308 u8 pll; 309 u8 sync_src; 310 u8 qn; 311 u8 qn_plus_1; 312 int err = 0; 313 314 u16 output_mask = channel->output_mask; 315 316 switch (channel->dpll_n) { 317 case DPLL_0: 318 sync_src = SYNC_SOURCE_DPLL0_TOD_PPS; 319 break; 320 case DPLL_1: 321 sync_src = SYNC_SOURCE_DPLL1_TOD_PPS; 322 break; 323 case DPLL_2: 324 sync_src = SYNC_SOURCE_DPLL2_TOD_PPS; 325 break; 326 case DPLL_3: 327 sync_src = SYNC_SOURCE_DPLL3_TOD_PPS; 328 break; 329 default: 330 return -EINVAL; 331 } 332 333 for (pll = 0; pll < 8; pll++) { 334 335 qn = output_mask & 0x1; 336 output_mask = output_mask >> 1; 337 338 if (pll < 4) { 339 /* First 4 pll has 2 outputs */ 340 qn_plus_1 = output_mask & 0x1; 341 output_mask = output_mask >> 1; 342 } else { 343 qn_plus_1 = 0; 344 } 345 346 if ((qn != 0) || (qn_plus_1 != 0)) 347 err = _sync_pll_output(idtcm, pll, sync_src, qn, 348 qn_plus_1); 349 350 if (err) 351 return err; 352 } 353 354 return err; 355 } 356 357 static int _idtcm_set_dpll_tod(struct idtcm_channel *channel, 358 struct timespec64 const *ts, 359 enum hw_tod_write_trig_sel wr_trig) 360 { 361 struct idtcm *idtcm = channel->idtcm; 362 363 u8 buf[TOD_BYTE_COUNT]; 364 u8 cmd; 365 int err; 366 struct timespec64 local_ts = *ts; 367 s64 total_overhead_ns; 368 369 /* Configure HW TOD write trigger. */ 370 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 371 &cmd, sizeof(cmd)); 372 373 if (err) 374 return err; 375 376 cmd &= ~(0x0f); 377 cmd |= wr_trig | 0x08; 378 379 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 380 &cmd, sizeof(cmd)); 381 382 if (err) 383 return err; 384 385 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) { 386 387 err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); 388 389 if (err) 390 return err; 391 392 err = idtcm_write(idtcm, channel->hw_dpll_n, 393 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 394 395 if (err) 396 return err; 397 } 398 399 /* ARM HW TOD write trigger. */ 400 cmd &= ~(0x08); 401 402 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 403 &cmd, sizeof(cmd)); 404 405 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) { 406 407 if (idtcm->calculate_overhead_flag) { 408 total_overhead_ns = ktime_to_ns(ktime_get_raw() 409 - idtcm->start_time) 410 + idtcm->tod_write_overhead_ns 411 + SETTIME_CORRECTION; 412 413 timespec64_add_ns(&local_ts, total_overhead_ns); 414 415 idtcm->calculate_overhead_flag = 0; 416 } 417 418 err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); 419 420 if (err) 421 return err; 422 423 err = idtcm_write(idtcm, channel->hw_dpll_n, 424 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 425 } 426 427 return err; 428 } 429 430 static int _idtcm_settime(struct idtcm_channel *channel, 431 struct timespec64 const *ts, 432 enum hw_tod_write_trig_sel wr_trig) 433 { 434 struct idtcm *idtcm = channel->idtcm; 435 s32 retval; 436 int err; 437 int i; 438 u8 trig_sel; 439 440 err = _idtcm_set_dpll_tod(channel, ts, wr_trig); 441 442 if (err) 443 return err; 444 445 /* Wait for the operation to complete. */ 446 for (i = 0; i < 10000; i++) { 447 err = idtcm_read(idtcm, channel->hw_dpll_n, 448 HW_DPLL_TOD_CTRL_1, &trig_sel, 449 sizeof(trig_sel)); 450 451 if (err) 452 return err; 453 454 if (trig_sel == 0x4a) 455 break; 456 457 err = 1; 458 } 459 460 if (err) 461 return err; 462 463 retval = idtcm_sync_pps_output(channel); 464 465 return retval; 466 } 467 468 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel, 469 s32 offset_ns) 470 { 471 int err; 472 int i; 473 struct idtcm *idtcm = channel->idtcm; 474 475 u8 buf[4]; 476 477 for (i = 0; i < 4; i++) { 478 buf[i] = 0xff & (offset_ns); 479 offset_ns >>= 8; 480 } 481 482 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET, 483 buf, sizeof(buf)); 484 485 return err; 486 } 487 488 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel, 489 u32 max_ffo_ppb) 490 { 491 int err; 492 u8 i; 493 struct idtcm *idtcm = channel->idtcm; 494 495 u8 buf[3]; 496 497 if (max_ffo_ppb & 0xff000000) 498 max_ffo_ppb = 0; 499 500 for (i = 0; i < 3; i++) { 501 buf[i] = 0xff & (max_ffo_ppb); 502 max_ffo_ppb >>= 8; 503 } 504 505 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, 506 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf)); 507 508 return err; 509 } 510 511 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel) 512 { 513 int err; 514 struct idtcm *idtcm = channel->idtcm; 515 516 u8 buf; 517 518 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL, 519 &buf, sizeof(buf)); 520 521 if (err) 522 return err; 523 524 if (buf == 0) { 525 buf = 0x01; 526 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, 527 PULL_IN_CTRL, &buf, sizeof(buf)); 528 } else { 529 err = -EBUSY; 530 } 531 532 return err; 533 } 534 535 static int idtcm_do_phase_pull_in(struct idtcm_channel *channel, 536 s32 offset_ns, 537 u32 max_ffo_ppb) 538 { 539 int err; 540 541 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns); 542 543 if (err) 544 return err; 545 546 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb); 547 548 if (err) 549 return err; 550 551 err = idtcm_start_phase_pull_in(channel); 552 553 return err; 554 } 555 556 static int _idtcm_adjtime(struct idtcm_channel *channel, s64 delta) 557 { 558 int err; 559 struct idtcm *idtcm = channel->idtcm; 560 struct timespec64 ts; 561 s64 now; 562 563 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) { 564 err = idtcm_do_phase_pull_in(channel, delta, 0); 565 } else { 566 idtcm->calculate_overhead_flag = 1; 567 568 err = _idtcm_gettime(channel, &ts); 569 570 if (err) 571 return err; 572 573 now = timespec64_to_ns(&ts); 574 now += delta; 575 576 ts = ns_to_timespec64(now); 577 578 err = _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB); 579 } 580 581 return err; 582 } 583 584 static int idtcm_state_machine_reset(struct idtcm *idtcm) 585 { 586 int err; 587 u8 byte = SM_RESET_CMD; 588 589 err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte)); 590 591 if (!err) 592 msleep_interruptible(POST_SM_RESET_DELAY_MS); 593 594 return err; 595 } 596 597 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id) 598 { 599 return idtcm_read(idtcm, 600 GENERAL_STATUS, 601 HW_REV_ID, 602 hw_rev_id, 603 sizeof(u8)); 604 } 605 606 static int idtcm_read_bond_id(struct idtcm *idtcm, u8 *bond_id) 607 { 608 return idtcm_read(idtcm, 609 GENERAL_STATUS, 610 BOND_ID, 611 bond_id, 612 sizeof(u8)); 613 } 614 615 static int idtcm_read_hw_csr_id(struct idtcm *idtcm, u16 *hw_csr_id) 616 { 617 int err; 618 u8 buf[2] = {0}; 619 620 err = idtcm_read(idtcm, GENERAL_STATUS, HW_CSR_ID, buf, sizeof(buf)); 621 622 *hw_csr_id = (buf[1] << 8) | buf[0]; 623 624 return err; 625 } 626 627 static int idtcm_read_hw_irq_id(struct idtcm *idtcm, u16 *hw_irq_id) 628 { 629 int err; 630 u8 buf[2] = {0}; 631 632 err = idtcm_read(idtcm, GENERAL_STATUS, HW_IRQ_ID, buf, sizeof(buf)); 633 634 *hw_irq_id = (buf[1] << 8) | buf[0]; 635 636 return err; 637 } 638 639 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id) 640 { 641 int err; 642 u8 buf[2] = {0}; 643 644 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf)); 645 646 *product_id = (buf[1] << 8) | buf[0]; 647 648 return err; 649 } 650 651 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major) 652 { 653 int err; 654 u8 buf = 0; 655 656 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf)); 657 658 *major = buf >> 1; 659 660 return err; 661 } 662 663 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor) 664 { 665 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8)); 666 } 667 668 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix) 669 { 670 return idtcm_read(idtcm, 671 GENERAL_STATUS, 672 HOTFIX_REL, 673 hotfix, 674 sizeof(u8)); 675 } 676 677 static int idtcm_read_pipeline(struct idtcm *idtcm, u32 *pipeline) 678 { 679 int err; 680 u8 buf[4] = {0}; 681 682 err = idtcm_read(idtcm, 683 GENERAL_STATUS, 684 PIPELINE_ID, 685 &buf[0], 686 sizeof(buf)); 687 688 *pipeline = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 689 690 return err; 691 } 692 693 static int process_pll_mask(struct idtcm *idtcm, u32 addr, u8 val, u8 *mask) 694 { 695 int err = 0; 696 697 if (addr == PLL_MASK_ADDR) { 698 if ((val & 0xf0) || !(val & 0xf)) { 699 dev_err(&idtcm->client->dev, 700 "Invalid PLL mask 0x%hhx\n", val); 701 err = -EINVAL; 702 } 703 *mask = val; 704 } 705 706 return err; 707 } 708 709 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val) 710 { 711 int err = 0; 712 713 switch (addr) { 714 case OUTPUT_MASK_PLL0_ADDR: 715 SET_U16_LSB(idtcm->channel[0].output_mask, val); 716 break; 717 case OUTPUT_MASK_PLL0_ADDR + 1: 718 SET_U16_MSB(idtcm->channel[0].output_mask, val); 719 break; 720 case OUTPUT_MASK_PLL1_ADDR: 721 SET_U16_LSB(idtcm->channel[1].output_mask, val); 722 break; 723 case OUTPUT_MASK_PLL1_ADDR + 1: 724 SET_U16_MSB(idtcm->channel[1].output_mask, val); 725 break; 726 case OUTPUT_MASK_PLL2_ADDR: 727 SET_U16_LSB(idtcm->channel[2].output_mask, val); 728 break; 729 case OUTPUT_MASK_PLL2_ADDR + 1: 730 SET_U16_MSB(idtcm->channel[2].output_mask, val); 731 break; 732 case OUTPUT_MASK_PLL3_ADDR: 733 SET_U16_LSB(idtcm->channel[3].output_mask, val); 734 break; 735 case OUTPUT_MASK_PLL3_ADDR + 1: 736 SET_U16_MSB(idtcm->channel[3].output_mask, val); 737 break; 738 default: 739 err = -EINVAL; 740 break; 741 } 742 743 return err; 744 } 745 746 static int check_and_set_masks(struct idtcm *idtcm, 747 u16 regaddr, 748 u8 val) 749 { 750 int err = 0; 751 752 if (set_pll_output_mask(idtcm, regaddr, val)) { 753 /* Not an output mask, check for pll mask */ 754 err = process_pll_mask(idtcm, regaddr, val, &idtcm->pll_mask); 755 } 756 757 return err; 758 } 759 760 static void display_pll_and_output_masks(struct idtcm *idtcm) 761 { 762 u8 i; 763 u8 mask; 764 765 dev_dbg(&idtcm->client->dev, "pllmask = 0x%02x\n", idtcm->pll_mask); 766 767 for (i = 0; i < MAX_PHC_PLL; i++) { 768 mask = 1 << i; 769 770 if (mask & idtcm->pll_mask) 771 dev_dbg(&idtcm->client->dev, 772 "PLL%d output_mask = 0x%04x\n", 773 i, idtcm->channel[i].output_mask); 774 } 775 } 776 777 static int idtcm_load_firmware(struct idtcm *idtcm, 778 struct device *dev) 779 { 780 const struct firmware *fw; 781 struct idtcm_fwrc *rec; 782 u32 regaddr; 783 int err; 784 s32 len; 785 u8 val; 786 u8 loaddr; 787 788 dev_dbg(&idtcm->client->dev, "requesting firmware '%s'\n", FW_FILENAME); 789 790 err = request_firmware(&fw, FW_FILENAME, dev); 791 792 if (err) 793 return err; 794 795 dev_dbg(&idtcm->client->dev, "firmware size %zu bytes\n", fw->size); 796 797 rec = (struct idtcm_fwrc *) fw->data; 798 799 if (fw->size > 0) 800 idtcm_state_machine_reset(idtcm); 801 802 for (len = fw->size; len > 0; len -= sizeof(*rec)) { 803 804 if (rec->reserved) { 805 dev_err(&idtcm->client->dev, 806 "bad firmware, reserved field non-zero\n"); 807 err = -EINVAL; 808 } else { 809 regaddr = rec->hiaddr << 8; 810 regaddr |= rec->loaddr; 811 812 val = rec->value; 813 loaddr = rec->loaddr; 814 815 rec++; 816 817 err = check_and_set_masks(idtcm, regaddr, val); 818 } 819 820 if (err == 0) { 821 /* Top (status registers) and bottom are read-only */ 822 if ((regaddr < GPIO_USER_CONTROL) 823 || (regaddr >= SCRATCH)) 824 continue; 825 826 /* Page size 128, last 4 bytes of page skipped */ 827 if (((loaddr > 0x7b) && (loaddr <= 0x7f)) 828 || ((loaddr > 0xfb) && (loaddr <= 0xff))) 829 continue; 830 831 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val)); 832 } 833 834 if (err) 835 goto out; 836 } 837 838 display_pll_and_output_masks(idtcm); 839 840 out: 841 release_firmware(fw); 842 return err; 843 } 844 845 static int idtcm_pps_enable(struct idtcm_channel *channel, bool enable) 846 { 847 struct idtcm *idtcm = channel->idtcm; 848 u32 module; 849 u8 val; 850 int err; 851 852 /* 853 * This assumes that the 1-PPS is on the second of the two 854 * output. But is this always true? 855 */ 856 switch (channel->dpll_n) { 857 case DPLL_0: 858 module = OUTPUT_1; 859 break; 860 case DPLL_1: 861 module = OUTPUT_3; 862 break; 863 case DPLL_2: 864 module = OUTPUT_5; 865 break; 866 case DPLL_3: 867 module = OUTPUT_7; 868 break; 869 default: 870 return -EINVAL; 871 } 872 873 err = idtcm_read(idtcm, module, OUT_CTRL_1, &val, sizeof(val)); 874 875 if (err) 876 return err; 877 878 if (enable) 879 val |= SQUELCH_DISABLE; 880 else 881 val &= ~SQUELCH_DISABLE; 882 883 err = idtcm_write(idtcm, module, OUT_CTRL_1, &val, sizeof(val)); 884 885 if (err) 886 return err; 887 888 return 0; 889 } 890 891 static int idtcm_set_pll_mode(struct idtcm_channel *channel, 892 enum pll_mode pll_mode) 893 { 894 struct idtcm *idtcm = channel->idtcm; 895 int err; 896 u8 dpll_mode; 897 898 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE, 899 &dpll_mode, sizeof(dpll_mode)); 900 if (err) 901 return err; 902 903 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT); 904 905 dpll_mode |= (pll_mode << PLL_MODE_SHIFT); 906 907 channel->pll_mode = pll_mode; 908 909 err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE, 910 &dpll_mode, sizeof(dpll_mode)); 911 if (err) 912 return err; 913 914 return 0; 915 } 916 917 /* PTP Hardware Clock interface */ 918 919 static int idtcm_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 920 { 921 struct idtcm_channel *channel = 922 container_of(ptp, struct idtcm_channel, caps); 923 struct idtcm *idtcm = channel->idtcm; 924 u8 i; 925 bool neg_adj = 0; 926 int err; 927 u8 buf[6] = {0}; 928 s64 fcw; 929 930 if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) { 931 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY); 932 if (err) 933 return err; 934 } 935 936 /* 937 * Frequency Control Word unit is: 1.11 * 10^-10 ppm 938 * 939 * adjfreq: 940 * ppb * 10^9 941 * FCW = ---------- 942 * 111 943 * 944 * adjfine: 945 * ppm_16 * 5^12 946 * FCW = ------------- 947 * 111 * 2^4 948 */ 949 if (ppb < 0) { 950 neg_adj = 1; 951 ppb = -ppb; 952 } 953 954 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */ 955 fcw = ppb * 1000000000000ULL; 956 957 fcw = div_u64(fcw, 111022); 958 959 if (neg_adj) 960 fcw = -fcw; 961 962 for (i = 0; i < 6; i++) { 963 buf[i] = fcw & 0xff; 964 fcw >>= 8; 965 } 966 967 mutex_lock(&idtcm->reg_lock); 968 969 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ, 970 buf, sizeof(buf)); 971 972 mutex_unlock(&idtcm->reg_lock); 973 return err; 974 } 975 976 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 977 { 978 struct idtcm_channel *channel = 979 container_of(ptp, struct idtcm_channel, caps); 980 struct idtcm *idtcm = channel->idtcm; 981 int err; 982 983 mutex_lock(&idtcm->reg_lock); 984 985 err = _idtcm_gettime(channel, ts); 986 987 mutex_unlock(&idtcm->reg_lock); 988 989 return err; 990 } 991 992 static int idtcm_settime(struct ptp_clock_info *ptp, 993 const struct timespec64 *ts) 994 { 995 struct idtcm_channel *channel = 996 container_of(ptp, struct idtcm_channel, caps); 997 struct idtcm *idtcm = channel->idtcm; 998 int err; 999 1000 mutex_lock(&idtcm->reg_lock); 1001 1002 err = _idtcm_settime(channel, ts, HW_TOD_WR_TRIG_SEL_MSB); 1003 1004 mutex_unlock(&idtcm->reg_lock); 1005 1006 return err; 1007 } 1008 1009 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta) 1010 { 1011 struct idtcm_channel *channel = 1012 container_of(ptp, struct idtcm_channel, caps); 1013 struct idtcm *idtcm = channel->idtcm; 1014 int err; 1015 1016 mutex_lock(&idtcm->reg_lock); 1017 1018 err = _idtcm_adjtime(channel, delta); 1019 1020 mutex_unlock(&idtcm->reg_lock); 1021 1022 return err; 1023 } 1024 1025 static int idtcm_enable(struct ptp_clock_info *ptp, 1026 struct ptp_clock_request *rq, int on) 1027 { 1028 struct idtcm_channel *channel = 1029 container_of(ptp, struct idtcm_channel, caps); 1030 1031 switch (rq->type) { 1032 case PTP_CLK_REQ_PEROUT: 1033 if (!on) 1034 return idtcm_pps_enable(channel, false); 1035 1036 /* Only accept a 1-PPS aligned to the second. */ 1037 if (rq->perout.start.nsec || rq->perout.period.sec != 1 || 1038 rq->perout.period.nsec) 1039 return -ERANGE; 1040 1041 return idtcm_pps_enable(channel, true); 1042 default: 1043 break; 1044 } 1045 1046 return -EOPNOTSUPP; 1047 } 1048 1049 static int idtcm_enable_tod(struct idtcm_channel *channel) 1050 { 1051 struct idtcm *idtcm = channel->idtcm; 1052 struct timespec64 ts = {0, 0}; 1053 u8 cfg; 1054 int err; 1055 1056 err = idtcm_pps_enable(channel, false); 1057 if (err) 1058 return err; 1059 1060 /* 1061 * Start the TOD clock ticking. 1062 */ 1063 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg)); 1064 if (err) 1065 return err; 1066 1067 cfg |= TOD_ENABLE; 1068 1069 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg)); 1070 if (err) 1071 return err; 1072 1073 return _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB); 1074 } 1075 1076 static void idtcm_display_version_info(struct idtcm *idtcm) 1077 { 1078 u8 major; 1079 u8 minor; 1080 u8 hotfix; 1081 u32 pipeline; 1082 u16 product_id; 1083 u16 csr_id; 1084 u16 irq_id; 1085 u8 hw_rev_id; 1086 u8 bond_id; 1087 1088 idtcm_read_major_release(idtcm, &major); 1089 idtcm_read_minor_release(idtcm, &minor); 1090 idtcm_read_hotfix_release(idtcm, &hotfix); 1091 idtcm_read_pipeline(idtcm, &pipeline); 1092 1093 idtcm_read_product_id(idtcm, &product_id); 1094 idtcm_read_hw_rev_id(idtcm, &hw_rev_id); 1095 idtcm_read_bond_id(idtcm, &bond_id); 1096 idtcm_read_hw_csr_id(idtcm, &csr_id); 1097 idtcm_read_hw_irq_id(idtcm, &irq_id); 1098 1099 dev_info(&idtcm->client->dev, "Version: %d.%d.%d, Pipeline %u\t" 1100 "0x%04x, Rev %d, Bond %d, CSR %d, IRQ %d\n", 1101 major, minor, hotfix, pipeline, 1102 product_id, hw_rev_id, bond_id, csr_id, irq_id); 1103 } 1104 1105 static struct ptp_clock_info idtcm_caps = { 1106 .owner = THIS_MODULE, 1107 .max_adj = 244000, 1108 .n_per_out = 1, 1109 .adjfreq = &idtcm_adjfreq, 1110 .adjtime = &idtcm_adjtime, 1111 .gettime64 = &idtcm_gettime, 1112 .settime64 = &idtcm_settime, 1113 .enable = &idtcm_enable, 1114 }; 1115 1116 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) 1117 { 1118 struct idtcm_channel *channel; 1119 int err; 1120 1121 if (!(index < MAX_PHC_PLL)) 1122 return -EINVAL; 1123 1124 channel = &idtcm->channel[index]; 1125 1126 switch (index) { 1127 case 0: 1128 channel->dpll_freq = DPLL_FREQ_0; 1129 channel->dpll_n = DPLL_0; 1130 channel->tod_read_primary = TOD_READ_PRIMARY_0; 1131 channel->tod_write = TOD_WRITE_0; 1132 channel->tod_n = TOD_0; 1133 channel->hw_dpll_n = HW_DPLL_0; 1134 channel->dpll_phase = DPLL_PHASE_0; 1135 channel->dpll_ctrl_n = DPLL_CTRL_0; 1136 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0; 1137 break; 1138 case 1: 1139 channel->dpll_freq = DPLL_FREQ_1; 1140 channel->dpll_n = DPLL_1; 1141 channel->tod_read_primary = TOD_READ_PRIMARY_1; 1142 channel->tod_write = TOD_WRITE_1; 1143 channel->tod_n = TOD_1; 1144 channel->hw_dpll_n = HW_DPLL_1; 1145 channel->dpll_phase = DPLL_PHASE_1; 1146 channel->dpll_ctrl_n = DPLL_CTRL_1; 1147 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1; 1148 break; 1149 case 2: 1150 channel->dpll_freq = DPLL_FREQ_2; 1151 channel->dpll_n = DPLL_2; 1152 channel->tod_read_primary = TOD_READ_PRIMARY_2; 1153 channel->tod_write = TOD_WRITE_2; 1154 channel->tod_n = TOD_2; 1155 channel->hw_dpll_n = HW_DPLL_2; 1156 channel->dpll_phase = DPLL_PHASE_2; 1157 channel->dpll_ctrl_n = DPLL_CTRL_2; 1158 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2; 1159 break; 1160 case 3: 1161 channel->dpll_freq = DPLL_FREQ_3; 1162 channel->dpll_n = DPLL_3; 1163 channel->tod_read_primary = TOD_READ_PRIMARY_3; 1164 channel->tod_write = TOD_WRITE_3; 1165 channel->tod_n = TOD_3; 1166 channel->hw_dpll_n = HW_DPLL_3; 1167 channel->dpll_phase = DPLL_PHASE_3; 1168 channel->dpll_ctrl_n = DPLL_CTRL_3; 1169 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3; 1170 break; 1171 default: 1172 return -EINVAL; 1173 } 1174 1175 channel->idtcm = idtcm; 1176 1177 channel->caps = idtcm_caps; 1178 snprintf(channel->caps.name, sizeof(channel->caps.name), 1179 "IDT CM PLL%u", index); 1180 1181 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY); 1182 if (err) 1183 return err; 1184 1185 err = idtcm_enable_tod(channel); 1186 if (err) 1187 return err; 1188 1189 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL); 1190 1191 if (IS_ERR(channel->ptp_clock)) { 1192 err = PTR_ERR(channel->ptp_clock); 1193 channel->ptp_clock = NULL; 1194 return err; 1195 } 1196 1197 if (!channel->ptp_clock) 1198 return -ENOTSUPP; 1199 1200 dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d\n", 1201 index, channel->ptp_clock->index); 1202 1203 return 0; 1204 } 1205 1206 static void ptp_clock_unregister_all(struct idtcm *idtcm) 1207 { 1208 u8 i; 1209 struct idtcm_channel *channel; 1210 1211 for (i = 0; i < MAX_PHC_PLL; i++) { 1212 1213 channel = &idtcm->channel[i]; 1214 1215 if (channel->ptp_clock) 1216 ptp_clock_unregister(channel->ptp_clock); 1217 } 1218 } 1219 1220 static void set_default_masks(struct idtcm *idtcm) 1221 { 1222 idtcm->pll_mask = DEFAULT_PLL_MASK; 1223 1224 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0; 1225 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1; 1226 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2; 1227 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3; 1228 } 1229 1230 static int set_tod_write_overhead(struct idtcm *idtcm) 1231 { 1232 int err; 1233 u8 i; 1234 1235 s64 total_ns = 0; 1236 1237 ktime_t start; 1238 ktime_t stop; 1239 1240 char buf[TOD_BYTE_COUNT]; 1241 1242 struct idtcm_channel *channel = &idtcm->channel[2]; 1243 1244 /* Set page offset */ 1245 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0, 1246 buf, sizeof(buf)); 1247 1248 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) { 1249 1250 start = ktime_get_raw(); 1251 1252 err = idtcm_write(idtcm, channel->hw_dpll_n, 1253 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 1254 1255 if (err) 1256 return err; 1257 1258 stop = ktime_get_raw(); 1259 1260 total_ns += ktime_to_ns(stop - start); 1261 } 1262 1263 idtcm->tod_write_overhead_ns = div_s64(total_ns, 1264 TOD_WRITE_OVERHEAD_COUNT_MAX); 1265 1266 return err; 1267 } 1268 1269 static int idtcm_probe(struct i2c_client *client, 1270 const struct i2c_device_id *id) 1271 { 1272 struct idtcm *idtcm; 1273 int err; 1274 u8 i; 1275 1276 /* Unused for now */ 1277 (void)id; 1278 1279 idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL); 1280 1281 if (!idtcm) 1282 return -ENOMEM; 1283 1284 idtcm->client = client; 1285 idtcm->page_offset = 0xff; 1286 idtcm->calculate_overhead_flag = 0; 1287 1288 set_default_masks(idtcm); 1289 1290 mutex_init(&idtcm->reg_lock); 1291 mutex_lock(&idtcm->reg_lock); 1292 1293 idtcm_display_version_info(idtcm); 1294 1295 err = set_tod_write_overhead(idtcm); 1296 1297 if (err) { 1298 mutex_unlock(&idtcm->reg_lock); 1299 return err; 1300 } 1301 1302 err = idtcm_load_firmware(idtcm, &client->dev); 1303 1304 if (err) 1305 dev_warn(&idtcm->client->dev, 1306 "loading firmware failed with %d\n", err); 1307 1308 if (idtcm->pll_mask) { 1309 for (i = 0; i < MAX_PHC_PLL; i++) { 1310 if (idtcm->pll_mask & (1 << i)) { 1311 err = idtcm_enable_channel(idtcm, i); 1312 if (err) 1313 break; 1314 } 1315 } 1316 } else { 1317 dev_err(&idtcm->client->dev, 1318 "no PLLs flagged as PHCs, nothing to do\n"); 1319 err = -ENODEV; 1320 } 1321 1322 mutex_unlock(&idtcm->reg_lock); 1323 1324 if (err) { 1325 ptp_clock_unregister_all(idtcm); 1326 return err; 1327 } 1328 1329 i2c_set_clientdata(client, idtcm); 1330 1331 return 0; 1332 } 1333 1334 static int idtcm_remove(struct i2c_client *client) 1335 { 1336 struct idtcm *idtcm = i2c_get_clientdata(client); 1337 1338 ptp_clock_unregister_all(idtcm); 1339 1340 mutex_destroy(&idtcm->reg_lock); 1341 1342 return 0; 1343 } 1344 1345 #ifdef CONFIG_OF 1346 static const struct of_device_id idtcm_dt_id[] = { 1347 { .compatible = "idt,8a34000" }, 1348 { .compatible = "idt,8a34001" }, 1349 { .compatible = "idt,8a34002" }, 1350 { .compatible = "idt,8a34003" }, 1351 { .compatible = "idt,8a34004" }, 1352 { .compatible = "idt,8a34005" }, 1353 { .compatible = "idt,8a34006" }, 1354 { .compatible = "idt,8a34007" }, 1355 { .compatible = "idt,8a34008" }, 1356 { .compatible = "idt,8a34009" }, 1357 { .compatible = "idt,8a34010" }, 1358 { .compatible = "idt,8a34011" }, 1359 { .compatible = "idt,8a34012" }, 1360 { .compatible = "idt,8a34013" }, 1361 { .compatible = "idt,8a34014" }, 1362 { .compatible = "idt,8a34015" }, 1363 { .compatible = "idt,8a34016" }, 1364 { .compatible = "idt,8a34017" }, 1365 { .compatible = "idt,8a34018" }, 1366 { .compatible = "idt,8a34019" }, 1367 { .compatible = "idt,8a34040" }, 1368 { .compatible = "idt,8a34041" }, 1369 { .compatible = "idt,8a34042" }, 1370 { .compatible = "idt,8a34043" }, 1371 { .compatible = "idt,8a34044" }, 1372 { .compatible = "idt,8a34045" }, 1373 { .compatible = "idt,8a34046" }, 1374 { .compatible = "idt,8a34047" }, 1375 { .compatible = "idt,8a34048" }, 1376 { .compatible = "idt,8a34049" }, 1377 {}, 1378 }; 1379 MODULE_DEVICE_TABLE(of, idtcm_dt_id); 1380 #endif 1381 1382 static const struct i2c_device_id idtcm_i2c_id[] = { 1383 { "8a34000" }, 1384 { "8a34001" }, 1385 { "8a34002" }, 1386 { "8a34003" }, 1387 { "8a34004" }, 1388 { "8a34005" }, 1389 { "8a34006" }, 1390 { "8a34007" }, 1391 { "8a34008" }, 1392 { "8a34009" }, 1393 { "8a34010" }, 1394 { "8a34011" }, 1395 { "8a34012" }, 1396 { "8a34013" }, 1397 { "8a34014" }, 1398 { "8a34015" }, 1399 { "8a34016" }, 1400 { "8a34017" }, 1401 { "8a34018" }, 1402 { "8a34019" }, 1403 { "8a34040" }, 1404 { "8a34041" }, 1405 { "8a34042" }, 1406 { "8a34043" }, 1407 { "8a34044" }, 1408 { "8a34045" }, 1409 { "8a34046" }, 1410 { "8a34047" }, 1411 { "8a34048" }, 1412 { "8a34049" }, 1413 {}, 1414 }; 1415 MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id); 1416 1417 static struct i2c_driver idtcm_driver = { 1418 .driver = { 1419 .of_match_table = of_match_ptr(idtcm_dt_id), 1420 .name = "idtcm", 1421 }, 1422 .probe = idtcm_probe, 1423 .remove = idtcm_remove, 1424 .id_table = idtcm_i2c_id, 1425 }; 1426 1427 module_i2c_driver(idtcm_driver); 1428