1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and 4 * synchronization devices. 5 * 6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. 7 */ 8 #include <linux/firmware.h> 9 #include <linux/i2c.h> 10 #include <linux/module.h> 11 #include <linux/ptp_clock_kernel.h> 12 #include <linux/delay.h> 13 #include <linux/jiffies.h> 14 #include <linux/kernel.h> 15 #include <linux/timekeeping.h> 16 #include <linux/string.h> 17 18 #include "ptp_private.h" 19 #include "ptp_clockmatrix.h" 20 21 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family"); 22 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); 23 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>"); 24 MODULE_VERSION("1.0"); 25 MODULE_LICENSE("GPL"); 26 27 /* 28 * The name of the firmware file to be loaded 29 * over-rides any automatic selection 30 */ 31 static char *firmware; 32 module_param(firmware, charp, 0); 33 34 #define SETTIME_CORRECTION (0) 35 36 static int contains_full_configuration(struct idtcm *idtcm, 37 const struct firmware *fw) 38 { 39 struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data; 40 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH); 41 s32 full_count; 42 s32 count = 0; 43 u16 regaddr; 44 u8 loaddr; 45 s32 len; 46 47 /* 4 bytes skipped every 0x80 */ 48 full_count = (scratch - GPIO_USER_CONTROL) - 49 ((scratch >> 7) - (GPIO_USER_CONTROL >> 7)) * 4; 50 51 /* If the firmware contains 'full configuration' SM_RESET can be used 52 * to ensure proper configuration. 53 * 54 * Full configuration is defined as the number of programmable 55 * bytes within the configuration range minus page offset addr range. 56 */ 57 for (len = fw->size; len > 0; len -= sizeof(*rec)) { 58 regaddr = rec->hiaddr << 8; 59 regaddr |= rec->loaddr; 60 61 loaddr = rec->loaddr; 62 63 rec++; 64 65 /* Top (status registers) and bottom are read-only */ 66 if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch) 67 continue; 68 69 /* Page size 128, last 4 bytes of page skipped */ 70 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb) 71 continue; 72 73 count++; 74 } 75 76 return (count >= full_count); 77 } 78 79 static int char_array_to_timespec(u8 *buf, 80 u8 count, 81 struct timespec64 *ts) 82 { 83 u8 i; 84 u64 nsec; 85 time64_t sec; 86 87 if (count < TOD_BYTE_COUNT) 88 return 1; 89 90 /* Sub-nanoseconds are in buf[0]. */ 91 nsec = buf[4]; 92 for (i = 0; i < 3; i++) { 93 nsec <<= 8; 94 nsec |= buf[3 - i]; 95 } 96 97 sec = buf[10]; 98 for (i = 0; i < 5; i++) { 99 sec <<= 8; 100 sec |= buf[9 - i]; 101 } 102 103 ts->tv_sec = sec; 104 ts->tv_nsec = nsec; 105 106 return 0; 107 } 108 109 static int timespec_to_char_array(struct timespec64 const *ts, 110 u8 *buf, 111 u8 count) 112 { 113 u8 i; 114 s32 nsec; 115 time64_t sec; 116 117 if (count < TOD_BYTE_COUNT) 118 return 1; 119 120 nsec = ts->tv_nsec; 121 sec = ts->tv_sec; 122 123 /* Sub-nanoseconds are in buf[0]. */ 124 buf[0] = 0; 125 for (i = 1; i < 5; i++) { 126 buf[i] = nsec & 0xff; 127 nsec >>= 8; 128 } 129 130 for (i = 5; i < TOD_BYTE_COUNT; i++) { 131 132 buf[i] = sec & 0xff; 133 sec >>= 8; 134 } 135 136 return 0; 137 } 138 139 static int idtcm_strverscmp(const char *version1, const char *version2) 140 { 141 u8 ver1[3], ver2[3]; 142 int i; 143 144 if (sscanf(version1, "%hhu.%hhu.%hhu", 145 &ver1[0], &ver1[1], &ver1[2]) != 3) 146 return -1; 147 if (sscanf(version2, "%hhu.%hhu.%hhu", 148 &ver2[0], &ver2[1], &ver2[2]) != 3) 149 return -1; 150 151 for (i = 0; i < 3; i++) { 152 if (ver1[i] > ver2[i]) 153 return 1; 154 if (ver1[i] < ver2[i]) 155 return -1; 156 } 157 158 return 0; 159 } 160 161 static enum fw_version idtcm_fw_version(const char *version) 162 { 163 enum fw_version ver = V_DEFAULT; 164 165 if (idtcm_strverscmp(version, "4.8.7") >= 0) 166 ver = V487; 167 168 if (idtcm_strverscmp(version, "5.2.0") >= 0) 169 ver = V520; 170 171 return ver; 172 } 173 174 static int idtcm_xfer_read(struct idtcm *idtcm, 175 u8 regaddr, 176 u8 *buf, 177 u16 count) 178 { 179 struct i2c_client *client = idtcm->client; 180 struct i2c_msg msg[2]; 181 int cnt; 182 183 msg[0].addr = client->addr; 184 msg[0].flags = 0; 185 msg[0].len = 1; 186 msg[0].buf = ®addr; 187 188 msg[1].addr = client->addr; 189 msg[1].flags = I2C_M_RD; 190 msg[1].len = count; 191 msg[1].buf = buf; 192 193 cnt = i2c_transfer(client->adapter, msg, 2); 194 195 if (cnt < 0) { 196 dev_err(&client->dev, 197 "i2c_transfer failed at %d in %s, at addr: %04x!", 198 __LINE__, __func__, regaddr); 199 return cnt; 200 } else if (cnt != 2) { 201 dev_err(&client->dev, 202 "i2c_transfer sent only %d of %d messages", cnt, 2); 203 return -EIO; 204 } 205 206 return 0; 207 } 208 209 static int idtcm_xfer_write(struct idtcm *idtcm, 210 u8 regaddr, 211 u8 *buf, 212 u16 count) 213 { 214 struct i2c_client *client = idtcm->client; 215 /* we add 1 byte for device register */ 216 u8 msg[IDTCM_MAX_WRITE_COUNT + 1]; 217 int cnt; 218 219 if (count > IDTCM_MAX_WRITE_COUNT) 220 return -EINVAL; 221 222 msg[0] = regaddr; 223 memcpy(&msg[1], buf, count); 224 225 cnt = i2c_master_send(client, msg, count + 1); 226 227 if (cnt < 0) { 228 dev_err(&client->dev, 229 "i2c_master_send failed at %d in %s, at addr: %04x!", 230 __LINE__, __func__, regaddr); 231 return cnt; 232 } 233 234 return 0; 235 } 236 237 static int idtcm_page_offset(struct idtcm *idtcm, u8 val) 238 { 239 u8 buf[4]; 240 int err; 241 242 if (idtcm->page_offset == val) 243 return 0; 244 245 buf[0] = 0x0; 246 buf[1] = val; 247 buf[2] = 0x10; 248 buf[3] = 0x20; 249 250 err = idtcm_xfer_write(idtcm, PAGE_ADDR, buf, sizeof(buf)); 251 if (err) { 252 idtcm->page_offset = 0xff; 253 dev_err(&idtcm->client->dev, "failed to set page offset"); 254 } else { 255 idtcm->page_offset = val; 256 } 257 258 return err; 259 } 260 261 static int _idtcm_rdwr(struct idtcm *idtcm, 262 u16 regaddr, 263 u8 *buf, 264 u16 count, 265 bool write) 266 { 267 u8 hi; 268 u8 lo; 269 int err; 270 271 hi = (regaddr >> 8) & 0xff; 272 lo = regaddr & 0xff; 273 274 err = idtcm_page_offset(idtcm, hi); 275 if (err) 276 return err; 277 278 if (write) 279 return idtcm_xfer_write(idtcm, lo, buf, count); 280 281 return idtcm_xfer_read(idtcm, lo, buf, count); 282 } 283 284 static int idtcm_read(struct idtcm *idtcm, 285 u16 module, 286 u16 regaddr, 287 u8 *buf, 288 u16 count) 289 { 290 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false); 291 } 292 293 static int idtcm_write(struct idtcm *idtcm, 294 u16 module, 295 u16 regaddr, 296 u8 *buf, 297 u16 count) 298 { 299 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true); 300 } 301 302 static int clear_boot_status(struct idtcm *idtcm) 303 { 304 u8 buf[4] = {0}; 305 306 return idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf)); 307 } 308 309 static int read_boot_status(struct idtcm *idtcm, u32 *status) 310 { 311 int err; 312 u8 buf[4] = {0}; 313 314 err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf)); 315 316 *status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 317 318 return err; 319 } 320 321 static int wait_for_boot_status_ready(struct idtcm *idtcm) 322 { 323 u32 status = 0; 324 u8 i = 30; /* 30 * 100ms = 3s */ 325 int err; 326 327 do { 328 err = read_boot_status(idtcm, &status); 329 if (err) 330 return err; 331 332 if (status == 0xA0) 333 return 0; 334 335 msleep(100); 336 i--; 337 338 } while (i); 339 340 dev_warn(&idtcm->client->dev, "%s timed out", __func__); 341 342 return -EBUSY; 343 } 344 345 static int read_sys_apll_status(struct idtcm *idtcm, u8 *status) 346 { 347 return idtcm_read(idtcm, STATUS, DPLL_SYS_APLL_STATUS, status, 348 sizeof(u8)); 349 } 350 351 static int read_sys_dpll_status(struct idtcm *idtcm, u8 *status) 352 { 353 return idtcm_read(idtcm, STATUS, DPLL_SYS_STATUS, status, sizeof(u8)); 354 } 355 356 static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm) 357 { 358 unsigned long timeout = jiffies + msecs_to_jiffies(LOCK_TIMEOUT_MS); 359 u8 apll = 0; 360 u8 dpll = 0; 361 int err; 362 363 do { 364 err = read_sys_apll_status(idtcm, &apll); 365 if (err) 366 return err; 367 368 err = read_sys_dpll_status(idtcm, &dpll); 369 if (err) 370 return err; 371 372 apll &= SYS_APLL_LOSS_LOCK_LIVE_MASK; 373 dpll &= DPLL_SYS_STATE_MASK; 374 375 if (apll == SYS_APLL_LOSS_LOCK_LIVE_LOCKED && 376 dpll == DPLL_STATE_LOCKED) { 377 return 0; 378 } else if (dpll == DPLL_STATE_FREERUN || 379 dpll == DPLL_STATE_HOLDOVER || 380 dpll == DPLL_STATE_OPEN_LOOP) { 381 dev_warn(&idtcm->client->dev, 382 "No wait state: DPLL_SYS_STATE %d", dpll); 383 return -EPERM; 384 } 385 386 msleep(LOCK_POLL_INTERVAL_MS); 387 } while (time_is_after_jiffies(timeout)); 388 389 dev_warn(&idtcm->client->dev, 390 "%d ms lock timeout: SYS APLL Loss Lock %d SYS DPLL state %d", 391 LOCK_TIMEOUT_MS, apll, dpll); 392 393 return -ETIME; 394 } 395 396 static void wait_for_chip_ready(struct idtcm *idtcm) 397 { 398 if (wait_for_boot_status_ready(idtcm)) 399 dev_warn(&idtcm->client->dev, "BOOT_STATUS != 0xA0"); 400 401 if (wait_for_sys_apll_dpll_lock(idtcm)) 402 dev_warn(&idtcm->client->dev, 403 "Continuing while SYS APLL/DPLL is not locked"); 404 } 405 406 static int _idtcm_gettime(struct idtcm_channel *channel, 407 struct timespec64 *ts) 408 { 409 struct idtcm *idtcm = channel->idtcm; 410 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD); 411 u8 buf[TOD_BYTE_COUNT]; 412 u8 timeout = 10; 413 u8 trigger; 414 int err; 415 416 err = idtcm_read(idtcm, channel->tod_read_primary, 417 tod_read_cmd, &trigger, sizeof(trigger)); 418 if (err) 419 return err; 420 421 trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT); 422 trigger |= (1 << TOD_READ_TRIGGER_SHIFT); 423 trigger &= ~TOD_READ_TRIGGER_MODE; /* single shot */ 424 425 err = idtcm_write(idtcm, channel->tod_read_primary, 426 tod_read_cmd, &trigger, sizeof(trigger)); 427 if (err) 428 return err; 429 430 /* wait trigger to be 0 */ 431 while (trigger & TOD_READ_TRIGGER_MASK) { 432 if (idtcm->calculate_overhead_flag) 433 idtcm->start_time = ktime_get_raw(); 434 435 err = idtcm_read(idtcm, channel->tod_read_primary, 436 tod_read_cmd, &trigger, 437 sizeof(trigger)); 438 if (err) 439 return err; 440 441 if (--timeout == 0) 442 return -EIO; 443 } 444 445 err = idtcm_read(idtcm, channel->tod_read_primary, 446 TOD_READ_PRIMARY, buf, sizeof(buf)); 447 if (err) 448 return err; 449 450 err = char_array_to_timespec(buf, sizeof(buf), ts); 451 452 return err; 453 } 454 455 static int _sync_pll_output(struct idtcm *idtcm, 456 u8 pll, 457 u8 sync_src, 458 u8 qn, 459 u8 qn_plus_1) 460 { 461 int err; 462 u8 val; 463 u16 sync_ctrl0; 464 u16 sync_ctrl1; 465 u8 temp; 466 467 if (qn == 0 && qn_plus_1 == 0) 468 return 0; 469 470 switch (pll) { 471 case 0: 472 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0; 473 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1; 474 break; 475 case 1: 476 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0; 477 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1; 478 break; 479 case 2: 480 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0; 481 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1; 482 break; 483 case 3: 484 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0; 485 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1; 486 break; 487 case 4: 488 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0; 489 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1; 490 break; 491 case 5: 492 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0; 493 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1; 494 break; 495 case 6: 496 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0; 497 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1; 498 break; 499 case 7: 500 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0; 501 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1; 502 break; 503 default: 504 return -EINVAL; 505 } 506 507 val = SYNCTRL1_MASTER_SYNC_RST; 508 509 /* Place master sync in reset */ 510 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 511 if (err) 512 return err; 513 514 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src)); 515 if (err) 516 return err; 517 518 /* Set sync trigger mask */ 519 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG; 520 521 if (qn) 522 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG; 523 524 if (qn_plus_1) 525 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG; 526 527 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 528 if (err) 529 return err; 530 531 /* PLL5 can have OUT8 as second additional output. */ 532 if (pll == 5 && qn_plus_1 != 0) { 533 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE, 534 &temp, sizeof(temp)); 535 if (err) 536 return err; 537 538 temp &= ~(Q9_TO_Q8_SYNC_TRIG); 539 540 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE, 541 &temp, sizeof(temp)); 542 if (err) 543 return err; 544 545 temp |= Q9_TO_Q8_SYNC_TRIG; 546 547 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE, 548 &temp, sizeof(temp)); 549 if (err) 550 return err; 551 } 552 553 /* PLL6 can have OUT11 as second additional output. */ 554 if (pll == 6 && qn_plus_1 != 0) { 555 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE, 556 &temp, sizeof(temp)); 557 if (err) 558 return err; 559 560 temp &= ~(Q10_TO_Q11_SYNC_TRIG); 561 562 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE, 563 &temp, sizeof(temp)); 564 if (err) 565 return err; 566 567 temp |= Q10_TO_Q11_SYNC_TRIG; 568 569 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE, 570 &temp, sizeof(temp)); 571 if (err) 572 return err; 573 } 574 575 /* Place master sync out of reset */ 576 val &= ~(SYNCTRL1_MASTER_SYNC_RST); 577 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 578 579 return err; 580 } 581 582 static int idtcm_sync_pps_output(struct idtcm_channel *channel) 583 { 584 struct idtcm *idtcm = channel->idtcm; 585 u8 pll; 586 u8 qn; 587 u8 qn_plus_1; 588 int err = 0; 589 u8 out8_mux = 0; 590 u8 out11_mux = 0; 591 u8 temp; 592 u16 output_mask = channel->output_mask; 593 594 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE, 595 &temp, sizeof(temp)); 596 if (err) 597 return err; 598 599 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) == 600 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) 601 out8_mux = 1; 602 603 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE, 604 &temp, sizeof(temp)); 605 if (err) 606 return err; 607 608 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) == 609 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) 610 out11_mux = 1; 611 612 for (pll = 0; pll < 8; pll++) { 613 qn = 0; 614 qn_plus_1 = 0; 615 616 if (pll < 4) { 617 /* First 4 pll has 2 outputs */ 618 qn = output_mask & 0x1; 619 output_mask = output_mask >> 1; 620 qn_plus_1 = output_mask & 0x1; 621 output_mask = output_mask >> 1; 622 } else if (pll == 4) { 623 if (out8_mux == 0) { 624 qn = output_mask & 0x1; 625 output_mask = output_mask >> 1; 626 } 627 } else if (pll == 5) { 628 if (out8_mux) { 629 qn_plus_1 = output_mask & 0x1; 630 output_mask = output_mask >> 1; 631 } 632 qn = output_mask & 0x1; 633 output_mask = output_mask >> 1; 634 } else if (pll == 6) { 635 qn = output_mask & 0x1; 636 output_mask = output_mask >> 1; 637 if (out11_mux) { 638 qn_plus_1 = output_mask & 0x1; 639 output_mask = output_mask >> 1; 640 } 641 } else if (pll == 7) { 642 if (out11_mux == 0) { 643 qn = output_mask & 0x1; 644 output_mask = output_mask >> 1; 645 } 646 } 647 648 if (qn != 0 || qn_plus_1 != 0) 649 err = _sync_pll_output(idtcm, pll, channel->sync_src, 650 qn, qn_plus_1); 651 652 if (err) 653 return err; 654 } 655 656 return err; 657 } 658 659 static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel, 660 struct timespec64 const *ts, 661 enum hw_tod_write_trig_sel wr_trig) 662 { 663 struct idtcm *idtcm = channel->idtcm; 664 u8 buf[TOD_BYTE_COUNT]; 665 u8 cmd; 666 int err; 667 struct timespec64 local_ts = *ts; 668 s64 total_overhead_ns; 669 670 /* Configure HW TOD write trigger. */ 671 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 672 &cmd, sizeof(cmd)); 673 if (err) 674 return err; 675 676 cmd &= ~(0x0f); 677 cmd |= wr_trig | 0x08; 678 679 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 680 &cmd, sizeof(cmd)); 681 if (err) 682 return err; 683 684 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) { 685 err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); 686 if (err) 687 return err; 688 689 err = idtcm_write(idtcm, channel->hw_dpll_n, 690 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 691 if (err) 692 return err; 693 } 694 695 /* ARM HW TOD write trigger. */ 696 cmd &= ~(0x08); 697 698 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 699 &cmd, sizeof(cmd)); 700 701 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) { 702 if (idtcm->calculate_overhead_flag) { 703 /* Assumption: I2C @ 400KHz */ 704 ktime_t diff = ktime_sub(ktime_get_raw(), 705 idtcm->start_time); 706 total_overhead_ns = ktime_to_ns(diff) 707 + idtcm->tod_write_overhead_ns 708 + SETTIME_CORRECTION; 709 710 timespec64_add_ns(&local_ts, total_overhead_ns); 711 712 idtcm->calculate_overhead_flag = 0; 713 } 714 715 err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); 716 if (err) 717 return err; 718 719 err = idtcm_write(idtcm, channel->hw_dpll_n, 720 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 721 } 722 723 return err; 724 } 725 726 static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel, 727 struct timespec64 const *ts, 728 enum scsr_tod_write_trig_sel wr_trig, 729 enum scsr_tod_write_type_sel wr_type) 730 { 731 struct idtcm *idtcm = channel->idtcm; 732 unsigned char buf[TOD_BYTE_COUNT], cmd; 733 struct timespec64 local_ts = *ts; 734 int err, count = 0; 735 736 timespec64_add_ns(&local_ts, SETTIME_CORRECTION); 737 738 err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); 739 if (err) 740 return err; 741 742 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE, 743 buf, sizeof(buf)); 744 if (err) 745 return err; 746 747 /* Trigger the write operation. */ 748 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD, 749 &cmd, sizeof(cmd)); 750 if (err) 751 return err; 752 753 cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT); 754 cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT); 755 cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT); 756 cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT); 757 758 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD, 759 &cmd, sizeof(cmd)); 760 if (err) 761 return err; 762 763 /* Wait for the operation to complete. */ 764 while (1) { 765 /* pps trigger takes up to 1 sec to complete */ 766 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS) 767 msleep(50); 768 769 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD, 770 &cmd, sizeof(cmd)); 771 if (err) 772 return err; 773 774 if ((cmd & TOD_WRITE_SELECTION_MASK) == 0) 775 break; 776 777 if (++count > 20) { 778 dev_err(&idtcm->client->dev, 779 "Timed out waiting for the write counter"); 780 return -EIO; 781 } 782 } 783 784 return 0; 785 } 786 787 static int get_output_base_addr(enum fw_version ver, u8 outn) 788 { 789 int base; 790 791 switch (outn) { 792 case 0: 793 base = IDTCM_FW_REG(ver, V520, OUTPUT_0); 794 break; 795 case 1: 796 base = IDTCM_FW_REG(ver, V520, OUTPUT_1); 797 break; 798 case 2: 799 base = IDTCM_FW_REG(ver, V520, OUTPUT_2); 800 break; 801 case 3: 802 base = IDTCM_FW_REG(ver, V520, OUTPUT_3); 803 break; 804 case 4: 805 base = IDTCM_FW_REG(ver, V520, OUTPUT_4); 806 break; 807 case 5: 808 base = IDTCM_FW_REG(ver, V520, OUTPUT_5); 809 break; 810 case 6: 811 base = IDTCM_FW_REG(ver, V520, OUTPUT_6); 812 break; 813 case 7: 814 base = IDTCM_FW_REG(ver, V520, OUTPUT_7); 815 break; 816 case 8: 817 base = IDTCM_FW_REG(ver, V520, OUTPUT_8); 818 break; 819 case 9: 820 base = IDTCM_FW_REG(ver, V520, OUTPUT_9); 821 break; 822 case 10: 823 base = IDTCM_FW_REG(ver, V520, OUTPUT_10); 824 break; 825 case 11: 826 base = IDTCM_FW_REG(ver, V520, OUTPUT_11); 827 break; 828 default: 829 base = -EINVAL; 830 } 831 832 return base; 833 } 834 835 static int _idtcm_settime_deprecated(struct idtcm_channel *channel, 836 struct timespec64 const *ts) 837 { 838 struct idtcm *idtcm = channel->idtcm; 839 int err; 840 841 err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB); 842 if (err) { 843 dev_err(&idtcm->client->dev, 844 "%s: Set HW ToD failed", __func__); 845 return err; 846 } 847 848 return idtcm_sync_pps_output(channel); 849 } 850 851 static int _idtcm_settime(struct idtcm_channel *channel, 852 struct timespec64 const *ts, 853 enum scsr_tod_write_type_sel wr_type) 854 { 855 return _idtcm_set_dpll_scsr_tod(channel, ts, 856 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE, 857 wr_type); 858 } 859 860 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel, 861 s32 offset_ns) 862 { 863 int err; 864 int i; 865 struct idtcm *idtcm = channel->idtcm; 866 u8 buf[4]; 867 868 for (i = 0; i < 4; i++) { 869 buf[i] = 0xff & (offset_ns); 870 offset_ns >>= 8; 871 } 872 873 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET, 874 buf, sizeof(buf)); 875 876 return err; 877 } 878 879 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel, 880 u32 max_ffo_ppb) 881 { 882 int err; 883 u8 i; 884 struct idtcm *idtcm = channel->idtcm; 885 u8 buf[3]; 886 887 if (max_ffo_ppb & 0xff000000) 888 max_ffo_ppb = 0; 889 890 for (i = 0; i < 3; i++) { 891 buf[i] = 0xff & (max_ffo_ppb); 892 max_ffo_ppb >>= 8; 893 } 894 895 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, 896 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf)); 897 898 return err; 899 } 900 901 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel) 902 { 903 int err; 904 struct idtcm *idtcm = channel->idtcm; 905 u8 buf; 906 907 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL, 908 &buf, sizeof(buf)); 909 if (err) 910 return err; 911 912 if (buf == 0) { 913 buf = 0x01; 914 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, 915 PULL_IN_CTRL, &buf, sizeof(buf)); 916 } else { 917 err = -EBUSY; 918 } 919 920 return err; 921 } 922 923 static int idtcm_do_phase_pull_in(struct idtcm_channel *channel, 924 s32 offset_ns, 925 u32 max_ffo_ppb) 926 { 927 int err; 928 929 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns); 930 if (err) 931 return err; 932 933 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb); 934 if (err) 935 return err; 936 937 err = idtcm_start_phase_pull_in(channel); 938 939 return err; 940 } 941 942 static int set_tod_write_overhead(struct idtcm_channel *channel) 943 { 944 struct idtcm *idtcm = channel->idtcm; 945 s64 current_ns = 0; 946 s64 lowest_ns = 0; 947 int err; 948 u8 i; 949 ktime_t start; 950 ktime_t stop; 951 ktime_t diff; 952 953 char buf[TOD_BYTE_COUNT] = {0}; 954 955 /* Set page offset */ 956 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0, 957 buf, sizeof(buf)); 958 959 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) { 960 start = ktime_get_raw(); 961 962 err = idtcm_write(idtcm, channel->hw_dpll_n, 963 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 964 if (err) 965 return err; 966 967 stop = ktime_get_raw(); 968 969 diff = ktime_sub(stop, start); 970 971 current_ns = ktime_to_ns(diff); 972 973 if (i == 0) { 974 lowest_ns = current_ns; 975 } else { 976 if (current_ns < lowest_ns) 977 lowest_ns = current_ns; 978 } 979 } 980 981 idtcm->tod_write_overhead_ns = lowest_ns; 982 983 return err; 984 } 985 986 static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta) 987 { 988 int err; 989 struct idtcm *idtcm = channel->idtcm; 990 struct timespec64 ts; 991 s64 now; 992 993 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) { 994 err = idtcm_do_phase_pull_in(channel, delta, 0); 995 } else { 996 idtcm->calculate_overhead_flag = 1; 997 998 err = set_tod_write_overhead(channel); 999 if (err) 1000 return err; 1001 1002 err = _idtcm_gettime(channel, &ts); 1003 if (err) 1004 return err; 1005 1006 now = timespec64_to_ns(&ts); 1007 now += delta; 1008 1009 ts = ns_to_timespec64(now); 1010 1011 err = _idtcm_settime_deprecated(channel, &ts); 1012 } 1013 1014 return err; 1015 } 1016 1017 static int idtcm_state_machine_reset(struct idtcm *idtcm) 1018 { 1019 u8 byte = SM_RESET_CMD; 1020 u32 status = 0; 1021 int err; 1022 u8 i; 1023 1024 clear_boot_status(idtcm); 1025 1026 err = idtcm_write(idtcm, RESET_CTRL, 1027 IDTCM_FW_REG(idtcm->fw_ver, V520, SM_RESET), 1028 &byte, sizeof(byte)); 1029 1030 if (!err) { 1031 for (i = 0; i < 30; i++) { 1032 msleep_interruptible(100); 1033 read_boot_status(idtcm, &status); 1034 1035 if (status == 0xA0) { 1036 dev_dbg(&idtcm->client->dev, 1037 "SM_RESET completed in %d ms", i * 100); 1038 break; 1039 } 1040 } 1041 1042 if (!status) 1043 dev_err(&idtcm->client->dev, 1044 "Timed out waiting for CM_RESET to complete"); 1045 } 1046 1047 return err; 1048 } 1049 1050 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id) 1051 { 1052 return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8)); 1053 } 1054 1055 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id) 1056 { 1057 int err; 1058 u8 buf[2] = {0}; 1059 1060 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf)); 1061 1062 *product_id = (buf[1] << 8) | buf[0]; 1063 1064 return err; 1065 } 1066 1067 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major) 1068 { 1069 int err; 1070 u8 buf = 0; 1071 1072 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf)); 1073 1074 *major = buf >> 1; 1075 1076 return err; 1077 } 1078 1079 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor) 1080 { 1081 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8)); 1082 } 1083 1084 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix) 1085 { 1086 return idtcm_read(idtcm, 1087 GENERAL_STATUS, 1088 HOTFIX_REL, 1089 hotfix, 1090 sizeof(u8)); 1091 } 1092 1093 static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm, 1094 u8 *config_select) 1095 { 1096 return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT, 1097 config_select, sizeof(u8)); 1098 } 1099 1100 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val) 1101 { 1102 int err = 0; 1103 1104 switch (addr) { 1105 case TOD0_OUT_ALIGN_MASK_ADDR: 1106 SET_U16_LSB(idtcm->channel[0].output_mask, val); 1107 break; 1108 case TOD0_OUT_ALIGN_MASK_ADDR + 1: 1109 SET_U16_MSB(idtcm->channel[0].output_mask, val); 1110 break; 1111 case TOD1_OUT_ALIGN_MASK_ADDR: 1112 SET_U16_LSB(idtcm->channel[1].output_mask, val); 1113 break; 1114 case TOD1_OUT_ALIGN_MASK_ADDR + 1: 1115 SET_U16_MSB(idtcm->channel[1].output_mask, val); 1116 break; 1117 case TOD2_OUT_ALIGN_MASK_ADDR: 1118 SET_U16_LSB(idtcm->channel[2].output_mask, val); 1119 break; 1120 case TOD2_OUT_ALIGN_MASK_ADDR + 1: 1121 SET_U16_MSB(idtcm->channel[2].output_mask, val); 1122 break; 1123 case TOD3_OUT_ALIGN_MASK_ADDR: 1124 SET_U16_LSB(idtcm->channel[3].output_mask, val); 1125 break; 1126 case TOD3_OUT_ALIGN_MASK_ADDR + 1: 1127 SET_U16_MSB(idtcm->channel[3].output_mask, val); 1128 break; 1129 default: 1130 err = -EFAULT; /* Bad address */; 1131 break; 1132 } 1133 1134 return err; 1135 } 1136 1137 static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll) 1138 { 1139 if (index >= MAX_TOD) { 1140 dev_err(&idtcm->client->dev, "ToD%d not supported", index); 1141 return -EINVAL; 1142 } 1143 1144 if (pll >= MAX_PLL) { 1145 dev_err(&idtcm->client->dev, "Pll%d not supported", pll); 1146 return -EINVAL; 1147 } 1148 1149 idtcm->channel[index].pll = pll; 1150 1151 return 0; 1152 } 1153 1154 static int check_and_set_masks(struct idtcm *idtcm, 1155 u16 regaddr, 1156 u8 val) 1157 { 1158 int err = 0; 1159 1160 switch (regaddr) { 1161 case TOD_MASK_ADDR: 1162 if ((val & 0xf0) || !(val & 0x0f)) { 1163 dev_err(&idtcm->client->dev, "Invalid TOD mask 0x%02x", val); 1164 err = -EINVAL; 1165 } else { 1166 idtcm->tod_mask = val; 1167 } 1168 break; 1169 case TOD0_PTP_PLL_ADDR: 1170 err = set_tod_ptp_pll(idtcm, 0, val); 1171 break; 1172 case TOD1_PTP_PLL_ADDR: 1173 err = set_tod_ptp_pll(idtcm, 1, val); 1174 break; 1175 case TOD2_PTP_PLL_ADDR: 1176 err = set_tod_ptp_pll(idtcm, 2, val); 1177 break; 1178 case TOD3_PTP_PLL_ADDR: 1179 err = set_tod_ptp_pll(idtcm, 3, val); 1180 break; 1181 default: 1182 err = set_pll_output_mask(idtcm, regaddr, val); 1183 break; 1184 } 1185 1186 return err; 1187 } 1188 1189 static void display_pll_and_masks(struct idtcm *idtcm) 1190 { 1191 u8 i; 1192 u8 mask; 1193 1194 dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x", idtcm->tod_mask); 1195 1196 for (i = 0; i < MAX_TOD; i++) { 1197 mask = 1 << i; 1198 1199 if (mask & idtcm->tod_mask) 1200 dev_dbg(&idtcm->client->dev, 1201 "TOD%d pll = %d output_mask = 0x%04x", 1202 i, idtcm->channel[i].pll, 1203 idtcm->channel[i].output_mask); 1204 } 1205 } 1206 1207 static int idtcm_load_firmware(struct idtcm *idtcm, 1208 struct device *dev) 1209 { 1210 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH); 1211 char fname[128] = FW_FILENAME; 1212 const struct firmware *fw; 1213 struct idtcm_fwrc *rec; 1214 u32 regaddr; 1215 int err; 1216 s32 len; 1217 u8 val; 1218 u8 loaddr; 1219 1220 if (firmware) /* module parameter */ 1221 snprintf(fname, sizeof(fname), "%s", firmware); 1222 1223 dev_dbg(&idtcm->client->dev, "requesting firmware '%s'", fname); 1224 1225 err = request_firmware(&fw, fname, dev); 1226 if (err) { 1227 dev_err(&idtcm->client->dev, 1228 "Failed at line %d in %s!", __LINE__, __func__); 1229 return err; 1230 } 1231 1232 dev_dbg(&idtcm->client->dev, "firmware size %zu bytes", fw->size); 1233 1234 rec = (struct idtcm_fwrc *) fw->data; 1235 1236 if (contains_full_configuration(idtcm, fw)) 1237 idtcm_state_machine_reset(idtcm); 1238 1239 for (len = fw->size; len > 0; len -= sizeof(*rec)) { 1240 if (rec->reserved) { 1241 dev_err(&idtcm->client->dev, 1242 "bad firmware, reserved field non-zero"); 1243 err = -EINVAL; 1244 } else { 1245 regaddr = rec->hiaddr << 8; 1246 regaddr |= rec->loaddr; 1247 1248 val = rec->value; 1249 loaddr = rec->loaddr; 1250 1251 rec++; 1252 1253 err = check_and_set_masks(idtcm, regaddr, val); 1254 } 1255 1256 if (err != -EINVAL) { 1257 err = 0; 1258 1259 /* Top (status registers) and bottom are read-only */ 1260 if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch) 1261 continue; 1262 1263 /* Page size 128, last 4 bytes of page skipped */ 1264 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb) 1265 continue; 1266 1267 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val)); 1268 } 1269 1270 if (err) 1271 goto out; 1272 } 1273 1274 display_pll_and_masks(idtcm); 1275 1276 out: 1277 release_firmware(fw); 1278 return err; 1279 } 1280 1281 static int idtcm_output_enable(struct idtcm_channel *channel, 1282 bool enable, unsigned int outn) 1283 { 1284 struct idtcm *idtcm = channel->idtcm; 1285 int base; 1286 int err; 1287 u8 val; 1288 1289 base = get_output_base_addr(idtcm->fw_ver, outn); 1290 1291 if (!(base > 0)) { 1292 dev_err(&idtcm->client->dev, 1293 "%s - Unsupported out%d", __func__, outn); 1294 return base; 1295 } 1296 1297 err = idtcm_read(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val)); 1298 if (err) 1299 return err; 1300 1301 if (enable) 1302 val |= SQUELCH_DISABLE; 1303 else 1304 val &= ~SQUELCH_DISABLE; 1305 1306 return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val)); 1307 } 1308 1309 static int idtcm_output_mask_enable(struct idtcm_channel *channel, 1310 bool enable) 1311 { 1312 u16 mask; 1313 int err; 1314 u8 outn; 1315 1316 mask = channel->output_mask; 1317 outn = 0; 1318 1319 while (mask) { 1320 if (mask & 0x1) { 1321 err = idtcm_output_enable(channel, enable, outn); 1322 if (err) 1323 return err; 1324 } 1325 1326 mask >>= 0x1; 1327 outn++; 1328 } 1329 1330 return 0; 1331 } 1332 1333 static int idtcm_perout_enable(struct idtcm_channel *channel, 1334 bool enable, 1335 struct ptp_perout_request *perout) 1336 { 1337 struct idtcm *idtcm = channel->idtcm; 1338 unsigned int flags = perout->flags; 1339 struct timespec64 ts = {0, 0}; 1340 int err; 1341 1342 if (flags == PEROUT_ENABLE_OUTPUT_MASK) 1343 err = idtcm_output_mask_enable(channel, enable); 1344 else 1345 err = idtcm_output_enable(channel, enable, perout->index); 1346 1347 if (err) { 1348 dev_err(&idtcm->client->dev, "Unable to set output enable"); 1349 return err; 1350 } 1351 1352 /* Align output to internal 1 PPS */ 1353 return _idtcm_settime(channel, &ts, SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS); 1354 } 1355 1356 static int idtcm_get_pll_mode(struct idtcm_channel *channel, 1357 enum pll_mode *pll_mode) 1358 { 1359 struct idtcm *idtcm = channel->idtcm; 1360 int err; 1361 u8 dpll_mode; 1362 1363 err = idtcm_read(idtcm, channel->dpll_n, 1364 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE), 1365 &dpll_mode, sizeof(dpll_mode)); 1366 if (err) 1367 return err; 1368 1369 *pll_mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK; 1370 1371 return 0; 1372 } 1373 1374 static int idtcm_set_pll_mode(struct idtcm_channel *channel, 1375 enum pll_mode pll_mode) 1376 { 1377 struct idtcm *idtcm = channel->idtcm; 1378 int err; 1379 u8 dpll_mode; 1380 1381 err = idtcm_read(idtcm, channel->dpll_n, 1382 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE), 1383 &dpll_mode, sizeof(dpll_mode)); 1384 if (err) 1385 return err; 1386 1387 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT); 1388 1389 dpll_mode |= (pll_mode << PLL_MODE_SHIFT); 1390 1391 channel->pll_mode = pll_mode; 1392 1393 err = idtcm_write(idtcm, channel->dpll_n, 1394 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE), 1395 &dpll_mode, sizeof(dpll_mode)); 1396 if (err) 1397 return err; 1398 1399 return 0; 1400 } 1401 1402 /* PTP Hardware Clock interface */ 1403 1404 /** 1405 * @brief Maximum absolute value for write phase offset in picoseconds 1406 * 1407 * Destination signed register is 32-bit register in resolution of 50ps 1408 * 1409 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350 1410 */ 1411 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns) 1412 { 1413 struct idtcm *idtcm = channel->idtcm; 1414 int err; 1415 u8 i; 1416 u8 buf[4] = {0}; 1417 s32 phase_50ps; 1418 s64 offset_ps; 1419 1420 if (channel->pll_mode != PLL_MODE_WRITE_PHASE) { 1421 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE); 1422 if (err) 1423 return err; 1424 } 1425 1426 offset_ps = (s64)delta_ns * 1000; 1427 1428 /* 1429 * Check for 32-bit signed max * 50: 1430 * 1431 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350 1432 */ 1433 if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS) 1434 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS; 1435 else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS) 1436 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS; 1437 1438 phase_50ps = div_s64(offset_ps, 50); 1439 1440 for (i = 0; i < 4; i++) { 1441 buf[i] = phase_50ps & 0xff; 1442 phase_50ps >>= 8; 1443 } 1444 1445 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE, 1446 buf, sizeof(buf)); 1447 1448 return err; 1449 } 1450 1451 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm) 1452 { 1453 struct idtcm *idtcm = channel->idtcm; 1454 u8 i; 1455 int err; 1456 u8 buf[6] = {0}; 1457 s64 fcw; 1458 1459 if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) { 1460 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY); 1461 if (err) 1462 return err; 1463 } 1464 1465 /* 1466 * Frequency Control Word unit is: 1.11 * 10^-10 ppm 1467 * 1468 * adjfreq: 1469 * ppb * 10^9 1470 * FCW = ---------- 1471 * 111 1472 * 1473 * adjfine: 1474 * ppm_16 * 5^12 1475 * FCW = ------------- 1476 * 111 * 2^4 1477 */ 1478 1479 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */ 1480 fcw = scaled_ppm * 244140625ULL; 1481 1482 fcw = div_s64(fcw, 1776); 1483 1484 for (i = 0; i < 6; i++) { 1485 buf[i] = fcw & 0xff; 1486 fcw >>= 8; 1487 } 1488 1489 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ, 1490 buf, sizeof(buf)); 1491 1492 return err; 1493 } 1494 1495 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 1496 { 1497 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1498 struct idtcm *idtcm = channel->idtcm; 1499 int err; 1500 1501 mutex_lock(&idtcm->reg_lock); 1502 1503 err = _idtcm_gettime(channel, ts); 1504 if (err) 1505 dev_err(&idtcm->client->dev, "Failed at line %d in %s!", 1506 __LINE__, __func__); 1507 1508 mutex_unlock(&idtcm->reg_lock); 1509 1510 return err; 1511 } 1512 1513 static int idtcm_settime_deprecated(struct ptp_clock_info *ptp, 1514 const struct timespec64 *ts) 1515 { 1516 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1517 struct idtcm *idtcm = channel->idtcm; 1518 int err; 1519 1520 mutex_lock(&idtcm->reg_lock); 1521 1522 err = _idtcm_settime_deprecated(channel, ts); 1523 if (err) 1524 dev_err(&idtcm->client->dev, 1525 "Failed at line %d in %s!", __LINE__, __func__); 1526 1527 mutex_unlock(&idtcm->reg_lock); 1528 1529 return err; 1530 } 1531 1532 static int idtcm_settime(struct ptp_clock_info *ptp, 1533 const struct timespec64 *ts) 1534 { 1535 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1536 struct idtcm *idtcm = channel->idtcm; 1537 int err; 1538 1539 mutex_lock(&idtcm->reg_lock); 1540 1541 err = _idtcm_settime(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE); 1542 if (err) 1543 dev_err(&idtcm->client->dev, 1544 "Failed at line %d in %s!", __LINE__, __func__); 1545 1546 mutex_unlock(&idtcm->reg_lock); 1547 1548 return err; 1549 } 1550 1551 static int idtcm_adjtime_deprecated(struct ptp_clock_info *ptp, s64 delta) 1552 { 1553 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1554 struct idtcm *idtcm = channel->idtcm; 1555 int err; 1556 1557 mutex_lock(&idtcm->reg_lock); 1558 1559 err = _idtcm_adjtime_deprecated(channel, delta); 1560 if (err) 1561 dev_err(&idtcm->client->dev, 1562 "Failed at line %d in %s!", __LINE__, __func__); 1563 1564 mutex_unlock(&idtcm->reg_lock); 1565 1566 return err; 1567 } 1568 1569 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta) 1570 { 1571 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1572 struct idtcm *idtcm = channel->idtcm; 1573 struct timespec64 ts; 1574 enum scsr_tod_write_type_sel type; 1575 int err; 1576 1577 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) { 1578 err = idtcm_do_phase_pull_in(channel, delta, 0); 1579 if (err) 1580 dev_err(&idtcm->client->dev, 1581 "Failed at line %d in %s!", __LINE__, __func__); 1582 return err; 1583 } 1584 1585 if (delta >= 0) { 1586 ts = ns_to_timespec64(delta); 1587 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS; 1588 } else { 1589 ts = ns_to_timespec64(-delta); 1590 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS; 1591 } 1592 1593 mutex_lock(&idtcm->reg_lock); 1594 1595 err = _idtcm_settime(channel, &ts, type); 1596 if (err) 1597 dev_err(&idtcm->client->dev, 1598 "Failed at line %d in %s!", __LINE__, __func__); 1599 1600 mutex_unlock(&idtcm->reg_lock); 1601 1602 return err; 1603 } 1604 1605 static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta) 1606 { 1607 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1608 struct idtcm *idtcm = channel->idtcm; 1609 int err; 1610 1611 mutex_lock(&idtcm->reg_lock); 1612 1613 err = _idtcm_adjphase(channel, delta); 1614 if (err) 1615 dev_err(&idtcm->client->dev, 1616 "Failed at line %d in %s!", __LINE__, __func__); 1617 1618 mutex_unlock(&idtcm->reg_lock); 1619 1620 return err; 1621 } 1622 1623 static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 1624 { 1625 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1626 struct idtcm *idtcm = channel->idtcm; 1627 int err; 1628 1629 mutex_lock(&idtcm->reg_lock); 1630 1631 err = _idtcm_adjfine(channel, scaled_ppm); 1632 if (err) 1633 dev_err(&idtcm->client->dev, 1634 "Failed at line %d in %s!", __LINE__, __func__); 1635 1636 mutex_unlock(&idtcm->reg_lock); 1637 1638 return err; 1639 } 1640 1641 static int idtcm_enable(struct ptp_clock_info *ptp, 1642 struct ptp_clock_request *rq, int on) 1643 { 1644 int err; 1645 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1646 1647 switch (rq->type) { 1648 case PTP_CLK_REQ_PEROUT: 1649 if (!on) { 1650 err = idtcm_perout_enable(channel, false, &rq->perout); 1651 if (err) 1652 dev_err(&channel->idtcm->client->dev, 1653 "Failed at line %d in %s!", 1654 __LINE__, __func__); 1655 return err; 1656 } 1657 1658 /* Only accept a 1-PPS aligned to the second. */ 1659 if (rq->perout.start.nsec || rq->perout.period.sec != 1 || 1660 rq->perout.period.nsec) 1661 return -ERANGE; 1662 1663 err = idtcm_perout_enable(channel, true, &rq->perout); 1664 if (err) 1665 dev_err(&channel->idtcm->client->dev, 1666 "Failed at line %d in %s!", __LINE__, __func__); 1667 return err; 1668 default: 1669 break; 1670 } 1671 1672 return -EOPNOTSUPP; 1673 } 1674 1675 static int idtcm_enable_tod(struct idtcm_channel *channel) 1676 { 1677 struct idtcm *idtcm = channel->idtcm; 1678 struct timespec64 ts = {0, 0}; 1679 u16 tod_cfg = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_CFG); 1680 u8 cfg; 1681 int err; 1682 1683 /* STEELAI-366 - Temporary workaround for ts2phc compatibility */ 1684 if (0) { 1685 err = idtcm_output_mask_enable(channel, false); 1686 if (err) 1687 return err; 1688 } 1689 1690 /* 1691 * Start the TOD clock ticking. 1692 */ 1693 err = idtcm_read(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg)); 1694 if (err) 1695 return err; 1696 1697 cfg |= TOD_ENABLE; 1698 1699 err = idtcm_write(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg)); 1700 if (err) 1701 return err; 1702 1703 if (idtcm->fw_ver < V487) 1704 return _idtcm_settime_deprecated(channel, &ts); 1705 else 1706 return _idtcm_settime(channel, &ts, 1707 SCSR_TOD_WR_TYPE_SEL_ABSOLUTE); 1708 } 1709 1710 static void idtcm_set_version_info(struct idtcm *idtcm) 1711 { 1712 u8 major; 1713 u8 minor; 1714 u8 hotfix; 1715 u16 product_id; 1716 u8 hw_rev_id; 1717 u8 config_select; 1718 1719 idtcm_read_major_release(idtcm, &major); 1720 idtcm_read_minor_release(idtcm, &minor); 1721 idtcm_read_hotfix_release(idtcm, &hotfix); 1722 1723 idtcm_read_product_id(idtcm, &product_id); 1724 idtcm_read_hw_rev_id(idtcm, &hw_rev_id); 1725 1726 idtcm_read_otp_scsr_config_select(idtcm, &config_select); 1727 1728 snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u", 1729 major, minor, hotfix); 1730 1731 idtcm->fw_ver = idtcm_fw_version(idtcm->version); 1732 1733 dev_info(&idtcm->client->dev, 1734 "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d", 1735 major, minor, hotfix, 1736 product_id, hw_rev_id, config_select); 1737 } 1738 1739 static const struct ptp_clock_info idtcm_caps = { 1740 .owner = THIS_MODULE, 1741 .max_adj = 244000, 1742 .n_per_out = 12, 1743 .adjphase = &idtcm_adjphase, 1744 .adjfine = &idtcm_adjfine, 1745 .adjtime = &idtcm_adjtime, 1746 .gettime64 = &idtcm_gettime, 1747 .settime64 = &idtcm_settime, 1748 .enable = &idtcm_enable, 1749 }; 1750 1751 static const struct ptp_clock_info idtcm_caps_deprecated = { 1752 .owner = THIS_MODULE, 1753 .max_adj = 244000, 1754 .n_per_out = 12, 1755 .adjphase = &idtcm_adjphase, 1756 .adjfine = &idtcm_adjfine, 1757 .adjtime = &idtcm_adjtime_deprecated, 1758 .gettime64 = &idtcm_gettime, 1759 .settime64 = &idtcm_settime_deprecated, 1760 .enable = &idtcm_enable, 1761 }; 1762 1763 static int configure_channel_pll(struct idtcm_channel *channel) 1764 { 1765 struct idtcm *idtcm = channel->idtcm; 1766 int err = 0; 1767 1768 switch (channel->pll) { 1769 case 0: 1770 channel->dpll_freq = DPLL_FREQ_0; 1771 channel->dpll_n = DPLL_0; 1772 channel->hw_dpll_n = HW_DPLL_0; 1773 channel->dpll_phase = DPLL_PHASE_0; 1774 channel->dpll_ctrl_n = DPLL_CTRL_0; 1775 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0; 1776 break; 1777 case 1: 1778 channel->dpll_freq = DPLL_FREQ_1; 1779 channel->dpll_n = DPLL_1; 1780 channel->hw_dpll_n = HW_DPLL_1; 1781 channel->dpll_phase = DPLL_PHASE_1; 1782 channel->dpll_ctrl_n = DPLL_CTRL_1; 1783 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1; 1784 break; 1785 case 2: 1786 channel->dpll_freq = DPLL_FREQ_2; 1787 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_2); 1788 channel->hw_dpll_n = HW_DPLL_2; 1789 channel->dpll_phase = DPLL_PHASE_2; 1790 channel->dpll_ctrl_n = DPLL_CTRL_2; 1791 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2; 1792 break; 1793 case 3: 1794 channel->dpll_freq = DPLL_FREQ_3; 1795 channel->dpll_n = DPLL_3; 1796 channel->hw_dpll_n = HW_DPLL_3; 1797 channel->dpll_phase = DPLL_PHASE_3; 1798 channel->dpll_ctrl_n = DPLL_CTRL_3; 1799 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3; 1800 break; 1801 case 4: 1802 channel->dpll_freq = DPLL_FREQ_4; 1803 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_4); 1804 channel->hw_dpll_n = HW_DPLL_4; 1805 channel->dpll_phase = DPLL_PHASE_4; 1806 channel->dpll_ctrl_n = DPLL_CTRL_4; 1807 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4; 1808 break; 1809 case 5: 1810 channel->dpll_freq = DPLL_FREQ_5; 1811 channel->dpll_n = DPLL_5; 1812 channel->hw_dpll_n = HW_DPLL_5; 1813 channel->dpll_phase = DPLL_PHASE_5; 1814 channel->dpll_ctrl_n = DPLL_CTRL_5; 1815 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5; 1816 break; 1817 case 6: 1818 channel->dpll_freq = DPLL_FREQ_6; 1819 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_6); 1820 channel->hw_dpll_n = HW_DPLL_6; 1821 channel->dpll_phase = DPLL_PHASE_6; 1822 channel->dpll_ctrl_n = DPLL_CTRL_6; 1823 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6; 1824 break; 1825 case 7: 1826 channel->dpll_freq = DPLL_FREQ_7; 1827 channel->dpll_n = DPLL_7; 1828 channel->hw_dpll_n = HW_DPLL_7; 1829 channel->dpll_phase = DPLL_PHASE_7; 1830 channel->dpll_ctrl_n = DPLL_CTRL_7; 1831 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7; 1832 break; 1833 default: 1834 err = -EINVAL; 1835 } 1836 1837 return err; 1838 } 1839 1840 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) 1841 { 1842 enum fw_version fw_ver = idtcm->fw_ver; 1843 struct idtcm_channel *channel; 1844 int err; 1845 1846 if (!(index < MAX_TOD)) 1847 return -EINVAL; 1848 1849 channel = &idtcm->channel[index]; 1850 channel->idtcm = idtcm; 1851 1852 /* Set pll addresses */ 1853 err = configure_channel_pll(channel); 1854 if (err) 1855 return err; 1856 1857 /* Set tod addresses */ 1858 switch (index) { 1859 case 0: 1860 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_0); 1861 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_0); 1862 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_0); 1863 channel->sync_src = SYNC_SOURCE_DPLL0_TOD_PPS; 1864 break; 1865 case 1: 1866 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_1); 1867 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_1); 1868 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_1); 1869 channel->sync_src = SYNC_SOURCE_DPLL1_TOD_PPS; 1870 break; 1871 case 2: 1872 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_2); 1873 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_2); 1874 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_2); 1875 channel->sync_src = SYNC_SOURCE_DPLL2_TOD_PPS; 1876 break; 1877 case 3: 1878 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_3); 1879 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_3); 1880 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_3); 1881 channel->sync_src = SYNC_SOURCE_DPLL3_TOD_PPS; 1882 break; 1883 default: 1884 return -EINVAL; 1885 } 1886 1887 if (idtcm->fw_ver < V487) 1888 channel->caps = idtcm_caps_deprecated; 1889 else 1890 channel->caps = idtcm_caps; 1891 1892 snprintf(channel->caps.name, sizeof(channel->caps.name), 1893 "IDT CM TOD%u", index); 1894 1895 /* Sync pll mode with hardware */ 1896 err = idtcm_get_pll_mode(channel, &channel->pll_mode); 1897 if (err) { 1898 dev_err(&idtcm->client->dev, 1899 "Error: %s - Unable to read pll mode", __func__); 1900 return err; 1901 } 1902 1903 err = idtcm_enable_tod(channel); 1904 if (err) { 1905 dev_err(&idtcm->client->dev, 1906 "Failed at line %d in %s!", __LINE__, __func__); 1907 return err; 1908 } 1909 1910 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL); 1911 1912 if (IS_ERR(channel->ptp_clock)) { 1913 err = PTR_ERR(channel->ptp_clock); 1914 channel->ptp_clock = NULL; 1915 return err; 1916 } 1917 1918 if (!channel->ptp_clock) 1919 return -ENOTSUPP; 1920 1921 dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d", 1922 index, channel->ptp_clock->index); 1923 1924 return 0; 1925 } 1926 1927 static void ptp_clock_unregister_all(struct idtcm *idtcm) 1928 { 1929 u8 i; 1930 struct idtcm_channel *channel; 1931 1932 for (i = 0; i < MAX_TOD; i++) { 1933 channel = &idtcm->channel[i]; 1934 1935 if (channel->ptp_clock) 1936 ptp_clock_unregister(channel->ptp_clock); 1937 } 1938 } 1939 1940 static void set_default_masks(struct idtcm *idtcm) 1941 { 1942 idtcm->tod_mask = DEFAULT_TOD_MASK; 1943 1944 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL; 1945 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL; 1946 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL; 1947 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL; 1948 1949 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0; 1950 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1; 1951 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2; 1952 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3; 1953 } 1954 1955 static int idtcm_probe(struct i2c_client *client, 1956 const struct i2c_device_id *id) 1957 { 1958 struct idtcm *idtcm; 1959 int err; 1960 u8 i; 1961 1962 /* Unused for now */ 1963 (void)id; 1964 1965 idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL); 1966 1967 if (!idtcm) 1968 return -ENOMEM; 1969 1970 idtcm->client = client; 1971 idtcm->page_offset = 0xff; 1972 idtcm->calculate_overhead_flag = 0; 1973 1974 set_default_masks(idtcm); 1975 1976 mutex_init(&idtcm->reg_lock); 1977 mutex_lock(&idtcm->reg_lock); 1978 1979 idtcm_set_version_info(idtcm); 1980 1981 err = idtcm_load_firmware(idtcm, &client->dev); 1982 if (err) 1983 dev_warn(&idtcm->client->dev, "loading firmware failed with %d", err); 1984 1985 wait_for_chip_ready(idtcm); 1986 1987 if (idtcm->tod_mask) { 1988 for (i = 0; i < MAX_TOD; i++) { 1989 if (idtcm->tod_mask & (1 << i)) { 1990 err = idtcm_enable_channel(idtcm, i); 1991 if (err) { 1992 dev_err(&idtcm->client->dev, 1993 "idtcm_enable_channel %d failed!", i); 1994 break; 1995 } 1996 } 1997 } 1998 } else { 1999 dev_err(&idtcm->client->dev, 2000 "no PLLs flagged as PHCs, nothing to do"); 2001 err = -ENODEV; 2002 } 2003 2004 mutex_unlock(&idtcm->reg_lock); 2005 2006 if (err) { 2007 ptp_clock_unregister_all(idtcm); 2008 return err; 2009 } 2010 2011 i2c_set_clientdata(client, idtcm); 2012 2013 return 0; 2014 } 2015 2016 static int idtcm_remove(struct i2c_client *client) 2017 { 2018 struct idtcm *idtcm = i2c_get_clientdata(client); 2019 2020 ptp_clock_unregister_all(idtcm); 2021 2022 mutex_destroy(&idtcm->reg_lock); 2023 2024 return 0; 2025 } 2026 2027 #ifdef CONFIG_OF 2028 static const struct of_device_id idtcm_dt_id[] = { 2029 { .compatible = "idt,8a34000" }, 2030 { .compatible = "idt,8a34001" }, 2031 { .compatible = "idt,8a34002" }, 2032 { .compatible = "idt,8a34003" }, 2033 { .compatible = "idt,8a34004" }, 2034 { .compatible = "idt,8a34005" }, 2035 { .compatible = "idt,8a34006" }, 2036 { .compatible = "idt,8a34007" }, 2037 { .compatible = "idt,8a34008" }, 2038 { .compatible = "idt,8a34009" }, 2039 { .compatible = "idt,8a34010" }, 2040 { .compatible = "idt,8a34011" }, 2041 { .compatible = "idt,8a34012" }, 2042 { .compatible = "idt,8a34013" }, 2043 { .compatible = "idt,8a34014" }, 2044 { .compatible = "idt,8a34015" }, 2045 { .compatible = "idt,8a34016" }, 2046 { .compatible = "idt,8a34017" }, 2047 { .compatible = "idt,8a34018" }, 2048 { .compatible = "idt,8a34019" }, 2049 { .compatible = "idt,8a34040" }, 2050 { .compatible = "idt,8a34041" }, 2051 { .compatible = "idt,8a34042" }, 2052 { .compatible = "idt,8a34043" }, 2053 { .compatible = "idt,8a34044" }, 2054 { .compatible = "idt,8a34045" }, 2055 { .compatible = "idt,8a34046" }, 2056 { .compatible = "idt,8a34047" }, 2057 { .compatible = "idt,8a34048" }, 2058 { .compatible = "idt,8a34049" }, 2059 {}, 2060 }; 2061 MODULE_DEVICE_TABLE(of, idtcm_dt_id); 2062 #endif 2063 2064 static const struct i2c_device_id idtcm_i2c_id[] = { 2065 { "8a34000" }, 2066 { "8a34001" }, 2067 { "8a34002" }, 2068 { "8a34003" }, 2069 { "8a34004" }, 2070 { "8a34005" }, 2071 { "8a34006" }, 2072 { "8a34007" }, 2073 { "8a34008" }, 2074 { "8a34009" }, 2075 { "8a34010" }, 2076 { "8a34011" }, 2077 { "8a34012" }, 2078 { "8a34013" }, 2079 { "8a34014" }, 2080 { "8a34015" }, 2081 { "8a34016" }, 2082 { "8a34017" }, 2083 { "8a34018" }, 2084 { "8a34019" }, 2085 { "8a34040" }, 2086 { "8a34041" }, 2087 { "8a34042" }, 2088 { "8a34043" }, 2089 { "8a34044" }, 2090 { "8a34045" }, 2091 { "8a34046" }, 2092 { "8a34047" }, 2093 { "8a34048" }, 2094 { "8a34049" }, 2095 {}, 2096 }; 2097 MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id); 2098 2099 static struct i2c_driver idtcm_driver = { 2100 .driver = { 2101 .of_match_table = of_match_ptr(idtcm_dt_id), 2102 .name = "idtcm", 2103 }, 2104 .probe = idtcm_probe, 2105 .remove = idtcm_remove, 2106 .id_table = idtcm_i2c_id, 2107 }; 2108 2109 module_i2c_driver(idtcm_driver); 2110