1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and 4 * synchronization devices. 5 * 6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. 7 */ 8 #include <linux/firmware.h> 9 #include <linux/i2c.h> 10 #include <linux/module.h> 11 #include <linux/ptp_clock_kernel.h> 12 #include <linux/delay.h> 13 #include <linux/jiffies.h> 14 #include <linux/kernel.h> 15 #include <linux/timekeeping.h> 16 17 #include "ptp_private.h" 18 #include "ptp_clockmatrix.h" 19 20 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family"); 21 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); 22 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>"); 23 MODULE_VERSION("1.0"); 24 MODULE_LICENSE("GPL"); 25 26 #define SETTIME_CORRECTION (0) 27 28 static long set_write_phase_ready(struct ptp_clock_info *ptp) 29 { 30 struct idtcm_channel *channel = 31 container_of(ptp, struct idtcm_channel, caps); 32 33 channel->write_phase_ready = 1; 34 35 return 0; 36 } 37 38 static int char_array_to_timespec(u8 *buf, 39 u8 count, 40 struct timespec64 *ts) 41 { 42 u8 i; 43 u64 nsec; 44 time64_t sec; 45 46 if (count < TOD_BYTE_COUNT) 47 return 1; 48 49 /* Sub-nanoseconds are in buf[0]. */ 50 nsec = buf[4]; 51 for (i = 0; i < 3; i++) { 52 nsec <<= 8; 53 nsec |= buf[3 - i]; 54 } 55 56 sec = buf[10]; 57 for (i = 0; i < 5; i++) { 58 sec <<= 8; 59 sec |= buf[9 - i]; 60 } 61 62 ts->tv_sec = sec; 63 ts->tv_nsec = nsec; 64 65 return 0; 66 } 67 68 static int timespec_to_char_array(struct timespec64 const *ts, 69 u8 *buf, 70 u8 count) 71 { 72 u8 i; 73 s32 nsec; 74 time64_t sec; 75 76 if (count < TOD_BYTE_COUNT) 77 return 1; 78 79 nsec = ts->tv_nsec; 80 sec = ts->tv_sec; 81 82 /* Sub-nanoseconds are in buf[0]. */ 83 buf[0] = 0; 84 for (i = 1; i < 5; i++) { 85 buf[i] = nsec & 0xff; 86 nsec >>= 8; 87 } 88 89 for (i = 5; i < TOD_BYTE_COUNT; i++) { 90 91 buf[i] = sec & 0xff; 92 sec >>= 8; 93 } 94 95 return 0; 96 } 97 98 static int idtcm_xfer(struct idtcm *idtcm, 99 u8 regaddr, 100 u8 *buf, 101 u16 count, 102 bool write) 103 { 104 struct i2c_client *client = idtcm->client; 105 struct i2c_msg msg[2]; 106 int cnt; 107 108 msg[0].addr = client->addr; 109 msg[0].flags = 0; 110 msg[0].len = 1; 111 msg[0].buf = ®addr; 112 113 msg[1].addr = client->addr; 114 msg[1].flags = write ? 0 : I2C_M_RD; 115 msg[1].len = count; 116 msg[1].buf = buf; 117 118 cnt = i2c_transfer(client->adapter, msg, 2); 119 120 if (cnt < 0) { 121 dev_err(&client->dev, "i2c_transfer returned %d\n", cnt); 122 return cnt; 123 } else if (cnt != 2) { 124 dev_err(&client->dev, 125 "i2c_transfer sent only %d of %d messages\n", cnt, 2); 126 return -EIO; 127 } 128 129 return 0; 130 } 131 132 static int idtcm_page_offset(struct idtcm *idtcm, u8 val) 133 { 134 u8 buf[4]; 135 int err; 136 137 if (idtcm->page_offset == val) 138 return 0; 139 140 buf[0] = 0x0; 141 buf[1] = val; 142 buf[2] = 0x10; 143 buf[3] = 0x20; 144 145 err = idtcm_xfer(idtcm, PAGE_ADDR, buf, sizeof(buf), 1); 146 147 if (err) 148 dev_err(&idtcm->client->dev, "failed to set page offset\n"); 149 else 150 idtcm->page_offset = val; 151 152 return err; 153 } 154 155 static int _idtcm_rdwr(struct idtcm *idtcm, 156 u16 regaddr, 157 u8 *buf, 158 u16 count, 159 bool write) 160 { 161 u8 hi; 162 u8 lo; 163 int err; 164 165 hi = (regaddr >> 8) & 0xff; 166 lo = regaddr & 0xff; 167 168 err = idtcm_page_offset(idtcm, hi); 169 170 if (err) 171 goto out; 172 173 err = idtcm_xfer(idtcm, lo, buf, count, write); 174 out: 175 return err; 176 } 177 178 static int idtcm_read(struct idtcm *idtcm, 179 u16 module, 180 u16 regaddr, 181 u8 *buf, 182 u16 count) 183 { 184 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false); 185 } 186 187 static int idtcm_write(struct idtcm *idtcm, 188 u16 module, 189 u16 regaddr, 190 u8 *buf, 191 u16 count) 192 { 193 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true); 194 } 195 196 static int _idtcm_gettime(struct idtcm_channel *channel, 197 struct timespec64 *ts) 198 { 199 struct idtcm *idtcm = channel->idtcm; 200 u8 buf[TOD_BYTE_COUNT]; 201 u8 trigger; 202 int err; 203 204 err = idtcm_read(idtcm, channel->tod_read_primary, 205 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger)); 206 if (err) 207 return err; 208 209 trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT); 210 trigger |= (1 << TOD_READ_TRIGGER_SHIFT); 211 trigger |= TOD_READ_TRIGGER_MODE; 212 213 err = idtcm_write(idtcm, channel->tod_read_primary, 214 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger)); 215 216 if (err) 217 return err; 218 219 if (idtcm->calculate_overhead_flag) 220 idtcm->start_time = ktime_get_raw(); 221 222 err = idtcm_read(idtcm, channel->tod_read_primary, 223 TOD_READ_PRIMARY, buf, sizeof(buf)); 224 225 if (err) 226 return err; 227 228 err = char_array_to_timespec(buf, sizeof(buf), ts); 229 230 return err; 231 } 232 233 static int _sync_pll_output(struct idtcm *idtcm, 234 u8 pll, 235 u8 sync_src, 236 u8 qn, 237 u8 qn_plus_1) 238 { 239 int err; 240 u8 val; 241 u16 sync_ctrl0; 242 u16 sync_ctrl1; 243 244 if ((qn == 0) && (qn_plus_1 == 0)) 245 return 0; 246 247 switch (pll) { 248 case 0: 249 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0; 250 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1; 251 break; 252 case 1: 253 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0; 254 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1; 255 break; 256 case 2: 257 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0; 258 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1; 259 break; 260 case 3: 261 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0; 262 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1; 263 break; 264 case 4: 265 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0; 266 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1; 267 break; 268 case 5: 269 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0; 270 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1; 271 break; 272 case 6: 273 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0; 274 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1; 275 break; 276 case 7: 277 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0; 278 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1; 279 break; 280 default: 281 return -EINVAL; 282 } 283 284 val = SYNCTRL1_MASTER_SYNC_RST; 285 286 /* Place master sync in reset */ 287 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 288 if (err) 289 return err; 290 291 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src)); 292 if (err) 293 return err; 294 295 /* Set sync trigger mask */ 296 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG; 297 298 if (qn) 299 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG; 300 301 if (qn_plus_1) 302 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG; 303 304 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 305 if (err) 306 return err; 307 308 /* Place master sync out of reset */ 309 val &= ~(SYNCTRL1_MASTER_SYNC_RST); 310 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); 311 312 return err; 313 } 314 315 static int idtcm_sync_pps_output(struct idtcm_channel *channel) 316 { 317 struct idtcm *idtcm = channel->idtcm; 318 319 u8 pll; 320 u8 sync_src; 321 u8 qn; 322 u8 qn_plus_1; 323 int err = 0; 324 325 u16 output_mask = channel->output_mask; 326 327 switch (channel->dpll_n) { 328 case DPLL_0: 329 sync_src = SYNC_SOURCE_DPLL0_TOD_PPS; 330 break; 331 case DPLL_1: 332 sync_src = SYNC_SOURCE_DPLL1_TOD_PPS; 333 break; 334 case DPLL_2: 335 sync_src = SYNC_SOURCE_DPLL2_TOD_PPS; 336 break; 337 case DPLL_3: 338 sync_src = SYNC_SOURCE_DPLL3_TOD_PPS; 339 break; 340 default: 341 return -EINVAL; 342 } 343 344 for (pll = 0; pll < 8; pll++) { 345 346 qn = output_mask & 0x1; 347 output_mask = output_mask >> 1; 348 349 if (pll < 4) { 350 /* First 4 pll has 2 outputs */ 351 qn_plus_1 = output_mask & 0x1; 352 output_mask = output_mask >> 1; 353 } else { 354 qn_plus_1 = 0; 355 } 356 357 if ((qn != 0) || (qn_plus_1 != 0)) 358 err = _sync_pll_output(idtcm, pll, sync_src, qn, 359 qn_plus_1); 360 361 if (err) 362 return err; 363 } 364 365 return err; 366 } 367 368 static int _idtcm_set_dpll_tod(struct idtcm_channel *channel, 369 struct timespec64 const *ts, 370 enum hw_tod_write_trig_sel wr_trig) 371 { 372 struct idtcm *idtcm = channel->idtcm; 373 374 u8 buf[TOD_BYTE_COUNT]; 375 u8 cmd; 376 int err; 377 struct timespec64 local_ts = *ts; 378 s64 total_overhead_ns; 379 380 /* Configure HW TOD write trigger. */ 381 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 382 &cmd, sizeof(cmd)); 383 384 if (err) 385 return err; 386 387 cmd &= ~(0x0f); 388 cmd |= wr_trig | 0x08; 389 390 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 391 &cmd, sizeof(cmd)); 392 393 if (err) 394 return err; 395 396 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) { 397 398 err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); 399 400 if (err) 401 return err; 402 403 err = idtcm_write(idtcm, channel->hw_dpll_n, 404 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 405 406 if (err) 407 return err; 408 } 409 410 /* ARM HW TOD write trigger. */ 411 cmd &= ~(0x08); 412 413 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, 414 &cmd, sizeof(cmd)); 415 416 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) { 417 418 if (idtcm->calculate_overhead_flag) { 419 /* Assumption: I2C @ 400KHz */ 420 total_overhead_ns = ktime_to_ns(ktime_get_raw() 421 - idtcm->start_time) 422 + idtcm->tod_write_overhead_ns 423 + SETTIME_CORRECTION; 424 425 timespec64_add_ns(&local_ts, total_overhead_ns); 426 427 idtcm->calculate_overhead_flag = 0; 428 } 429 430 err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); 431 432 if (err) 433 return err; 434 435 err = idtcm_write(idtcm, channel->hw_dpll_n, 436 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 437 } 438 439 return err; 440 } 441 442 static int _idtcm_settime(struct idtcm_channel *channel, 443 struct timespec64 const *ts, 444 enum hw_tod_write_trig_sel wr_trig) 445 { 446 struct idtcm *idtcm = channel->idtcm; 447 s32 retval; 448 int err; 449 int i; 450 u8 trig_sel; 451 452 err = _idtcm_set_dpll_tod(channel, ts, wr_trig); 453 454 if (err) 455 return err; 456 457 /* Wait for the operation to complete. */ 458 for (i = 0; i < 10000; i++) { 459 err = idtcm_read(idtcm, channel->hw_dpll_n, 460 HW_DPLL_TOD_CTRL_1, &trig_sel, 461 sizeof(trig_sel)); 462 463 if (err) 464 return err; 465 466 if (trig_sel == 0x4a) 467 break; 468 469 err = 1; 470 } 471 472 if (err) 473 return err; 474 475 retval = idtcm_sync_pps_output(channel); 476 477 return retval; 478 } 479 480 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel, 481 s32 offset_ns) 482 { 483 int err; 484 int i; 485 struct idtcm *idtcm = channel->idtcm; 486 487 u8 buf[4]; 488 489 for (i = 0; i < 4; i++) { 490 buf[i] = 0xff & (offset_ns); 491 offset_ns >>= 8; 492 } 493 494 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET, 495 buf, sizeof(buf)); 496 497 return err; 498 } 499 500 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel, 501 u32 max_ffo_ppb) 502 { 503 int err; 504 u8 i; 505 struct idtcm *idtcm = channel->idtcm; 506 507 u8 buf[3]; 508 509 if (max_ffo_ppb & 0xff000000) 510 max_ffo_ppb = 0; 511 512 for (i = 0; i < 3; i++) { 513 buf[i] = 0xff & (max_ffo_ppb); 514 max_ffo_ppb >>= 8; 515 } 516 517 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, 518 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf)); 519 520 return err; 521 } 522 523 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel) 524 { 525 int err; 526 struct idtcm *idtcm = channel->idtcm; 527 528 u8 buf; 529 530 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL, 531 &buf, sizeof(buf)); 532 533 if (err) 534 return err; 535 536 if (buf == 0) { 537 buf = 0x01; 538 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, 539 PULL_IN_CTRL, &buf, sizeof(buf)); 540 } else { 541 err = -EBUSY; 542 } 543 544 return err; 545 } 546 547 static int idtcm_do_phase_pull_in(struct idtcm_channel *channel, 548 s32 offset_ns, 549 u32 max_ffo_ppb) 550 { 551 int err; 552 553 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns); 554 555 if (err) 556 return err; 557 558 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb); 559 560 if (err) 561 return err; 562 563 err = idtcm_start_phase_pull_in(channel); 564 565 return err; 566 } 567 568 static int _idtcm_adjtime(struct idtcm_channel *channel, s64 delta) 569 { 570 int err; 571 struct idtcm *idtcm = channel->idtcm; 572 struct timespec64 ts; 573 s64 now; 574 575 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) { 576 err = idtcm_do_phase_pull_in(channel, delta, 0); 577 } else { 578 idtcm->calculate_overhead_flag = 1; 579 580 err = _idtcm_gettime(channel, &ts); 581 582 if (err) 583 return err; 584 585 now = timespec64_to_ns(&ts); 586 now += delta; 587 588 ts = ns_to_timespec64(now); 589 590 err = _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB); 591 } 592 593 return err; 594 } 595 596 static int idtcm_state_machine_reset(struct idtcm *idtcm) 597 { 598 int err; 599 u8 byte = SM_RESET_CMD; 600 601 err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte)); 602 603 if (!err) 604 msleep_interruptible(POST_SM_RESET_DELAY_MS); 605 606 return err; 607 } 608 609 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id) 610 { 611 return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8)); 612 } 613 614 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id) 615 { 616 int err; 617 u8 buf[2] = {0}; 618 619 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf)); 620 621 *product_id = (buf[1] << 8) | buf[0]; 622 623 return err; 624 } 625 626 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major) 627 { 628 int err; 629 u8 buf = 0; 630 631 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf)); 632 633 *major = buf >> 1; 634 635 return err; 636 } 637 638 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor) 639 { 640 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8)); 641 } 642 643 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix) 644 { 645 return idtcm_read(idtcm, 646 GENERAL_STATUS, 647 HOTFIX_REL, 648 hotfix, 649 sizeof(u8)); 650 } 651 652 static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm, 653 u8 *config_select) 654 { 655 return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT, 656 config_select, sizeof(u8)); 657 } 658 659 static int process_pll_mask(struct idtcm *idtcm, u32 addr, u8 val, u8 *mask) 660 { 661 int err = 0; 662 663 if (addr == PLL_MASK_ADDR) { 664 if ((val & 0xf0) || !(val & 0xf)) { 665 dev_err(&idtcm->client->dev, 666 "Invalid PLL mask 0x%hhx\n", val); 667 err = -EINVAL; 668 } 669 *mask = val; 670 } 671 672 return err; 673 } 674 675 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val) 676 { 677 int err = 0; 678 679 switch (addr) { 680 case OUTPUT_MASK_PLL0_ADDR: 681 SET_U16_LSB(idtcm->channel[0].output_mask, val); 682 break; 683 case OUTPUT_MASK_PLL0_ADDR + 1: 684 SET_U16_MSB(idtcm->channel[0].output_mask, val); 685 break; 686 case OUTPUT_MASK_PLL1_ADDR: 687 SET_U16_LSB(idtcm->channel[1].output_mask, val); 688 break; 689 case OUTPUT_MASK_PLL1_ADDR + 1: 690 SET_U16_MSB(idtcm->channel[1].output_mask, val); 691 break; 692 case OUTPUT_MASK_PLL2_ADDR: 693 SET_U16_LSB(idtcm->channel[2].output_mask, val); 694 break; 695 case OUTPUT_MASK_PLL2_ADDR + 1: 696 SET_U16_MSB(idtcm->channel[2].output_mask, val); 697 break; 698 case OUTPUT_MASK_PLL3_ADDR: 699 SET_U16_LSB(idtcm->channel[3].output_mask, val); 700 break; 701 case OUTPUT_MASK_PLL3_ADDR + 1: 702 SET_U16_MSB(idtcm->channel[3].output_mask, val); 703 break; 704 default: 705 err = -EINVAL; 706 break; 707 } 708 709 return err; 710 } 711 712 static int check_and_set_masks(struct idtcm *idtcm, 713 u16 regaddr, 714 u8 val) 715 { 716 int err = 0; 717 718 if (set_pll_output_mask(idtcm, regaddr, val)) { 719 /* Not an output mask, check for pll mask */ 720 err = process_pll_mask(idtcm, regaddr, val, &idtcm->pll_mask); 721 } 722 723 return err; 724 } 725 726 static void display_pll_and_output_masks(struct idtcm *idtcm) 727 { 728 u8 i; 729 u8 mask; 730 731 dev_dbg(&idtcm->client->dev, "pllmask = 0x%02x\n", idtcm->pll_mask); 732 733 for (i = 0; i < MAX_PHC_PLL; i++) { 734 mask = 1 << i; 735 736 if (mask & idtcm->pll_mask) 737 dev_dbg(&idtcm->client->dev, 738 "PLL%d output_mask = 0x%04x\n", 739 i, idtcm->channel[i].output_mask); 740 } 741 } 742 743 static int idtcm_load_firmware(struct idtcm *idtcm, 744 struct device *dev) 745 { 746 const struct firmware *fw; 747 struct idtcm_fwrc *rec; 748 u32 regaddr; 749 int err; 750 s32 len; 751 u8 val; 752 u8 loaddr; 753 754 dev_dbg(&idtcm->client->dev, "requesting firmware '%s'\n", FW_FILENAME); 755 756 err = request_firmware(&fw, FW_FILENAME, dev); 757 758 if (err) 759 return err; 760 761 dev_dbg(&idtcm->client->dev, "firmware size %zu bytes\n", fw->size); 762 763 rec = (struct idtcm_fwrc *) fw->data; 764 765 if (fw->size > 0) 766 idtcm_state_machine_reset(idtcm); 767 768 for (len = fw->size; len > 0; len -= sizeof(*rec)) { 769 770 if (rec->reserved) { 771 dev_err(&idtcm->client->dev, 772 "bad firmware, reserved field non-zero\n"); 773 err = -EINVAL; 774 } else { 775 regaddr = rec->hiaddr << 8; 776 regaddr |= rec->loaddr; 777 778 val = rec->value; 779 loaddr = rec->loaddr; 780 781 rec++; 782 783 err = check_and_set_masks(idtcm, regaddr, val); 784 } 785 786 if (err == 0) { 787 /* Top (status registers) and bottom are read-only */ 788 if ((regaddr < GPIO_USER_CONTROL) 789 || (regaddr >= SCRATCH)) 790 continue; 791 792 /* Page size 128, last 4 bytes of page skipped */ 793 if (((loaddr > 0x7b) && (loaddr <= 0x7f)) 794 || loaddr > 0xfb) 795 continue; 796 797 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val)); 798 } 799 800 if (err) 801 goto out; 802 } 803 804 display_pll_and_output_masks(idtcm); 805 806 out: 807 release_firmware(fw); 808 return err; 809 } 810 811 static int idtcm_pps_enable(struct idtcm_channel *channel, bool enable) 812 { 813 struct idtcm *idtcm = channel->idtcm; 814 u32 module; 815 u8 val; 816 int err; 817 818 /* 819 * This assumes that the 1-PPS is on the second of the two 820 * output. But is this always true? 821 */ 822 switch (channel->dpll_n) { 823 case DPLL_0: 824 module = OUTPUT_1; 825 break; 826 case DPLL_1: 827 module = OUTPUT_3; 828 break; 829 case DPLL_2: 830 module = OUTPUT_5; 831 break; 832 case DPLL_3: 833 module = OUTPUT_7; 834 break; 835 default: 836 return -EINVAL; 837 } 838 839 err = idtcm_read(idtcm, module, OUT_CTRL_1, &val, sizeof(val)); 840 841 if (err) 842 return err; 843 844 if (enable) 845 val |= SQUELCH_DISABLE; 846 else 847 val &= ~SQUELCH_DISABLE; 848 849 err = idtcm_write(idtcm, module, OUT_CTRL_1, &val, sizeof(val)); 850 851 if (err) 852 return err; 853 854 return 0; 855 } 856 857 static int idtcm_set_pll_mode(struct idtcm_channel *channel, 858 enum pll_mode pll_mode) 859 { 860 struct idtcm *idtcm = channel->idtcm; 861 int err; 862 u8 dpll_mode; 863 864 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE, 865 &dpll_mode, sizeof(dpll_mode)); 866 if (err) 867 return err; 868 869 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT); 870 871 dpll_mode |= (pll_mode << PLL_MODE_SHIFT); 872 873 channel->pll_mode = pll_mode; 874 875 err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE, 876 &dpll_mode, sizeof(dpll_mode)); 877 if (err) 878 return err; 879 880 return 0; 881 } 882 883 /* PTP Hardware Clock interface */ 884 885 /** 886 * @brief Maximum absolute value for write phase offset in picoseconds 887 * 888 * Destination signed register is 32-bit register in resolution of 50ps 889 * 890 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350 891 */ 892 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns) 893 { 894 struct idtcm *idtcm = channel->idtcm; 895 896 int err; 897 u8 i; 898 u8 buf[4] = {0}; 899 s32 phase_50ps; 900 s64 offset_ps; 901 902 if (channel->pll_mode != PLL_MODE_WRITE_PHASE) { 903 904 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE); 905 906 if (err) 907 return err; 908 909 channel->write_phase_ready = 0; 910 911 ptp_schedule_worker(channel->ptp_clock, 912 msecs_to_jiffies(WR_PHASE_SETUP_MS)); 913 } 914 915 if (!channel->write_phase_ready) 916 delta_ns = 0; 917 918 offset_ps = (s64)delta_ns * 1000; 919 920 /* 921 * Check for 32-bit signed max * 50: 922 * 923 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350 924 */ 925 if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS) 926 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS; 927 else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS) 928 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS; 929 930 phase_50ps = DIV_ROUND_CLOSEST(div64_s64(offset_ps, 50), 1); 931 932 for (i = 0; i < 4; i++) { 933 buf[i] = phase_50ps & 0xff; 934 phase_50ps >>= 8; 935 } 936 937 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE, 938 buf, sizeof(buf)); 939 940 return err; 941 } 942 943 static int idtcm_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 944 { 945 struct idtcm_channel *channel = 946 container_of(ptp, struct idtcm_channel, caps); 947 struct idtcm *idtcm = channel->idtcm; 948 u8 i; 949 bool neg_adj = 0; 950 int err; 951 u8 buf[6] = {0}; 952 s64 fcw; 953 954 if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) { 955 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY); 956 if (err) 957 return err; 958 } 959 960 /* 961 * Frequency Control Word unit is: 1.11 * 10^-10 ppm 962 * 963 * adjfreq: 964 * ppb * 10^9 965 * FCW = ---------- 966 * 111 967 * 968 * adjfine: 969 * ppm_16 * 5^12 970 * FCW = ------------- 971 * 111 * 2^4 972 */ 973 if (ppb < 0) { 974 neg_adj = 1; 975 ppb = -ppb; 976 } 977 978 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */ 979 fcw = ppb * 1000000000000ULL; 980 981 fcw = div_u64(fcw, 111022); 982 983 if (neg_adj) 984 fcw = -fcw; 985 986 for (i = 0; i < 6; i++) { 987 buf[i] = fcw & 0xff; 988 fcw >>= 8; 989 } 990 991 mutex_lock(&idtcm->reg_lock); 992 993 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ, 994 buf, sizeof(buf)); 995 996 mutex_unlock(&idtcm->reg_lock); 997 return err; 998 } 999 1000 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 1001 { 1002 struct idtcm_channel *channel = 1003 container_of(ptp, struct idtcm_channel, caps); 1004 struct idtcm *idtcm = channel->idtcm; 1005 int err; 1006 1007 mutex_lock(&idtcm->reg_lock); 1008 1009 err = _idtcm_gettime(channel, ts); 1010 1011 mutex_unlock(&idtcm->reg_lock); 1012 1013 return err; 1014 } 1015 1016 static int idtcm_settime(struct ptp_clock_info *ptp, 1017 const struct timespec64 *ts) 1018 { 1019 struct idtcm_channel *channel = 1020 container_of(ptp, struct idtcm_channel, caps); 1021 struct idtcm *idtcm = channel->idtcm; 1022 int err; 1023 1024 mutex_lock(&idtcm->reg_lock); 1025 1026 err = _idtcm_settime(channel, ts, HW_TOD_WR_TRIG_SEL_MSB); 1027 1028 mutex_unlock(&idtcm->reg_lock); 1029 1030 return err; 1031 } 1032 1033 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta) 1034 { 1035 struct idtcm_channel *channel = 1036 container_of(ptp, struct idtcm_channel, caps); 1037 struct idtcm *idtcm = channel->idtcm; 1038 int err; 1039 1040 mutex_lock(&idtcm->reg_lock); 1041 1042 err = _idtcm_adjtime(channel, delta); 1043 1044 mutex_unlock(&idtcm->reg_lock); 1045 1046 return err; 1047 } 1048 1049 static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta) 1050 { 1051 struct idtcm_channel *channel = 1052 container_of(ptp, struct idtcm_channel, caps); 1053 1054 struct idtcm *idtcm = channel->idtcm; 1055 1056 int err; 1057 1058 mutex_lock(&idtcm->reg_lock); 1059 1060 err = _idtcm_adjphase(channel, delta); 1061 1062 mutex_unlock(&idtcm->reg_lock); 1063 1064 return err; 1065 } 1066 1067 static int idtcm_enable(struct ptp_clock_info *ptp, 1068 struct ptp_clock_request *rq, int on) 1069 { 1070 struct idtcm_channel *channel = 1071 container_of(ptp, struct idtcm_channel, caps); 1072 1073 switch (rq->type) { 1074 case PTP_CLK_REQ_PEROUT: 1075 if (!on) 1076 return idtcm_pps_enable(channel, false); 1077 1078 /* Only accept a 1-PPS aligned to the second. */ 1079 if (rq->perout.start.nsec || rq->perout.period.sec != 1 || 1080 rq->perout.period.nsec) 1081 return -ERANGE; 1082 1083 return idtcm_pps_enable(channel, true); 1084 default: 1085 break; 1086 } 1087 1088 return -EOPNOTSUPP; 1089 } 1090 1091 static int idtcm_enable_tod(struct idtcm_channel *channel) 1092 { 1093 struct idtcm *idtcm = channel->idtcm; 1094 struct timespec64 ts = {0, 0}; 1095 u8 cfg; 1096 int err; 1097 1098 err = idtcm_pps_enable(channel, false); 1099 if (err) 1100 return err; 1101 1102 /* 1103 * Start the TOD clock ticking. 1104 */ 1105 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg)); 1106 if (err) 1107 return err; 1108 1109 cfg |= TOD_ENABLE; 1110 1111 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg)); 1112 if (err) 1113 return err; 1114 1115 return _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB); 1116 } 1117 1118 static void idtcm_display_version_info(struct idtcm *idtcm) 1119 { 1120 u8 major; 1121 u8 minor; 1122 u8 hotfix; 1123 u16 product_id; 1124 u8 hw_rev_id; 1125 u8 config_select; 1126 char *fmt = "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d\n"; 1127 1128 idtcm_read_major_release(idtcm, &major); 1129 idtcm_read_minor_release(idtcm, &minor); 1130 idtcm_read_hotfix_release(idtcm, &hotfix); 1131 1132 idtcm_read_product_id(idtcm, &product_id); 1133 idtcm_read_hw_rev_id(idtcm, &hw_rev_id); 1134 1135 idtcm_read_otp_scsr_config_select(idtcm, &config_select); 1136 1137 dev_info(&idtcm->client->dev, fmt, major, minor, hotfix, 1138 product_id, hw_rev_id, config_select); 1139 } 1140 1141 static const struct ptp_clock_info idtcm_caps = { 1142 .owner = THIS_MODULE, 1143 .max_adj = 244000, 1144 .n_per_out = 1, 1145 .adjphase = &idtcm_adjphase, 1146 .adjfreq = &idtcm_adjfreq, 1147 .adjtime = &idtcm_adjtime, 1148 .gettime64 = &idtcm_gettime, 1149 .settime64 = &idtcm_settime, 1150 .enable = &idtcm_enable, 1151 .do_aux_work = &set_write_phase_ready, 1152 }; 1153 1154 1155 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) 1156 { 1157 struct idtcm_channel *channel; 1158 int err; 1159 1160 if (!(index < MAX_PHC_PLL)) 1161 return -EINVAL; 1162 1163 channel = &idtcm->channel[index]; 1164 1165 switch (index) { 1166 case 0: 1167 channel->dpll_freq = DPLL_FREQ_0; 1168 channel->dpll_n = DPLL_0; 1169 channel->tod_read_primary = TOD_READ_PRIMARY_0; 1170 channel->tod_write = TOD_WRITE_0; 1171 channel->tod_n = TOD_0; 1172 channel->hw_dpll_n = HW_DPLL_0; 1173 channel->dpll_phase = DPLL_PHASE_0; 1174 channel->dpll_ctrl_n = DPLL_CTRL_0; 1175 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0; 1176 break; 1177 case 1: 1178 channel->dpll_freq = DPLL_FREQ_1; 1179 channel->dpll_n = DPLL_1; 1180 channel->tod_read_primary = TOD_READ_PRIMARY_1; 1181 channel->tod_write = TOD_WRITE_1; 1182 channel->tod_n = TOD_1; 1183 channel->hw_dpll_n = HW_DPLL_1; 1184 channel->dpll_phase = DPLL_PHASE_1; 1185 channel->dpll_ctrl_n = DPLL_CTRL_1; 1186 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1; 1187 break; 1188 case 2: 1189 channel->dpll_freq = DPLL_FREQ_2; 1190 channel->dpll_n = DPLL_2; 1191 channel->tod_read_primary = TOD_READ_PRIMARY_2; 1192 channel->tod_write = TOD_WRITE_2; 1193 channel->tod_n = TOD_2; 1194 channel->hw_dpll_n = HW_DPLL_2; 1195 channel->dpll_phase = DPLL_PHASE_2; 1196 channel->dpll_ctrl_n = DPLL_CTRL_2; 1197 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2; 1198 break; 1199 case 3: 1200 channel->dpll_freq = DPLL_FREQ_3; 1201 channel->dpll_n = DPLL_3; 1202 channel->tod_read_primary = TOD_READ_PRIMARY_3; 1203 channel->tod_write = TOD_WRITE_3; 1204 channel->tod_n = TOD_3; 1205 channel->hw_dpll_n = HW_DPLL_3; 1206 channel->dpll_phase = DPLL_PHASE_3; 1207 channel->dpll_ctrl_n = DPLL_CTRL_3; 1208 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3; 1209 break; 1210 default: 1211 return -EINVAL; 1212 } 1213 1214 channel->idtcm = idtcm; 1215 1216 channel->caps = idtcm_caps; 1217 snprintf(channel->caps.name, sizeof(channel->caps.name), 1218 "IDT CM PLL%u", index); 1219 1220 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY); 1221 if (err) 1222 return err; 1223 1224 err = idtcm_enable_tod(channel); 1225 if (err) 1226 return err; 1227 1228 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL); 1229 1230 if (IS_ERR(channel->ptp_clock)) { 1231 err = PTR_ERR(channel->ptp_clock); 1232 channel->ptp_clock = NULL; 1233 return err; 1234 } 1235 1236 if (!channel->ptp_clock) 1237 return -ENOTSUPP; 1238 1239 channel->write_phase_ready = 0; 1240 1241 dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d\n", 1242 index, channel->ptp_clock->index); 1243 1244 return 0; 1245 } 1246 1247 static void ptp_clock_unregister_all(struct idtcm *idtcm) 1248 { 1249 u8 i; 1250 struct idtcm_channel *channel; 1251 1252 for (i = 0; i < MAX_PHC_PLL; i++) { 1253 1254 channel = &idtcm->channel[i]; 1255 1256 if (channel->ptp_clock) 1257 ptp_clock_unregister(channel->ptp_clock); 1258 } 1259 } 1260 1261 static void set_default_masks(struct idtcm *idtcm) 1262 { 1263 idtcm->pll_mask = DEFAULT_PLL_MASK; 1264 1265 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0; 1266 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1; 1267 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2; 1268 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3; 1269 } 1270 1271 static int set_tod_write_overhead(struct idtcm *idtcm) 1272 { 1273 int err; 1274 u8 i; 1275 1276 s64 total_ns = 0; 1277 1278 ktime_t start; 1279 ktime_t stop; 1280 1281 char buf[TOD_BYTE_COUNT]; 1282 1283 struct idtcm_channel *channel = &idtcm->channel[2]; 1284 1285 /* Set page offset */ 1286 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0, 1287 buf, sizeof(buf)); 1288 1289 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) { 1290 1291 start = ktime_get_raw(); 1292 1293 err = idtcm_write(idtcm, channel->hw_dpll_n, 1294 HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); 1295 1296 if (err) 1297 return err; 1298 1299 stop = ktime_get_raw(); 1300 1301 total_ns += ktime_to_ns(stop - start); 1302 } 1303 1304 idtcm->tod_write_overhead_ns = div_s64(total_ns, 1305 TOD_WRITE_OVERHEAD_COUNT_MAX); 1306 1307 return err; 1308 } 1309 1310 static int idtcm_probe(struct i2c_client *client, 1311 const struct i2c_device_id *id) 1312 { 1313 struct idtcm *idtcm; 1314 int err; 1315 u8 i; 1316 1317 /* Unused for now */ 1318 (void)id; 1319 1320 idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL); 1321 1322 if (!idtcm) 1323 return -ENOMEM; 1324 1325 idtcm->client = client; 1326 idtcm->page_offset = 0xff; 1327 idtcm->calculate_overhead_flag = 0; 1328 1329 set_default_masks(idtcm); 1330 1331 mutex_init(&idtcm->reg_lock); 1332 mutex_lock(&idtcm->reg_lock); 1333 1334 idtcm_display_version_info(idtcm); 1335 1336 err = set_tod_write_overhead(idtcm); 1337 1338 if (err) { 1339 mutex_unlock(&idtcm->reg_lock); 1340 return err; 1341 } 1342 1343 err = idtcm_load_firmware(idtcm, &client->dev); 1344 1345 if (err) 1346 dev_warn(&idtcm->client->dev, 1347 "loading firmware failed with %d\n", err); 1348 1349 if (idtcm->pll_mask) { 1350 for (i = 0; i < MAX_PHC_PLL; i++) { 1351 if (idtcm->pll_mask & (1 << i)) { 1352 err = idtcm_enable_channel(idtcm, i); 1353 if (err) 1354 break; 1355 } 1356 } 1357 } else { 1358 dev_err(&idtcm->client->dev, 1359 "no PLLs flagged as PHCs, nothing to do\n"); 1360 err = -ENODEV; 1361 } 1362 1363 mutex_unlock(&idtcm->reg_lock); 1364 1365 if (err) { 1366 ptp_clock_unregister_all(idtcm); 1367 return err; 1368 } 1369 1370 i2c_set_clientdata(client, idtcm); 1371 1372 return 0; 1373 } 1374 1375 static int idtcm_remove(struct i2c_client *client) 1376 { 1377 struct idtcm *idtcm = i2c_get_clientdata(client); 1378 1379 ptp_clock_unregister_all(idtcm); 1380 1381 mutex_destroy(&idtcm->reg_lock); 1382 1383 return 0; 1384 } 1385 1386 #ifdef CONFIG_OF 1387 static const struct of_device_id idtcm_dt_id[] = { 1388 { .compatible = "idt,8a34000" }, 1389 { .compatible = "idt,8a34001" }, 1390 { .compatible = "idt,8a34002" }, 1391 { .compatible = "idt,8a34003" }, 1392 { .compatible = "idt,8a34004" }, 1393 { .compatible = "idt,8a34005" }, 1394 { .compatible = "idt,8a34006" }, 1395 { .compatible = "idt,8a34007" }, 1396 { .compatible = "idt,8a34008" }, 1397 { .compatible = "idt,8a34009" }, 1398 { .compatible = "idt,8a34010" }, 1399 { .compatible = "idt,8a34011" }, 1400 { .compatible = "idt,8a34012" }, 1401 { .compatible = "idt,8a34013" }, 1402 { .compatible = "idt,8a34014" }, 1403 { .compatible = "idt,8a34015" }, 1404 { .compatible = "idt,8a34016" }, 1405 { .compatible = "idt,8a34017" }, 1406 { .compatible = "idt,8a34018" }, 1407 { .compatible = "idt,8a34019" }, 1408 { .compatible = "idt,8a34040" }, 1409 { .compatible = "idt,8a34041" }, 1410 { .compatible = "idt,8a34042" }, 1411 { .compatible = "idt,8a34043" }, 1412 { .compatible = "idt,8a34044" }, 1413 { .compatible = "idt,8a34045" }, 1414 { .compatible = "idt,8a34046" }, 1415 { .compatible = "idt,8a34047" }, 1416 { .compatible = "idt,8a34048" }, 1417 { .compatible = "idt,8a34049" }, 1418 {}, 1419 }; 1420 MODULE_DEVICE_TABLE(of, idtcm_dt_id); 1421 #endif 1422 1423 static const struct i2c_device_id idtcm_i2c_id[] = { 1424 { "8a34000" }, 1425 { "8a34001" }, 1426 { "8a34002" }, 1427 { "8a34003" }, 1428 { "8a34004" }, 1429 { "8a34005" }, 1430 { "8a34006" }, 1431 { "8a34007" }, 1432 { "8a34008" }, 1433 { "8a34009" }, 1434 { "8a34010" }, 1435 { "8a34011" }, 1436 { "8a34012" }, 1437 { "8a34013" }, 1438 { "8a34014" }, 1439 { "8a34015" }, 1440 { "8a34016" }, 1441 { "8a34017" }, 1442 { "8a34018" }, 1443 { "8a34019" }, 1444 { "8a34040" }, 1445 { "8a34041" }, 1446 { "8a34042" }, 1447 { "8a34043" }, 1448 { "8a34044" }, 1449 { "8a34045" }, 1450 { "8a34046" }, 1451 { "8a34047" }, 1452 { "8a34048" }, 1453 { "8a34049" }, 1454 {}, 1455 }; 1456 MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id); 1457 1458 static struct i2c_driver idtcm_driver = { 1459 .driver = { 1460 .of_match_table = of_match_ptr(idtcm_dt_id), 1461 .name = "idtcm", 1462 }, 1463 .probe = idtcm_probe, 1464 .remove = idtcm_remove, 1465 .id_table = idtcm_i2c_id, 1466 }; 1467 1468 module_i2c_driver(idtcm_driver); 1469