1 /* 2 * Atmel AT91 SAM9 & SAMA5 SoCs reset code 3 * 4 * Copyright (C) 2007 Atmel Corporation. 5 * Copyright (C) BitBox Ltd 2010 6 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com> 7 * Copyright (C) 2014 Free Electrons 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of_address.h> 18 #include <linux/platform_device.h> 19 #include <linux/reboot.h> 20 #include <linux/reset-controller.h> 21 22 #include <soc/at91/at91sam9_ddrsdr.h> 23 #include <soc/at91/at91sam9_sdramc.h> 24 25 #include <dt-bindings/reset/sama7g5-reset.h> 26 27 #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */ 28 #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */ 29 #define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */ 30 #define AT91_RSTC_EXTRST BIT(3) /* External Reset */ 31 #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ 32 33 #define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */ 34 #define AT91_RSTC_URSTS BIT(0) /* User Reset Status */ 35 #define AT91_RSTC_RSTTYP GENMASK(10, 8) /* Reset Type */ 36 #define AT91_RSTC_NRSTL BIT(16) /* NRST Pin Level */ 37 #define AT91_RSTC_SRCMP BIT(17) /* Software Reset Command in Progress */ 38 39 #define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */ 40 #define AT91_RSTC_URSTEN BIT(0) /* User Reset Enable */ 41 #define AT91_RSTC_URSTASYNC BIT(2) /* User Reset Asynchronous Control */ 42 #define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */ 43 #define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */ 44 45 /** 46 * enum reset_type - reset types 47 * @RESET_TYPE_GENERAL: first power-up reset 48 * @RESET_TYPE_WAKEUP: return from backup mode 49 * @RESET_TYPE_WATCHDOG: watchdog fault 50 * @RESET_TYPE_SOFTWARE: processor reset required by software 51 * @RESET_TYPE_USER: NRST pin detected low 52 * @RESET_TYPE_CPU_FAIL: CPU clock failure detection 53 * @RESET_TYPE_XTAL_FAIL: 32KHz crystal failure dectection fault 54 * @RESET_TYPE_ULP2: ULP2 reset 55 */ 56 enum reset_type { 57 RESET_TYPE_GENERAL = 0, 58 RESET_TYPE_WAKEUP = 1, 59 RESET_TYPE_WATCHDOG = 2, 60 RESET_TYPE_SOFTWARE = 3, 61 RESET_TYPE_USER = 4, 62 RESET_TYPE_CPU_FAIL = 6, 63 RESET_TYPE_XTAL_FAIL = 7, 64 RESET_TYPE_ULP2 = 8, 65 }; 66 67 /** 68 * struct at91_reset - AT91 reset specific data structure 69 * @rstc_base: base address for system reset 70 * @ramc_base: array with base addresses of RAM controllers 71 * @dev_base: base address for devices reset 72 * @sclk: slow clock 73 * @data: platform specific reset data 74 * @rcdev: reset controller device 75 * @lock: lock for devices reset register access 76 * @nb: reset notifier block 77 * @args: SoC specific system reset arguments 78 * @ramc_lpr: SDRAM Controller Low Power Register 79 */ 80 struct at91_reset { 81 void __iomem *rstc_base; 82 void __iomem *ramc_base[2]; 83 void __iomem *dev_base; 84 struct clk *sclk; 85 const struct at91_reset_data *data; 86 struct reset_controller_dev rcdev; 87 spinlock_t lock; 88 struct notifier_block nb; 89 u32 args; 90 u32 ramc_lpr; 91 }; 92 93 #define to_at91_reset(r) container_of(r, struct at91_reset, rcdev) 94 95 /** 96 * struct at91_reset_data - AT91 reset data 97 * @reset_args: SoC specific system reset arguments 98 * @n_device_reset: number of device resets 99 * @device_reset_min_id: min id for device reset 100 * @device_reset_max_id: max id for device reset 101 */ 102 struct at91_reset_data { 103 u32 reset_args; 104 u32 n_device_reset; 105 u8 device_reset_min_id; 106 u8 device_reset_max_id; 107 }; 108 109 /* 110 * unless the SDRAM is cleanly shutdown before we hit the 111 * reset register it can be left driving the data bus and 112 * killing the chance of a subsequent boot from NAND 113 */ 114 static int at91_reset(struct notifier_block *this, unsigned long mode, 115 void *cmd) 116 { 117 struct at91_reset *reset = container_of(this, struct at91_reset, nb); 118 119 asm volatile( 120 /* Align to cache lines */ 121 ".balign 32\n\t" 122 123 /* Disable SDRAM0 accesses */ 124 " tst %0, #0\n\t" 125 " beq 1f\n\t" 126 " str %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t" 127 /* Power down SDRAM0 */ 128 " str %4, [%0, %6]\n\t" 129 /* Disable SDRAM1 accesses */ 130 "1: tst %1, #0\n\t" 131 " beq 2f\n\t" 132 " strne %3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t" 133 /* Power down SDRAM1 */ 134 " strne %4, [%1, %6]\n\t" 135 /* Reset CPU */ 136 "2: str %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t" 137 138 " b .\n\t" 139 : 140 : "r" (reset->ramc_base[0]), 141 "r" (reset->ramc_base[1]), 142 "r" (reset->rstc_base), 143 "r" (1), 144 "r" cpu_to_le32(AT91_DDRSDRC_LPCB_POWER_DOWN), 145 "r" (reset->data->reset_args), 146 "r" (reset->ramc_lpr) 147 : "r4"); 148 149 return NOTIFY_DONE; 150 } 151 152 static const char * __init at91_reset_reason(struct at91_reset *reset) 153 { 154 u32 reg = readl(reset->rstc_base + AT91_RSTC_SR); 155 const char *reason; 156 157 switch ((reg & AT91_RSTC_RSTTYP) >> 8) { 158 case RESET_TYPE_GENERAL: 159 reason = "general reset"; 160 break; 161 case RESET_TYPE_WAKEUP: 162 reason = "wakeup"; 163 break; 164 case RESET_TYPE_WATCHDOG: 165 reason = "watchdog reset"; 166 break; 167 case RESET_TYPE_SOFTWARE: 168 reason = "software reset"; 169 break; 170 case RESET_TYPE_USER: 171 reason = "user reset"; 172 break; 173 case RESET_TYPE_CPU_FAIL: 174 reason = "CPU clock failure detection"; 175 break; 176 case RESET_TYPE_XTAL_FAIL: 177 reason = "32.768 kHz crystal failure detection"; 178 break; 179 case RESET_TYPE_ULP2: 180 reason = "ULP2 reset"; 181 break; 182 default: 183 reason = "unknown reset"; 184 break; 185 } 186 187 return reason; 188 } 189 190 static const struct of_device_id at91_ramc_of_match[] = { 191 { 192 .compatible = "atmel,at91sam9260-sdramc", 193 .data = (void *)AT91_SDRAMC_LPR, 194 }, 195 { 196 .compatible = "atmel,at91sam9g45-ddramc", 197 .data = (void *)AT91_DDRSDRC_LPR, 198 }, 199 { /* sentinel */ } 200 }; 201 202 static const struct at91_reset_data sam9260 = { 203 .reset_args = AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST, 204 }; 205 206 static const struct at91_reset_data samx7 = { 207 .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, 208 }; 209 210 static const struct at91_reset_data sama7g5 = { 211 .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, 212 .n_device_reset = 3, 213 .device_reset_min_id = SAMA7G5_RESET_USB_PHY1, 214 .device_reset_max_id = SAMA7G5_RESET_USB_PHY3, 215 }; 216 217 static const struct of_device_id at91_reset_of_match[] = { 218 { 219 .compatible = "atmel,at91sam9260-rstc", 220 .data = &sam9260, 221 }, 222 { 223 .compatible = "atmel,at91sam9g45-rstc", 224 .data = &sam9260, 225 }, 226 { 227 .compatible = "atmel,sama5d3-rstc", 228 .data = &sam9260, 229 }, 230 { 231 .compatible = "atmel,samx7-rstc", 232 .data = &samx7, 233 }, 234 { 235 .compatible = "microchip,sam9x60-rstc", 236 .data = &samx7, 237 }, 238 { 239 .compatible = "microchip,sama7g5-rstc", 240 .data = &sama7g5, 241 }, 242 { /* sentinel */ } 243 }; 244 MODULE_DEVICE_TABLE(of, at91_reset_of_match); 245 246 static int at91_reset_update(struct reset_controller_dev *rcdev, 247 unsigned long id, bool assert) 248 { 249 struct at91_reset *reset = to_at91_reset(rcdev); 250 unsigned long flags; 251 u32 val; 252 253 spin_lock_irqsave(&reset->lock, flags); 254 val = readl_relaxed(reset->dev_base); 255 if (assert) 256 val |= BIT(id); 257 else 258 val &= ~BIT(id); 259 writel_relaxed(val, reset->dev_base); 260 spin_unlock_irqrestore(&reset->lock, flags); 261 262 return 0; 263 } 264 265 static int at91_reset_assert(struct reset_controller_dev *rcdev, 266 unsigned long id) 267 { 268 return at91_reset_update(rcdev, id, true); 269 } 270 271 static int at91_reset_deassert(struct reset_controller_dev *rcdev, 272 unsigned long id) 273 { 274 return at91_reset_update(rcdev, id, false); 275 } 276 277 static int at91_reset_dev_status(struct reset_controller_dev *rcdev, 278 unsigned long id) 279 { 280 struct at91_reset *reset = to_at91_reset(rcdev); 281 u32 val; 282 283 val = readl_relaxed(reset->dev_base); 284 285 return !!(val & BIT(id)); 286 } 287 288 static const struct reset_control_ops at91_reset_ops = { 289 .assert = at91_reset_assert, 290 .deassert = at91_reset_deassert, 291 .status = at91_reset_dev_status, 292 }; 293 294 static int at91_reset_of_xlate(struct reset_controller_dev *rcdev, 295 const struct of_phandle_args *reset_spec) 296 { 297 struct at91_reset *reset = to_at91_reset(rcdev); 298 299 if (!reset->data->n_device_reset || 300 (reset_spec->args[0] < reset->data->device_reset_min_id || 301 reset_spec->args[0] > reset->data->device_reset_max_id)) 302 return -EINVAL; 303 304 return reset_spec->args[0]; 305 } 306 307 static int at91_rcdev_init(struct at91_reset *reset, 308 struct platform_device *pdev) 309 { 310 if (!reset->data->n_device_reset) 311 return 0; 312 313 reset->dev_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 1, 314 NULL); 315 if (IS_ERR(reset->dev_base)) 316 return -ENODEV; 317 318 spin_lock_init(&reset->lock); 319 reset->rcdev.ops = &at91_reset_ops; 320 reset->rcdev.owner = THIS_MODULE; 321 reset->rcdev.of_node = pdev->dev.of_node; 322 reset->rcdev.nr_resets = reset->data->n_device_reset; 323 reset->rcdev.of_reset_n_cells = 1; 324 reset->rcdev.of_xlate = at91_reset_of_xlate; 325 326 return devm_reset_controller_register(&pdev->dev, &reset->rcdev); 327 } 328 329 static int __init at91_reset_probe(struct platform_device *pdev) 330 { 331 const struct of_device_id *match; 332 struct at91_reset *reset; 333 struct device_node *np; 334 int ret, idx = 0; 335 336 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); 337 if (!reset) 338 return -ENOMEM; 339 340 reset->rstc_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); 341 if (IS_ERR(reset->rstc_base)) { 342 dev_err(&pdev->dev, "Could not map reset controller address\n"); 343 return -ENODEV; 344 } 345 346 if (!of_device_is_compatible(pdev->dev.of_node, "atmel,sama5d3-rstc")) { 347 /* we need to shutdown the ddr controller, so get ramc base */ 348 for_each_matching_node_and_match(np, at91_ramc_of_match, &match) { 349 reset->ramc_lpr = (u32)match->data; 350 reset->ramc_base[idx] = devm_of_iomap(&pdev->dev, np, 0, NULL); 351 if (IS_ERR(reset->ramc_base[idx])) { 352 dev_err(&pdev->dev, "Could not map ram controller address\n"); 353 of_node_put(np); 354 return -ENODEV; 355 } 356 idx++; 357 } 358 } 359 360 reset->data = device_get_match_data(&pdev->dev); 361 if (!reset->data) 362 return -ENODEV; 363 364 reset->nb.notifier_call = at91_reset; 365 reset->nb.priority = 192; 366 367 reset->sclk = devm_clk_get(&pdev->dev, NULL); 368 if (IS_ERR(reset->sclk)) 369 return PTR_ERR(reset->sclk); 370 371 ret = clk_prepare_enable(reset->sclk); 372 if (ret) { 373 dev_err(&pdev->dev, "Could not enable slow clock\n"); 374 return ret; 375 } 376 377 platform_set_drvdata(pdev, reset); 378 379 ret = at91_rcdev_init(reset, pdev); 380 if (ret) 381 goto disable_clk; 382 383 if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) { 384 u32 val = readl(reset->rstc_base + AT91_RSTC_MR); 385 386 writel(AT91_RSTC_KEY | AT91_RSTC_URSTASYNC | val, 387 reset->rstc_base + AT91_RSTC_MR); 388 } 389 390 ret = register_restart_handler(&reset->nb); 391 if (ret) 392 goto disable_clk; 393 394 dev_info(&pdev->dev, "Starting after %s\n", at91_reset_reason(reset)); 395 396 return 0; 397 398 disable_clk: 399 clk_disable_unprepare(reset->sclk); 400 return ret; 401 } 402 403 static int __exit at91_reset_remove(struct platform_device *pdev) 404 { 405 struct at91_reset *reset = platform_get_drvdata(pdev); 406 407 unregister_restart_handler(&reset->nb); 408 clk_disable_unprepare(reset->sclk); 409 410 return 0; 411 } 412 413 static struct platform_driver at91_reset_driver = { 414 .remove = __exit_p(at91_reset_remove), 415 .driver = { 416 .name = "at91-reset", 417 .of_match_table = at91_reset_of_match, 418 }, 419 }; 420 module_platform_driver_probe(at91_reset_driver, at91_reset_probe); 421 422 MODULE_AUTHOR("Atmel Corporation"); 423 MODULE_DESCRIPTION("Reset driver for Atmel SoCs"); 424 MODULE_LICENSE("GPL v2"); 425