1 /* 2 * Atmel AT91 SAM9 SoCs reset code 3 * 4 * Copyright (C) 2007 Atmel Corporation. 5 * Copyright (C) BitBox Ltd 2010 6 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com> 7 * Copyright (C) 2014 Free Electrons 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/platform_device.h> 18 #include <linux/reboot.h> 19 20 #include <soc/at91/at91sam9_ddrsdr.h> 21 #include <soc/at91/at91sam9_sdramc.h> 22 23 #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */ 24 #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */ 25 #define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */ 26 #define AT91_RSTC_EXTRST BIT(3) /* External Reset */ 27 #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ 28 29 #define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */ 30 #define AT91_RSTC_URSTS BIT(0) /* User Reset Status */ 31 #define AT91_RSTC_RSTTYP GENMASK(10, 8) /* Reset Type */ 32 #define AT91_RSTC_NRSTL BIT(16) /* NRST Pin Level */ 33 #define AT91_RSTC_SRCMP BIT(17) /* Software Reset Command in Progress */ 34 35 #define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */ 36 #define AT91_RSTC_URSTEN BIT(0) /* User Reset Enable */ 37 #define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */ 38 #define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */ 39 40 enum reset_type { 41 RESET_TYPE_GENERAL = 0, 42 RESET_TYPE_WAKEUP = 1, 43 RESET_TYPE_WATCHDOG = 2, 44 RESET_TYPE_SOFTWARE = 3, 45 RESET_TYPE_USER = 4, 46 }; 47 48 static void __iomem *at91_ramc_base[2], *at91_rstc_base; 49 50 /* 51 * unless the SDRAM is cleanly shutdown before we hit the 52 * reset register it can be left driving the data bus and 53 * killing the chance of a subsequent boot from NAND 54 */ 55 static int at91sam9260_restart(struct notifier_block *this, unsigned long mode, 56 void *cmd) 57 { 58 asm volatile( 59 /* Align to cache lines */ 60 ".balign 32\n\t" 61 62 /* Disable SDRAM accesses */ 63 "str %2, [%0, #" __stringify(AT91_SDRAMC_TR) "]\n\t" 64 65 /* Power down SDRAM */ 66 "str %3, [%0, #" __stringify(AT91_SDRAMC_LPR) "]\n\t" 67 68 /* Reset CPU */ 69 "str %4, [%1, #" __stringify(AT91_RSTC_CR) "]\n\t" 70 71 "b .\n\t" 72 : 73 : "r" (at91_ramc_base[0]), 74 "r" (at91_rstc_base), 75 "r" (1), 76 "r" cpu_to_le32(AT91_SDRAMC_LPCB_POWER_DOWN), 77 "r" cpu_to_le32(AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST)); 78 79 return NOTIFY_DONE; 80 } 81 82 static int at91sam9g45_restart(struct notifier_block *this, unsigned long mode, 83 void *cmd) 84 { 85 asm volatile( 86 /* 87 * Test wether we have a second RAM controller to care 88 * about. 89 * 90 * First, test that we can dereference the virtual address. 91 */ 92 "cmp %1, #0\n\t" 93 "beq 1f\n\t" 94 95 /* Then, test that the RAM controller is enabled */ 96 "ldr r0, [%1]\n\t" 97 "cmp r0, #0\n\t" 98 99 /* Align to cache lines */ 100 ".balign 32\n\t" 101 102 /* Disable SDRAM0 accesses */ 103 "1: str %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t" 104 /* Power down SDRAM0 */ 105 " str %4, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t" 106 /* Disable SDRAM1 accesses */ 107 " strne %3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t" 108 /* Power down SDRAM1 */ 109 " strne %4, [%1, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t" 110 /* Reset CPU */ 111 " str %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t" 112 113 " b .\n\t" 114 : 115 : "r" (at91_ramc_base[0]), 116 "r" (at91_ramc_base[1]), 117 "r" (at91_rstc_base), 118 "r" (1), 119 "r" cpu_to_le32(AT91_DDRSDRC_LPCB_POWER_DOWN), 120 "r" cpu_to_le32(AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST) 121 : "r0"); 122 123 return NOTIFY_DONE; 124 } 125 126 static int sama5d3_restart(struct notifier_block *this, unsigned long mode, 127 void *cmd) 128 { 129 writel(cpu_to_le32(AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST), 130 at91_rstc_base); 131 132 return NOTIFY_DONE; 133 } 134 135 static void __init at91_reset_status(struct platform_device *pdev) 136 { 137 u32 reg = readl(at91_rstc_base + AT91_RSTC_SR); 138 char *reason; 139 140 switch ((reg & AT91_RSTC_RSTTYP) >> 8) { 141 case RESET_TYPE_GENERAL: 142 reason = "general reset"; 143 break; 144 case RESET_TYPE_WAKEUP: 145 reason = "wakeup"; 146 break; 147 case RESET_TYPE_WATCHDOG: 148 reason = "watchdog reset"; 149 break; 150 case RESET_TYPE_SOFTWARE: 151 reason = "software reset"; 152 break; 153 case RESET_TYPE_USER: 154 reason = "user reset"; 155 break; 156 default: 157 reason = "unknown reset"; 158 break; 159 } 160 161 pr_info("AT91: Starting after %s\n", reason); 162 } 163 164 static const struct of_device_id at91_ramc_of_match[] = { 165 { .compatible = "atmel,at91sam9260-sdramc", }, 166 { .compatible = "atmel,at91sam9g45-ddramc", }, 167 { /* sentinel */ } 168 }; 169 170 static const struct of_device_id at91_reset_of_match[] = { 171 { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9260_restart }, 172 { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart }, 173 { .compatible = "atmel,sama5d3-rstc", .data = sama5d3_restart }, 174 { /* sentinel */ } 175 }; 176 177 static struct notifier_block at91_restart_nb = { 178 .priority = 192, 179 }; 180 181 static int at91_reset_of_probe(struct platform_device *pdev) 182 { 183 const struct of_device_id *match; 184 struct device_node *np; 185 int idx = 0; 186 187 at91_rstc_base = of_iomap(pdev->dev.of_node, 0); 188 if (!at91_rstc_base) { 189 dev_err(&pdev->dev, "Could not map reset controller address\n"); 190 return -ENODEV; 191 } 192 193 if (!of_device_is_compatible(pdev->dev.of_node, "atmel,sama5d3-rstc")) { 194 /* we need to shutdown the ddr controller, so get ramc base */ 195 for_each_matching_node(np, at91_ramc_of_match) { 196 at91_ramc_base[idx] = of_iomap(np, 0); 197 if (!at91_ramc_base[idx]) { 198 dev_err(&pdev->dev, "Could not map ram controller address\n"); 199 return -ENODEV; 200 } 201 idx++; 202 } 203 } 204 205 match = of_match_node(at91_reset_of_match, pdev->dev.of_node); 206 at91_restart_nb.notifier_call = match->data; 207 return register_restart_handler(&at91_restart_nb); 208 } 209 210 static int at91_reset_platform_probe(struct platform_device *pdev) 211 { 212 const struct platform_device_id *match; 213 struct resource *res; 214 int idx = 0; 215 216 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 217 at91_rstc_base = devm_ioremap_resource(&pdev->dev, res); 218 if (IS_ERR(at91_rstc_base)) { 219 dev_err(&pdev->dev, "Could not map reset controller address\n"); 220 return PTR_ERR(at91_rstc_base); 221 } 222 223 for (idx = 0; idx < 2; idx++) { 224 res = platform_get_resource(pdev, IORESOURCE_MEM, idx + 1 ); 225 at91_ramc_base[idx] = devm_ioremap(&pdev->dev, res->start, 226 resource_size(res)); 227 if (!at91_ramc_base[idx]) { 228 dev_err(&pdev->dev, "Could not map ram controller address\n"); 229 return -ENOMEM; 230 } 231 } 232 233 match = platform_get_device_id(pdev); 234 at91_restart_nb.notifier_call = 235 (int (*)(struct notifier_block *, 236 unsigned long, void *)) match->driver_data; 237 238 return register_restart_handler(&at91_restart_nb); 239 } 240 241 static int at91_reset_probe(struct platform_device *pdev) 242 { 243 int ret; 244 245 if (pdev->dev.of_node) 246 ret = at91_reset_of_probe(pdev); 247 else 248 ret = at91_reset_platform_probe(pdev); 249 250 if (ret) 251 return ret; 252 253 at91_reset_status(pdev); 254 255 return 0; 256 } 257 258 static const struct platform_device_id at91_reset_plat_match[] = { 259 { "at91-sam9260-reset", (unsigned long)at91sam9260_restart }, 260 { "at91-sam9g45-reset", (unsigned long)at91sam9g45_restart }, 261 { /* sentinel */ } 262 }; 263 264 static struct platform_driver at91_reset_driver = { 265 .probe = at91_reset_probe, 266 .driver = { 267 .name = "at91-reset", 268 .of_match_table = at91_reset_of_match, 269 }, 270 .id_table = at91_reset_plat_match, 271 }; 272 module_platform_driver(at91_reset_driver); 273