1*e2ad626fSUlf Hansson /* SPDX-License-Identifier: GPL-2.0-only */ 2*e2ad626fSUlf Hansson 3*e2ad626fSUlf Hansson #ifndef __SOC_MEDIATEK_MT6795_PM_DOMAINS_H 4*e2ad626fSUlf Hansson #define __SOC_MEDIATEK_MT6795_PM_DOMAINS_H 5*e2ad626fSUlf Hansson 6*e2ad626fSUlf Hansson #include "mtk-pm-domains.h" 7*e2ad626fSUlf Hansson #include <dt-bindings/power/mt6795-power.h> 8*e2ad626fSUlf Hansson 9*e2ad626fSUlf Hansson /* 10*e2ad626fSUlf Hansson * MT6795 power domain support 11*e2ad626fSUlf Hansson */ 12*e2ad626fSUlf Hansson 13*e2ad626fSUlf Hansson static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = { 14*e2ad626fSUlf Hansson [MT6795_POWER_DOMAIN_VDEC] = { 15*e2ad626fSUlf Hansson .name = "vdec", 16*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_VDEC, 17*e2ad626fSUlf Hansson .ctl_offs = SPM_VDE_PWR_CON, 18*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 19*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 20*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 21*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 22*e2ad626fSUlf Hansson }, 23*e2ad626fSUlf Hansson [MT6795_POWER_DOMAIN_VENC] = { 24*e2ad626fSUlf Hansson .name = "venc", 25*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_VENC, 26*e2ad626fSUlf Hansson .ctl_offs = SPM_VEN_PWR_CON, 27*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 28*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 29*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 30*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(15, 12), 31*e2ad626fSUlf Hansson }, 32*e2ad626fSUlf Hansson [MT6795_POWER_DOMAIN_ISP] = { 33*e2ad626fSUlf Hansson .name = "isp", 34*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_ISP, 35*e2ad626fSUlf Hansson .ctl_offs = SPM_ISP_PWR_CON, 36*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 37*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 38*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 39*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(13, 12), 40*e2ad626fSUlf Hansson }, 41*e2ad626fSUlf Hansson [MT6795_POWER_DOMAIN_MM] = { 42*e2ad626fSUlf Hansson .name = "mm", 43*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_DISP, 44*e2ad626fSUlf Hansson .ctl_offs = SPM_DIS_PWR_CON, 45*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 46*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 47*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 48*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 49*e2ad626fSUlf Hansson .bp_infracfg = { 50*e2ad626fSUlf Hansson BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | 51*e2ad626fSUlf Hansson MT8173_TOP_AXI_PROT_EN_MM_M1), 52*e2ad626fSUlf Hansson }, 53*e2ad626fSUlf Hansson }, 54*e2ad626fSUlf Hansson [MT6795_POWER_DOMAIN_MJC] = { 55*e2ad626fSUlf Hansson .name = "mjc", 56*e2ad626fSUlf Hansson .sta_mask = BIT(20), 57*e2ad626fSUlf Hansson .ctl_offs = 0x298, 58*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 59*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 60*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 61*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(15, 12), 62*e2ad626fSUlf Hansson }, 63*e2ad626fSUlf Hansson [MT6795_POWER_DOMAIN_AUDIO] = { 64*e2ad626fSUlf Hansson .name = "audio", 65*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_AUDIO, 66*e2ad626fSUlf Hansson .ctl_offs = SPM_AUDIO_PWR_CON, 67*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 68*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 69*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 70*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(15, 12), 71*e2ad626fSUlf Hansson }, 72*e2ad626fSUlf Hansson [MT6795_POWER_DOMAIN_MFG_ASYNC] = { 73*e2ad626fSUlf Hansson .name = "mfg_async", 74*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_MFG_ASYNC, 75*e2ad626fSUlf Hansson .ctl_offs = SPM_MFG_ASYNC_PWR_CON, 76*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 77*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 78*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 79*e2ad626fSUlf Hansson .sram_pdn_ack_bits = 0, 80*e2ad626fSUlf Hansson }, 81*e2ad626fSUlf Hansson [MT6795_POWER_DOMAIN_MFG_2D] = { 82*e2ad626fSUlf Hansson .name = "mfg_2d", 83*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_MFG_2D, 84*e2ad626fSUlf Hansson .ctl_offs = SPM_MFG_2D_PWR_CON, 85*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 86*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 87*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 88*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(13, 12), 89*e2ad626fSUlf Hansson }, 90*e2ad626fSUlf Hansson [MT6795_POWER_DOMAIN_MFG] = { 91*e2ad626fSUlf Hansson .name = "mfg", 92*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_MFG, 93*e2ad626fSUlf Hansson .ctl_offs = SPM_MFG_PWR_CON, 94*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 95*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 96*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(13, 8), 97*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(21, 16), 98*e2ad626fSUlf Hansson .bp_infracfg = { 99*e2ad626fSUlf Hansson BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | 100*e2ad626fSUlf Hansson MT8173_TOP_AXI_PROT_EN_MFG_M0 | 101*e2ad626fSUlf Hansson MT8173_TOP_AXI_PROT_EN_MFG_M1 | 102*e2ad626fSUlf Hansson MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), 103*e2ad626fSUlf Hansson }, 104*e2ad626fSUlf Hansson }, 105*e2ad626fSUlf Hansson }; 106*e2ad626fSUlf Hansson 107*e2ad626fSUlf Hansson static const struct scpsys_soc_data mt6795_scpsys_data = { 108*e2ad626fSUlf Hansson .domains_data = scpsys_domain_data_mt6795, 109*e2ad626fSUlf Hansson .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6795), 110*e2ad626fSUlf Hansson }; 111*e2ad626fSUlf Hansson 112*e2ad626fSUlf Hansson #endif /* __SOC_MEDIATEK_MT6795_PM_DOMAINS_H */ 113