1*e2ad626fSUlf Hansson // SPDX-License-Identifier: GPL-2.0
2*e2ad626fSUlf Hansson /*
3*e2ad626fSUlf Hansson * Copyright 2022 NXP, Peng Fan <peng.fan@nxp.com>
4*e2ad626fSUlf Hansson */
5*e2ad626fSUlf Hansson
6*e2ad626fSUlf Hansson #include <linux/clk.h>
7*e2ad626fSUlf Hansson #include <linux/device.h>
8*e2ad626fSUlf Hansson #include <linux/module.h>
9*e2ad626fSUlf Hansson #include <linux/of.h>
10*e2ad626fSUlf Hansson #include <linux/platform_device.h>
11*e2ad626fSUlf Hansson #include <linux/pm_domain.h>
12*e2ad626fSUlf Hansson #include <linux/pm_runtime.h>
13*e2ad626fSUlf Hansson #include <linux/regmap.h>
14*e2ad626fSUlf Hansson #include <linux/sizes.h>
15*e2ad626fSUlf Hansson
16*e2ad626fSUlf Hansson #include <dt-bindings/power/fsl,imx93-power.h>
17*e2ad626fSUlf Hansson
18*e2ad626fSUlf Hansson #define BLK_SFT_RSTN 0x0
19*e2ad626fSUlf Hansson #define BLK_CLK_EN 0x4
20*e2ad626fSUlf Hansson #define BLK_MAX_CLKS 4
21*e2ad626fSUlf Hansson
22*e2ad626fSUlf Hansson #define DOMAIN_MAX_CLKS 4
23*e2ad626fSUlf Hansson
24*e2ad626fSUlf Hansson #define LCDIF_QOS_REG 0xC
25*e2ad626fSUlf Hansson #define LCDIF_DEFAULT_QOS_OFF 12
26*e2ad626fSUlf Hansson #define LCDIF_CFG_QOS_OFF 8
27*e2ad626fSUlf Hansson
28*e2ad626fSUlf Hansson #define PXP_QOS_REG 0x10
29*e2ad626fSUlf Hansson #define PXP_R_DEFAULT_QOS_OFF 28
30*e2ad626fSUlf Hansson #define PXP_R_CFG_QOS_OFF 24
31*e2ad626fSUlf Hansson #define PXP_W_DEFAULT_QOS_OFF 20
32*e2ad626fSUlf Hansson #define PXP_W_CFG_QOS_OFF 16
33*e2ad626fSUlf Hansson
34*e2ad626fSUlf Hansson #define ISI_CACHE_REG 0x14
35*e2ad626fSUlf Hansson
36*e2ad626fSUlf Hansson #define ISI_QOS_REG 0x1C
37*e2ad626fSUlf Hansson #define ISI_V_DEFAULT_QOS_OFF 28
38*e2ad626fSUlf Hansson #define ISI_V_CFG_QOS_OFF 24
39*e2ad626fSUlf Hansson #define ISI_U_DEFAULT_QOS_OFF 20
40*e2ad626fSUlf Hansson #define ISI_U_CFG_QOS_OFF 16
41*e2ad626fSUlf Hansson #define ISI_Y_R_DEFAULT_QOS_OFF 12
42*e2ad626fSUlf Hansson #define ISI_Y_R_CFG_QOS_OFF 8
43*e2ad626fSUlf Hansson #define ISI_Y_W_DEFAULT_QOS_OFF 4
44*e2ad626fSUlf Hansson #define ISI_Y_W_CFG_QOS_OFF 0
45*e2ad626fSUlf Hansson
46*e2ad626fSUlf Hansson #define PRIO_MASK 0xF
47*e2ad626fSUlf Hansson
48*e2ad626fSUlf Hansson #define PRIO(X) (X)
49*e2ad626fSUlf Hansson
50*e2ad626fSUlf Hansson struct imx93_blk_ctrl_domain;
51*e2ad626fSUlf Hansson
52*e2ad626fSUlf Hansson struct imx93_blk_ctrl {
53*e2ad626fSUlf Hansson struct device *dev;
54*e2ad626fSUlf Hansson struct regmap *regmap;
55*e2ad626fSUlf Hansson int num_clks;
56*e2ad626fSUlf Hansson struct clk_bulk_data clks[BLK_MAX_CLKS];
57*e2ad626fSUlf Hansson struct imx93_blk_ctrl_domain *domains;
58*e2ad626fSUlf Hansson struct genpd_onecell_data onecell_data;
59*e2ad626fSUlf Hansson };
60*e2ad626fSUlf Hansson
61*e2ad626fSUlf Hansson #define DOMAIN_MAX_QOS 4
62*e2ad626fSUlf Hansson
63*e2ad626fSUlf Hansson struct imx93_blk_ctrl_qos {
64*e2ad626fSUlf Hansson u32 reg;
65*e2ad626fSUlf Hansson u32 cfg_off;
66*e2ad626fSUlf Hansson u32 default_prio;
67*e2ad626fSUlf Hansson u32 cfg_prio;
68*e2ad626fSUlf Hansson };
69*e2ad626fSUlf Hansson
70*e2ad626fSUlf Hansson struct imx93_blk_ctrl_domain_data {
71*e2ad626fSUlf Hansson const char *name;
72*e2ad626fSUlf Hansson const char * const *clk_names;
73*e2ad626fSUlf Hansson int num_clks;
74*e2ad626fSUlf Hansson u32 rst_mask;
75*e2ad626fSUlf Hansson u32 clk_mask;
76*e2ad626fSUlf Hansson int num_qos;
77*e2ad626fSUlf Hansson struct imx93_blk_ctrl_qos qos[DOMAIN_MAX_QOS];
78*e2ad626fSUlf Hansson };
79*e2ad626fSUlf Hansson
80*e2ad626fSUlf Hansson struct imx93_blk_ctrl_domain {
81*e2ad626fSUlf Hansson struct generic_pm_domain genpd;
82*e2ad626fSUlf Hansson const struct imx93_blk_ctrl_domain_data *data;
83*e2ad626fSUlf Hansson struct clk_bulk_data clks[DOMAIN_MAX_CLKS];
84*e2ad626fSUlf Hansson struct imx93_blk_ctrl *bc;
85*e2ad626fSUlf Hansson };
86*e2ad626fSUlf Hansson
87*e2ad626fSUlf Hansson struct imx93_blk_ctrl_data {
88*e2ad626fSUlf Hansson const struct imx93_blk_ctrl_domain_data *domains;
89*e2ad626fSUlf Hansson int num_domains;
90*e2ad626fSUlf Hansson const char * const *clk_names;
91*e2ad626fSUlf Hansson int num_clks;
92*e2ad626fSUlf Hansson const struct regmap_access_table *reg_access_table;
93*e2ad626fSUlf Hansson };
94*e2ad626fSUlf Hansson
95*e2ad626fSUlf Hansson static inline struct imx93_blk_ctrl_domain *
to_imx93_blk_ctrl_domain(struct generic_pm_domain * genpd)96*e2ad626fSUlf Hansson to_imx93_blk_ctrl_domain(struct generic_pm_domain *genpd)
97*e2ad626fSUlf Hansson {
98*e2ad626fSUlf Hansson return container_of(genpd, struct imx93_blk_ctrl_domain, genpd);
99*e2ad626fSUlf Hansson }
100*e2ad626fSUlf Hansson
imx93_blk_ctrl_set_qos(struct imx93_blk_ctrl_domain * domain)101*e2ad626fSUlf Hansson static int imx93_blk_ctrl_set_qos(struct imx93_blk_ctrl_domain *domain)
102*e2ad626fSUlf Hansson {
103*e2ad626fSUlf Hansson const struct imx93_blk_ctrl_domain_data *data = domain->data;
104*e2ad626fSUlf Hansson struct imx93_blk_ctrl *bc = domain->bc;
105*e2ad626fSUlf Hansson const struct imx93_blk_ctrl_qos *qos;
106*e2ad626fSUlf Hansson u32 val, mask;
107*e2ad626fSUlf Hansson int i;
108*e2ad626fSUlf Hansson
109*e2ad626fSUlf Hansson for (i = 0; i < data->num_qos; i++) {
110*e2ad626fSUlf Hansson qos = &data->qos[i];
111*e2ad626fSUlf Hansson
112*e2ad626fSUlf Hansson mask = PRIO_MASK << qos->cfg_off;
113*e2ad626fSUlf Hansson mask |= PRIO_MASK << (qos->cfg_off + 4);
114*e2ad626fSUlf Hansson val = qos->cfg_prio << qos->cfg_off;
115*e2ad626fSUlf Hansson val |= qos->default_prio << (qos->cfg_off + 4);
116*e2ad626fSUlf Hansson
117*e2ad626fSUlf Hansson regmap_write_bits(bc->regmap, qos->reg, mask, val);
118*e2ad626fSUlf Hansson
119*e2ad626fSUlf Hansson dev_dbg(bc->dev, "data->qos[i].reg 0x%x 0x%x\n", qos->reg, val);
120*e2ad626fSUlf Hansson }
121*e2ad626fSUlf Hansson
122*e2ad626fSUlf Hansson return 0;
123*e2ad626fSUlf Hansson }
124*e2ad626fSUlf Hansson
imx93_blk_ctrl_power_on(struct generic_pm_domain * genpd)125*e2ad626fSUlf Hansson static int imx93_blk_ctrl_power_on(struct generic_pm_domain *genpd)
126*e2ad626fSUlf Hansson {
127*e2ad626fSUlf Hansson struct imx93_blk_ctrl_domain *domain = to_imx93_blk_ctrl_domain(genpd);
128*e2ad626fSUlf Hansson const struct imx93_blk_ctrl_domain_data *data = domain->data;
129*e2ad626fSUlf Hansson struct imx93_blk_ctrl *bc = domain->bc;
130*e2ad626fSUlf Hansson int ret;
131*e2ad626fSUlf Hansson
132*e2ad626fSUlf Hansson ret = clk_bulk_prepare_enable(bc->num_clks, bc->clks);
133*e2ad626fSUlf Hansson if (ret) {
134*e2ad626fSUlf Hansson dev_err(bc->dev, "failed to enable bus clocks\n");
135*e2ad626fSUlf Hansson return ret;
136*e2ad626fSUlf Hansson }
137*e2ad626fSUlf Hansson
138*e2ad626fSUlf Hansson ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);
139*e2ad626fSUlf Hansson if (ret) {
140*e2ad626fSUlf Hansson clk_bulk_disable_unprepare(bc->num_clks, bc->clks);
141*e2ad626fSUlf Hansson dev_err(bc->dev, "failed to enable clocks\n");
142*e2ad626fSUlf Hansson return ret;
143*e2ad626fSUlf Hansson }
144*e2ad626fSUlf Hansson
145*e2ad626fSUlf Hansson ret = pm_runtime_get_sync(bc->dev);
146*e2ad626fSUlf Hansson if (ret < 0) {
147*e2ad626fSUlf Hansson pm_runtime_put_noidle(bc->dev);
148*e2ad626fSUlf Hansson dev_err(bc->dev, "failed to power up domain\n");
149*e2ad626fSUlf Hansson goto disable_clk;
150*e2ad626fSUlf Hansson }
151*e2ad626fSUlf Hansson
152*e2ad626fSUlf Hansson /* ungate clk */
153*e2ad626fSUlf Hansson regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
154*e2ad626fSUlf Hansson
155*e2ad626fSUlf Hansson /* release reset */
156*e2ad626fSUlf Hansson regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
157*e2ad626fSUlf Hansson
158*e2ad626fSUlf Hansson dev_dbg(bc->dev, "pd_on: name: %s\n", genpd->name);
159*e2ad626fSUlf Hansson
160*e2ad626fSUlf Hansson return imx93_blk_ctrl_set_qos(domain);
161*e2ad626fSUlf Hansson
162*e2ad626fSUlf Hansson disable_clk:
163*e2ad626fSUlf Hansson clk_bulk_disable_unprepare(data->num_clks, domain->clks);
164*e2ad626fSUlf Hansson
165*e2ad626fSUlf Hansson clk_bulk_disable_unprepare(bc->num_clks, bc->clks);
166*e2ad626fSUlf Hansson
167*e2ad626fSUlf Hansson return ret;
168*e2ad626fSUlf Hansson }
169*e2ad626fSUlf Hansson
imx93_blk_ctrl_power_off(struct generic_pm_domain * genpd)170*e2ad626fSUlf Hansson static int imx93_blk_ctrl_power_off(struct generic_pm_domain *genpd)
171*e2ad626fSUlf Hansson {
172*e2ad626fSUlf Hansson struct imx93_blk_ctrl_domain *domain = to_imx93_blk_ctrl_domain(genpd);
173*e2ad626fSUlf Hansson const struct imx93_blk_ctrl_domain_data *data = domain->data;
174*e2ad626fSUlf Hansson struct imx93_blk_ctrl *bc = domain->bc;
175*e2ad626fSUlf Hansson
176*e2ad626fSUlf Hansson dev_dbg(bc->dev, "pd_off: name: %s\n", genpd->name);
177*e2ad626fSUlf Hansson
178*e2ad626fSUlf Hansson regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
179*e2ad626fSUlf Hansson regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
180*e2ad626fSUlf Hansson
181*e2ad626fSUlf Hansson pm_runtime_put(bc->dev);
182*e2ad626fSUlf Hansson
183*e2ad626fSUlf Hansson clk_bulk_disable_unprepare(data->num_clks, domain->clks);
184*e2ad626fSUlf Hansson
185*e2ad626fSUlf Hansson clk_bulk_disable_unprepare(bc->num_clks, bc->clks);
186*e2ad626fSUlf Hansson
187*e2ad626fSUlf Hansson return 0;
188*e2ad626fSUlf Hansson }
189*e2ad626fSUlf Hansson
190*e2ad626fSUlf Hansson static struct lock_class_key blk_ctrl_genpd_lock_class;
191*e2ad626fSUlf Hansson
imx93_blk_ctrl_probe(struct platform_device * pdev)192*e2ad626fSUlf Hansson static int imx93_blk_ctrl_probe(struct platform_device *pdev)
193*e2ad626fSUlf Hansson {
194*e2ad626fSUlf Hansson struct device *dev = &pdev->dev;
195*e2ad626fSUlf Hansson const struct imx93_blk_ctrl_data *bc_data = of_device_get_match_data(dev);
196*e2ad626fSUlf Hansson struct imx93_blk_ctrl *bc;
197*e2ad626fSUlf Hansson void __iomem *base;
198*e2ad626fSUlf Hansson int i, ret;
199*e2ad626fSUlf Hansson
200*e2ad626fSUlf Hansson struct regmap_config regmap_config = {
201*e2ad626fSUlf Hansson .reg_bits = 32,
202*e2ad626fSUlf Hansson .val_bits = 32,
203*e2ad626fSUlf Hansson .reg_stride = 4,
204*e2ad626fSUlf Hansson .rd_table = bc_data->reg_access_table,
205*e2ad626fSUlf Hansson .wr_table = bc_data->reg_access_table,
206*e2ad626fSUlf Hansson .max_register = SZ_4K,
207*e2ad626fSUlf Hansson };
208*e2ad626fSUlf Hansson
209*e2ad626fSUlf Hansson bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
210*e2ad626fSUlf Hansson if (!bc)
211*e2ad626fSUlf Hansson return -ENOMEM;
212*e2ad626fSUlf Hansson
213*e2ad626fSUlf Hansson bc->dev = dev;
214*e2ad626fSUlf Hansson
215*e2ad626fSUlf Hansson base = devm_platform_ioremap_resource(pdev, 0);
216*e2ad626fSUlf Hansson if (IS_ERR(base))
217*e2ad626fSUlf Hansson return PTR_ERR(base);
218*e2ad626fSUlf Hansson
219*e2ad626fSUlf Hansson bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
220*e2ad626fSUlf Hansson if (IS_ERR(bc->regmap))
221*e2ad626fSUlf Hansson return dev_err_probe(dev, PTR_ERR(bc->regmap),
222*e2ad626fSUlf Hansson "failed to init regmap\n");
223*e2ad626fSUlf Hansson
224*e2ad626fSUlf Hansson bc->domains = devm_kcalloc(dev, bc_data->num_domains,
225*e2ad626fSUlf Hansson sizeof(struct imx93_blk_ctrl_domain),
226*e2ad626fSUlf Hansson GFP_KERNEL);
227*e2ad626fSUlf Hansson if (!bc->domains)
228*e2ad626fSUlf Hansson return -ENOMEM;
229*e2ad626fSUlf Hansson
230*e2ad626fSUlf Hansson bc->onecell_data.num_domains = bc_data->num_domains;
231*e2ad626fSUlf Hansson bc->onecell_data.domains =
232*e2ad626fSUlf Hansson devm_kcalloc(dev, bc_data->num_domains,
233*e2ad626fSUlf Hansson sizeof(struct generic_pm_domain *), GFP_KERNEL);
234*e2ad626fSUlf Hansson if (!bc->onecell_data.domains)
235*e2ad626fSUlf Hansson return -ENOMEM;
236*e2ad626fSUlf Hansson
237*e2ad626fSUlf Hansson for (i = 0; i < bc_data->num_clks; i++)
238*e2ad626fSUlf Hansson bc->clks[i].id = bc_data->clk_names[i];
239*e2ad626fSUlf Hansson bc->num_clks = bc_data->num_clks;
240*e2ad626fSUlf Hansson
241*e2ad626fSUlf Hansson ret = devm_clk_bulk_get(dev, bc->num_clks, bc->clks);
242*e2ad626fSUlf Hansson if (ret) {
243*e2ad626fSUlf Hansson dev_err_probe(dev, ret, "failed to get bus clock\n");
244*e2ad626fSUlf Hansson return ret;
245*e2ad626fSUlf Hansson }
246*e2ad626fSUlf Hansson
247*e2ad626fSUlf Hansson for (i = 0; i < bc_data->num_domains; i++) {
248*e2ad626fSUlf Hansson const struct imx93_blk_ctrl_domain_data *data = &bc_data->domains[i];
249*e2ad626fSUlf Hansson struct imx93_blk_ctrl_domain *domain = &bc->domains[i];
250*e2ad626fSUlf Hansson int j;
251*e2ad626fSUlf Hansson
252*e2ad626fSUlf Hansson domain->data = data;
253*e2ad626fSUlf Hansson
254*e2ad626fSUlf Hansson for (j = 0; j < data->num_clks; j++)
255*e2ad626fSUlf Hansson domain->clks[j].id = data->clk_names[j];
256*e2ad626fSUlf Hansson
257*e2ad626fSUlf Hansson ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
258*e2ad626fSUlf Hansson if (ret) {
259*e2ad626fSUlf Hansson dev_err_probe(dev, ret, "failed to get clock\n");
260*e2ad626fSUlf Hansson goto cleanup_pds;
261*e2ad626fSUlf Hansson }
262*e2ad626fSUlf Hansson
263*e2ad626fSUlf Hansson domain->genpd.name = data->name;
264*e2ad626fSUlf Hansson domain->genpd.power_on = imx93_blk_ctrl_power_on;
265*e2ad626fSUlf Hansson domain->genpd.power_off = imx93_blk_ctrl_power_off;
266*e2ad626fSUlf Hansson domain->bc = bc;
267*e2ad626fSUlf Hansson
268*e2ad626fSUlf Hansson ret = pm_genpd_init(&domain->genpd, NULL, true);
269*e2ad626fSUlf Hansson if (ret) {
270*e2ad626fSUlf Hansson dev_err_probe(dev, ret, "failed to init power domain\n");
271*e2ad626fSUlf Hansson goto cleanup_pds;
272*e2ad626fSUlf Hansson }
273*e2ad626fSUlf Hansson
274*e2ad626fSUlf Hansson /*
275*e2ad626fSUlf Hansson * We use runtime PM to trigger power on/off of the upstream GPC
276*e2ad626fSUlf Hansson * domain, as a strict hierarchical parent/child power domain
277*e2ad626fSUlf Hansson * setup doesn't allow us to meet the sequencing requirements.
278*e2ad626fSUlf Hansson * This means we have nested locking of genpd locks, without the
279*e2ad626fSUlf Hansson * nesting being visible at the genpd level, so we need a
280*e2ad626fSUlf Hansson * separate lock class to make lockdep aware of the fact that
281*e2ad626fSUlf Hansson * this are separate domain locks that can be nested without a
282*e2ad626fSUlf Hansson * self-deadlock.
283*e2ad626fSUlf Hansson */
284*e2ad626fSUlf Hansson lockdep_set_class(&domain->genpd.mlock,
285*e2ad626fSUlf Hansson &blk_ctrl_genpd_lock_class);
286*e2ad626fSUlf Hansson
287*e2ad626fSUlf Hansson bc->onecell_data.domains[i] = &domain->genpd;
288*e2ad626fSUlf Hansson }
289*e2ad626fSUlf Hansson
290*e2ad626fSUlf Hansson pm_runtime_enable(dev);
291*e2ad626fSUlf Hansson
292*e2ad626fSUlf Hansson ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
293*e2ad626fSUlf Hansson if (ret) {
294*e2ad626fSUlf Hansson dev_err_probe(dev, ret, "failed to add power domain provider\n");
295*e2ad626fSUlf Hansson goto cleanup_pds;
296*e2ad626fSUlf Hansson }
297*e2ad626fSUlf Hansson
298*e2ad626fSUlf Hansson dev_set_drvdata(dev, bc);
299*e2ad626fSUlf Hansson
300*e2ad626fSUlf Hansson return 0;
301*e2ad626fSUlf Hansson
302*e2ad626fSUlf Hansson cleanup_pds:
303*e2ad626fSUlf Hansson for (i--; i >= 0; i--)
304*e2ad626fSUlf Hansson pm_genpd_remove(&bc->domains[i].genpd);
305*e2ad626fSUlf Hansson
306*e2ad626fSUlf Hansson return ret;
307*e2ad626fSUlf Hansson }
308*e2ad626fSUlf Hansson
imx93_blk_ctrl_remove(struct platform_device * pdev)309*e2ad626fSUlf Hansson static int imx93_blk_ctrl_remove(struct platform_device *pdev)
310*e2ad626fSUlf Hansson {
311*e2ad626fSUlf Hansson struct imx93_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
312*e2ad626fSUlf Hansson int i;
313*e2ad626fSUlf Hansson
314*e2ad626fSUlf Hansson of_genpd_del_provider(pdev->dev.of_node);
315*e2ad626fSUlf Hansson
316*e2ad626fSUlf Hansson for (i = 0; bc->onecell_data.num_domains; i++) {
317*e2ad626fSUlf Hansson struct imx93_blk_ctrl_domain *domain = &bc->domains[i];
318*e2ad626fSUlf Hansson
319*e2ad626fSUlf Hansson pm_genpd_remove(&domain->genpd);
320*e2ad626fSUlf Hansson }
321*e2ad626fSUlf Hansson
322*e2ad626fSUlf Hansson return 0;
323*e2ad626fSUlf Hansson }
324*e2ad626fSUlf Hansson
325*e2ad626fSUlf Hansson static const struct imx93_blk_ctrl_domain_data imx93_media_blk_ctl_domain_data[] = {
326*e2ad626fSUlf Hansson [IMX93_MEDIABLK_PD_MIPI_DSI] = {
327*e2ad626fSUlf Hansson .name = "mediablk-mipi-dsi",
328*e2ad626fSUlf Hansson .clk_names = (const char *[]){ "dsi" },
329*e2ad626fSUlf Hansson .num_clks = 1,
330*e2ad626fSUlf Hansson .rst_mask = BIT(11) | BIT(12),
331*e2ad626fSUlf Hansson .clk_mask = BIT(11) | BIT(12),
332*e2ad626fSUlf Hansson },
333*e2ad626fSUlf Hansson [IMX93_MEDIABLK_PD_MIPI_CSI] = {
334*e2ad626fSUlf Hansson .name = "mediablk-mipi-csi",
335*e2ad626fSUlf Hansson .clk_names = (const char *[]){ "cam", "csi" },
336*e2ad626fSUlf Hansson .num_clks = 2,
337*e2ad626fSUlf Hansson .rst_mask = BIT(9) | BIT(10),
338*e2ad626fSUlf Hansson .clk_mask = BIT(9) | BIT(10),
339*e2ad626fSUlf Hansson },
340*e2ad626fSUlf Hansson [IMX93_MEDIABLK_PD_PXP] = {
341*e2ad626fSUlf Hansson .name = "mediablk-pxp",
342*e2ad626fSUlf Hansson .clk_names = (const char *[]){ "pxp" },
343*e2ad626fSUlf Hansson .num_clks = 1,
344*e2ad626fSUlf Hansson .rst_mask = BIT(7) | BIT(8),
345*e2ad626fSUlf Hansson .clk_mask = BIT(7) | BIT(8),
346*e2ad626fSUlf Hansson .num_qos = 2,
347*e2ad626fSUlf Hansson .qos = {
348*e2ad626fSUlf Hansson {
349*e2ad626fSUlf Hansson .reg = PXP_QOS_REG,
350*e2ad626fSUlf Hansson .cfg_off = PXP_R_CFG_QOS_OFF,
351*e2ad626fSUlf Hansson .default_prio = PRIO(3),
352*e2ad626fSUlf Hansson .cfg_prio = PRIO(6),
353*e2ad626fSUlf Hansson }, {
354*e2ad626fSUlf Hansson .reg = PXP_QOS_REG,
355*e2ad626fSUlf Hansson .cfg_off = PXP_W_CFG_QOS_OFF,
356*e2ad626fSUlf Hansson .default_prio = PRIO(3),
357*e2ad626fSUlf Hansson .cfg_prio = PRIO(6),
358*e2ad626fSUlf Hansson }
359*e2ad626fSUlf Hansson }
360*e2ad626fSUlf Hansson },
361*e2ad626fSUlf Hansson [IMX93_MEDIABLK_PD_LCDIF] = {
362*e2ad626fSUlf Hansson .name = "mediablk-lcdif",
363*e2ad626fSUlf Hansson .clk_names = (const char *[]){ "disp", "lcdif" },
364*e2ad626fSUlf Hansson .num_clks = 2,
365*e2ad626fSUlf Hansson .rst_mask = BIT(4) | BIT(5) | BIT(6),
366*e2ad626fSUlf Hansson .clk_mask = BIT(4) | BIT(5) | BIT(6),
367*e2ad626fSUlf Hansson .num_qos = 1,
368*e2ad626fSUlf Hansson .qos = {
369*e2ad626fSUlf Hansson {
370*e2ad626fSUlf Hansson .reg = LCDIF_QOS_REG,
371*e2ad626fSUlf Hansson .cfg_off = LCDIF_CFG_QOS_OFF,
372*e2ad626fSUlf Hansson .default_prio = PRIO(3),
373*e2ad626fSUlf Hansson .cfg_prio = PRIO(7),
374*e2ad626fSUlf Hansson }
375*e2ad626fSUlf Hansson }
376*e2ad626fSUlf Hansson },
377*e2ad626fSUlf Hansson [IMX93_MEDIABLK_PD_ISI] = {
378*e2ad626fSUlf Hansson .name = "mediablk-isi",
379*e2ad626fSUlf Hansson .clk_names = (const char *[]){ "isi" },
380*e2ad626fSUlf Hansson .num_clks = 1,
381*e2ad626fSUlf Hansson .rst_mask = BIT(2) | BIT(3),
382*e2ad626fSUlf Hansson .clk_mask = BIT(2) | BIT(3),
383*e2ad626fSUlf Hansson .num_qos = 4,
384*e2ad626fSUlf Hansson .qos = {
385*e2ad626fSUlf Hansson {
386*e2ad626fSUlf Hansson .reg = ISI_QOS_REG,
387*e2ad626fSUlf Hansson .cfg_off = ISI_Y_W_CFG_QOS_OFF,
388*e2ad626fSUlf Hansson .default_prio = PRIO(3),
389*e2ad626fSUlf Hansson .cfg_prio = PRIO(7),
390*e2ad626fSUlf Hansson }, {
391*e2ad626fSUlf Hansson .reg = ISI_QOS_REG,
392*e2ad626fSUlf Hansson .cfg_off = ISI_Y_R_CFG_QOS_OFF,
393*e2ad626fSUlf Hansson .default_prio = PRIO(3),
394*e2ad626fSUlf Hansson .cfg_prio = PRIO(7),
395*e2ad626fSUlf Hansson }, {
396*e2ad626fSUlf Hansson .reg = ISI_QOS_REG,
397*e2ad626fSUlf Hansson .cfg_off = ISI_U_CFG_QOS_OFF,
398*e2ad626fSUlf Hansson .default_prio = PRIO(3),
399*e2ad626fSUlf Hansson .cfg_prio = PRIO(7),
400*e2ad626fSUlf Hansson }, {
401*e2ad626fSUlf Hansson .reg = ISI_QOS_REG,
402*e2ad626fSUlf Hansson .cfg_off = ISI_V_CFG_QOS_OFF,
403*e2ad626fSUlf Hansson .default_prio = PRIO(3),
404*e2ad626fSUlf Hansson .cfg_prio = PRIO(7),
405*e2ad626fSUlf Hansson }
406*e2ad626fSUlf Hansson }
407*e2ad626fSUlf Hansson },
408*e2ad626fSUlf Hansson };
409*e2ad626fSUlf Hansson
410*e2ad626fSUlf Hansson static const struct regmap_range imx93_media_blk_ctl_yes_ranges[] = {
411*e2ad626fSUlf Hansson regmap_reg_range(BLK_SFT_RSTN, BLK_CLK_EN),
412*e2ad626fSUlf Hansson regmap_reg_range(LCDIF_QOS_REG, ISI_CACHE_REG),
413*e2ad626fSUlf Hansson regmap_reg_range(ISI_QOS_REG, ISI_QOS_REG),
414*e2ad626fSUlf Hansson };
415*e2ad626fSUlf Hansson
416*e2ad626fSUlf Hansson static const struct regmap_access_table imx93_media_blk_ctl_access_table = {
417*e2ad626fSUlf Hansson .yes_ranges = imx93_media_blk_ctl_yes_ranges,
418*e2ad626fSUlf Hansson .n_yes_ranges = ARRAY_SIZE(imx93_media_blk_ctl_yes_ranges),
419*e2ad626fSUlf Hansson };
420*e2ad626fSUlf Hansson
421*e2ad626fSUlf Hansson static const struct imx93_blk_ctrl_data imx93_media_blk_ctl_dev_data = {
422*e2ad626fSUlf Hansson .domains = imx93_media_blk_ctl_domain_data,
423*e2ad626fSUlf Hansson .num_domains = ARRAY_SIZE(imx93_media_blk_ctl_domain_data),
424*e2ad626fSUlf Hansson .clk_names = (const char *[]){ "axi", "apb", "nic", },
425*e2ad626fSUlf Hansson .num_clks = 3,
426*e2ad626fSUlf Hansson .reg_access_table = &imx93_media_blk_ctl_access_table,
427*e2ad626fSUlf Hansson };
428*e2ad626fSUlf Hansson
429*e2ad626fSUlf Hansson static const struct of_device_id imx93_blk_ctrl_of_match[] = {
430*e2ad626fSUlf Hansson {
431*e2ad626fSUlf Hansson .compatible = "fsl,imx93-media-blk-ctrl",
432*e2ad626fSUlf Hansson .data = &imx93_media_blk_ctl_dev_data
433*e2ad626fSUlf Hansson }, {
434*e2ad626fSUlf Hansson /* Sentinel */
435*e2ad626fSUlf Hansson }
436*e2ad626fSUlf Hansson };
437*e2ad626fSUlf Hansson MODULE_DEVICE_TABLE(of, imx93_blk_ctrl_of_match);
438*e2ad626fSUlf Hansson
439*e2ad626fSUlf Hansson static struct platform_driver imx93_blk_ctrl_driver = {
440*e2ad626fSUlf Hansson .probe = imx93_blk_ctrl_probe,
441*e2ad626fSUlf Hansson .remove = imx93_blk_ctrl_remove,
442*e2ad626fSUlf Hansson .driver = {
443*e2ad626fSUlf Hansson .name = "imx93-blk-ctrl",
444*e2ad626fSUlf Hansson .of_match_table = imx93_blk_ctrl_of_match,
445*e2ad626fSUlf Hansson },
446*e2ad626fSUlf Hansson };
447*e2ad626fSUlf Hansson module_platform_driver(imx93_blk_ctrl_driver);
448*e2ad626fSUlf Hansson
449*e2ad626fSUlf Hansson MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
450*e2ad626fSUlf Hansson MODULE_DESCRIPTION("i.MX93 BLK CTRL driver");
451*e2ad626fSUlf Hansson MODULE_LICENSE("GPL");
452