1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Primary to Sideband (P2SB) bridge access support 4 * 5 * Copyright (c) 2017, 2021-2022 Intel Corporation. 6 * 7 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8 * Jonathan Yong <jonathan.yong@intel.com> 9 */ 10 11 #include <linux/bits.h> 12 #include <linux/export.h> 13 #include <linux/pci.h> 14 #include <linux/platform_data/x86/p2sb.h> 15 16 #include <asm/cpu_device_id.h> 17 #include <asm/intel-family.h> 18 19 #define P2SBC 0xe0 20 #define P2SBC_HIDE BIT(8) 21 22 #define P2SB_DEVFN_DEFAULT PCI_DEVFN(31, 1) 23 #define P2SB_DEVFN_GOLDMONT PCI_DEVFN(13, 0) 24 #define SPI_DEVFN_GOLDMONT PCI_DEVFN(13, 2) 25 26 static const struct x86_cpu_id p2sb_cpu_ids[] = { 27 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT), 28 {} 29 }; 30 31 /* 32 * Cache BAR0 of P2SB device functions 0 to 7. 33 * TODO: The constant 8 is the number of functions that PCI specification 34 * defines. Same definitions exist tree-wide. Unify this definition and 35 * the other definitions then move to include/uapi/linux/pci.h. 36 */ 37 #define NR_P2SB_RES_CACHE 8 38 39 struct p2sb_res_cache { 40 u32 bus_dev_id; 41 struct resource res; 42 }; 43 44 static struct p2sb_res_cache p2sb_resources[NR_P2SB_RES_CACHE]; 45 46 static int p2sb_get_devfn(unsigned int *devfn) 47 { 48 unsigned int fn = P2SB_DEVFN_DEFAULT; 49 const struct x86_cpu_id *id; 50 51 id = x86_match_cpu(p2sb_cpu_ids); 52 if (id) 53 fn = (unsigned int)id->driver_data; 54 55 *devfn = fn; 56 return 0; 57 } 58 59 static bool p2sb_valid_resource(const struct resource *res) 60 { 61 return res->flags & ~IORESOURCE_UNSET; 62 } 63 64 /* Copy resource from the first BAR of the device in question */ 65 static void p2sb_read_bar0(struct pci_dev *pdev, struct resource *mem) 66 { 67 struct resource *bar0 = &pdev->resource[0]; 68 69 /* Make sure we have no dangling pointers in the output */ 70 memset(mem, 0, sizeof(*mem)); 71 72 /* 73 * We copy only selected fields from the original resource. 74 * Because a PCI device will be removed soon, we may not use 75 * any allocated data, hence we may not copy any pointers. 76 */ 77 mem->start = bar0->start; 78 mem->end = bar0->end; 79 mem->flags = bar0->flags; 80 mem->desc = bar0->desc; 81 } 82 83 static void p2sb_scan_and_cache_devfn(struct pci_bus *bus, unsigned int devfn) 84 { 85 struct p2sb_res_cache *cache = &p2sb_resources[PCI_FUNC(devfn)]; 86 struct pci_dev *pdev; 87 88 pdev = pci_scan_single_device(bus, devfn); 89 if (!pdev) 90 return; 91 92 p2sb_read_bar0(pdev, &cache->res); 93 cache->bus_dev_id = bus->dev.id; 94 95 pci_stop_and_remove_bus_device(pdev); 96 } 97 98 static int p2sb_scan_and_cache(struct pci_bus *bus, unsigned int devfn) 99 { 100 /* Scan the P2SB device and cache its BAR0 */ 101 p2sb_scan_and_cache_devfn(bus, devfn); 102 103 /* On Goldmont p2sb_bar() also gets called for the SPI controller */ 104 if (devfn == P2SB_DEVFN_GOLDMONT) 105 p2sb_scan_and_cache_devfn(bus, SPI_DEVFN_GOLDMONT); 106 107 if (!p2sb_valid_resource(&p2sb_resources[PCI_FUNC(devfn)].res)) 108 return -ENOENT; 109 110 return 0; 111 } 112 113 static struct pci_bus *p2sb_get_bus(struct pci_bus *bus) 114 { 115 static struct pci_bus *p2sb_bus; 116 117 bus = bus ?: p2sb_bus; 118 if (bus) 119 return bus; 120 121 /* Assume P2SB is on the bus 0 in domain 0 */ 122 p2sb_bus = pci_find_bus(0, 0); 123 return p2sb_bus; 124 } 125 126 static int p2sb_cache_resources(void) 127 { 128 unsigned int devfn_p2sb; 129 u32 value = P2SBC_HIDE; 130 struct pci_bus *bus; 131 u16 class; 132 int ret; 133 134 /* Get devfn for P2SB device itself */ 135 ret = p2sb_get_devfn(&devfn_p2sb); 136 if (ret) 137 return ret; 138 139 bus = p2sb_get_bus(NULL); 140 if (!bus) 141 return -ENODEV; 142 143 /* 144 * When a device with same devfn exists and its device class is not 145 * PCI_CLASS_MEMORY_OTHER for P2SB, do not touch it. 146 */ 147 pci_bus_read_config_word(bus, devfn_p2sb, PCI_CLASS_DEVICE, &class); 148 if (!PCI_POSSIBLE_ERROR(class) && class != PCI_CLASS_MEMORY_OTHER) 149 return -ENODEV; 150 151 /* 152 * Prevent concurrent PCI bus scan from seeing the P2SB device and 153 * removing via sysfs while it is temporarily exposed. 154 */ 155 pci_lock_rescan_remove(); 156 157 /* 158 * The BIOS prevents the P2SB device from being enumerated by the PCI 159 * subsystem, so we need to unhide and hide it back to lookup the BAR. 160 * Unhide the P2SB device here, if needed. 161 */ 162 pci_bus_read_config_dword(bus, devfn_p2sb, P2SBC, &value); 163 if (value & P2SBC_HIDE) 164 pci_bus_write_config_dword(bus, devfn_p2sb, P2SBC, 0); 165 166 ret = p2sb_scan_and_cache(bus, devfn_p2sb); 167 168 /* Hide the P2SB device, if it was hidden */ 169 if (value & P2SBC_HIDE) 170 pci_bus_write_config_dword(bus, devfn_p2sb, P2SBC, P2SBC_HIDE); 171 172 pci_unlock_rescan_remove(); 173 174 return ret; 175 } 176 177 /** 178 * p2sb_bar - Get Primary to Sideband (P2SB) bridge device BAR 179 * @bus: PCI bus to communicate with 180 * @devfn: PCI slot and function to communicate with 181 * @mem: memory resource to be filled in 182 * 183 * If @bus is NULL, the bus 0 in domain 0 will be used. 184 * If @devfn is 0, it will be replaced by devfn of the P2SB device. 185 * 186 * Caller must provide a valid pointer to @mem. 187 * 188 * Return: 189 * 0 on success or appropriate errno value on error. 190 */ 191 int p2sb_bar(struct pci_bus *bus, unsigned int devfn, struct resource *mem) 192 { 193 struct p2sb_res_cache *cache; 194 int ret; 195 196 bus = p2sb_get_bus(bus); 197 if (!bus) 198 return -ENODEV; 199 200 if (!devfn) { 201 ret = p2sb_get_devfn(&devfn); 202 if (ret) 203 return ret; 204 } 205 206 cache = &p2sb_resources[PCI_FUNC(devfn)]; 207 if (cache->bus_dev_id != bus->dev.id) 208 return -ENODEV; 209 210 if (!p2sb_valid_resource(&cache->res)) 211 return -ENOENT; 212 213 memcpy(mem, &cache->res, sizeof(*mem)); 214 return 0; 215 } 216 EXPORT_SYMBOL_GPL(p2sb_bar); 217 218 static int __init p2sb_fs_init(void) 219 { 220 return p2sb_cache_resources(); 221 } 222 223 /* 224 * pci_rescan_remove_lock() can not be locked in sysfs PCI bus rescan path 225 * because of deadlock. To avoid the deadlock, access P2SB devices with the lock 226 * at an early step in kernel initialization and cache required resources. 227 * 228 * We want to run as early as possible. If the P2SB was assigned a bad BAR, 229 * we'll need to wait on pcibios_assign_resources() to fix it. So, our list of 230 * initcall dependencies looks something like this: 231 * 232 * ... 233 * subsys_initcall (pci_subsys_init) 234 * fs_initcall (pcibios_assign_resources) 235 */ 236 fs_initcall_sync(p2sb_fs_init); 237